1 /* pcnet32.c: An AMD PCnet32 ethernet driver for linux. */
3 * Copyright 1996-1999 Thomas Bogendoerfer
5 * Derived from the lance driver written 1993,1994,1995 by Donald Becker.
7 * Copyright 1993 United States Government as represented by the
8 * Director, National Security Agency.
10 * This software may be used and distributed according to the terms
11 * of the GNU General Public License, incorporated herein by reference.
13 * This driver is for PCnet32 and PCnetPCI based ethercards
15 /**************************************************************************
17 * Fixed a few bugs, related to running the controller in 32bit mode.
19 * Carsten Langgaard, carstenl@mips.com
20 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
22 *************************************************************************/
24 #define DRV_NAME "pcnet32"
25 #define DRV_VERSION "1.27b"
26 #define DRV_RELDATE "01.10.2002"
27 #define PFX DRV_NAME ": "
29 static const char *version =
30 DRV_NAME ".c:v" DRV_VERSION " " DRV_RELDATE " tsbogend@alpha.franken.de\n";
32 #include <linux/module.h>
34 #include <linux/kernel.h>
35 #include <linux/sched.h>
36 #include <linux/string.h>
37 #include <linux/ptrace.h>
38 #include <linux/errno.h>
39 #include <linux/ioport.h>
40 #include <linux/slab.h>
41 #include <linux/interrupt.h>
42 #include <linux/pci.h>
43 #include <linux/delay.h>
44 #include <linux/init.h>
45 #include <linux/ethtool.h>
46 #include <linux/mii.h>
47 #include <linux/crc32.h>
48 #include <asm/bitops.h>
51 #include <asm/uaccess.h>
53 #include <linux/netdevice.h>
54 #include <linux/etherdevice.h>
55 #include <linux/skbuff.h>
56 #include <linux/spinlock.h>
59 * PCI device identifiers for "new style" Linux PCI Device Drivers
61 static struct pci_device_id pcnet32_pci_tbl[] __devinitdata = {
62 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE_HOME, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
63 { PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_LANCE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
67 MODULE_DEVICE_TABLE (pci, pcnet32_pci_tbl);
69 int cards_found __initdata;
74 static unsigned int pcnet32_portlist[] __initdata =
75 { 0x300, 0x320, 0x340, 0x360, 0 };
79 static int pcnet32_debug = 1;
80 static int tx_start = 1; /* Mapping -- 0:20, 1:64, 2:128, 3:~220 (depends on chip vers) */
81 static int pcnet32vlb; /* check for VLB cards ? */
83 static struct net_device *pcnet32_dev;
85 static int max_interrupt_work = 80;
86 static int rx_copybreak = 200;
88 #define PCNET32_PORT_AUI 0x00
89 #define PCNET32_PORT_10BT 0x01
90 #define PCNET32_PORT_GPSI 0x02
91 #define PCNET32_PORT_MII 0x03
93 #define PCNET32_PORT_PORTSEL 0x03
94 #define PCNET32_PORT_ASEL 0x04
95 #define PCNET32_PORT_100 0x40
96 #define PCNET32_PORT_FD 0x80
98 #define PCNET32_DMA_MASK 0xffffffff
100 #define PCNET32_WATCHDOG_TIMEOUT (jiffies + (2 * HZ))
103 * table to translate option values from tulip
104 * to internal options
106 static unsigned char options_mapping[] = {
107 PCNET32_PORT_ASEL, /* 0 Auto-select */
108 PCNET32_PORT_AUI, /* 1 BNC/AUI */
109 PCNET32_PORT_AUI, /* 2 AUI/BNC */
110 PCNET32_PORT_ASEL, /* 3 not supported */
111 PCNET32_PORT_10BT | PCNET32_PORT_FD, /* 4 10baseT-FD */
112 PCNET32_PORT_ASEL, /* 5 not supported */
113 PCNET32_PORT_ASEL, /* 6 not supported */
114 PCNET32_PORT_ASEL, /* 7 not supported */
115 PCNET32_PORT_ASEL, /* 8 not supported */
116 PCNET32_PORT_MII, /* 9 MII 10baseT */
117 PCNET32_PORT_MII | PCNET32_PORT_FD, /* 10 MII 10baseT-FD */
118 PCNET32_PORT_MII, /* 11 MII (autosel) */
119 PCNET32_PORT_10BT, /* 12 10BaseT */
120 PCNET32_PORT_MII | PCNET32_PORT_100, /* 13 MII 100BaseTx */
121 PCNET32_PORT_MII | PCNET32_PORT_100 | PCNET32_PORT_FD, /* 14 MII 100BaseTx-FD */
122 PCNET32_PORT_ASEL /* 15 not supported */
125 #define MAX_UNITS 8 /* More are supported, limit only on options */
126 static int options[MAX_UNITS];
127 static int full_duplex[MAX_UNITS];
130 * Theory of Operation
132 * This driver uses the same software structure as the normal lance
133 * driver. So look for a verbose description in lance.c. The differences
134 * to the normal lance driver is the use of the 32bit mode of PCnet32
135 * and PCnetPCI chips. Because these chips are 32bit chips, there is no
136 * 16MB limitation and we don't need bounce buffers.
141 * v0.01: Initial version
142 * only tested on Alpha Noname Board
143 * v0.02: changed IRQ handling for new interrupt scheme (dev_id)
144 * tested on a ASUS SP3G
145 * v0.10: fixed an odd problem with the 79C974 in a Compaq Deskpro XL
146 * looks like the 974 doesn't like stopping and restarting in a
147 * short period of time; now we do a reinit of the lance; the
148 * bug was triggered by doing ifconfig eth0 <ip> broadcast <addr>
149 * and hangs the machine (thanks to Klaus Liedl for debugging)
150 * v0.12: by suggestion from Donald Becker: Renamed driver to pcnet32,
151 * made it standalone (no need for lance.c)
152 * v0.13: added additional PCI detecting for special PCI devices (Compaq)
153 * v0.14: stripped down additional PCI probe (thanks to David C Niemi
154 * and sveneric@xs4all.nl for testing this on their Compaq boxes)
155 * v0.15: added 79C965 (VLB) probe
156 * added interrupt sharing for PCI chips
157 * v0.16: fixed set_multicast_list on Alpha machines
158 * v0.17: removed hack from dev.c; now pcnet32 uses ethif_probe in Space.c
159 * v0.19: changed setting of autoselect bit
160 * v0.20: removed additional Compaq PCI probe; there is now a working one
161 * in arch/i386/bios32.c
162 * v0.21: added endian conversion for ppc, from work by cort@cs.nmt.edu
163 * v0.22: added printing of status to ring dump
164 * v0.23: changed enet_statistics to net_devive_stats
165 * v0.90: added multicast filter
166 * added module support
167 * changed irq probe to new style
168 * added PCnetFast chip id
169 * added fix for receive stalls with Intel saturn chipsets
170 * added in-place rx skbs like in the tulip driver
172 * v0.91: added PCnetFast+ chip id
174 * v1.00: added some stuff from Donald Becker's 2.0.34 version
175 * added support for byte counters in net_dev_stats
176 * v1.01: do ring dumps, only when debugging the driver
177 * increased the transmit timeout
178 * v1.02: fixed memory leak in pcnet32_init_ring()
179 * v1.10: workaround for stopped transmitter
180 * added port selection for modules
181 * detect special T1/E1 WAN card and setup port selection
182 * v1.11: fixed wrong checking of Tx errors
183 * v1.20: added check of return value kmalloc (cpeterso@cs.washington.edu)
184 * added save original kmalloc addr for freeing (mcr@solidum.com)
185 * added support for PCnetHome chip (joe@MIT.EDU)
186 * rewritten PCI card detection
187 * added dwio mode to get driver working on some PPC machines
188 * v1.21: added mii selection and mii ioctl
189 * v1.22: changed pci scanning code to make PPC people happy
190 * fixed switching to 32bit mode in pcnet32_open() (thanks
191 * to Michael Richard <mcr@solidum.com> for noticing this one)
192 * added sub vendor/device id matching (thanks again to
193 * Michael Richard <mcr@solidum.com>)
194 * added chip id for 79c973/975 (thanks to Zach Brown <zab@zabbo.net>)
195 * v1.23 fixed small bug, when manual selecting MII speed/duplex
196 * v1.24 Applied Thomas' patch to use TxStartPoint and thus decrease TxFIFO
197 * underflows. Added tx_start_pt module parameter. Increased
198 * TX_RING_SIZE from 16 to 32. Added #ifdef'd code to use DXSUFLO
199 * for FAST[+] chipsets. <kaf@fc.hp.com>
200 * v1.24ac Added SMP spinlocking - Alan Cox <alan@redhat.com>
201 * v1.25kf Added No Interrupt on successful Tx for some Tx's <kaf@fc.hp.com>
202 * v1.26 Converted to pci_alloc_consistent, Jamey Hicks / George France
203 * <jamey@crl.dec.com>
204 * - Fixed a few bugs, related to running the controller in 32bit mode.
205 * 23 Oct, 2000. Carsten Langgaard, carstenl@mips.com
206 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
207 * v1.26p Fix oops on rmmod+insmod; plug i/o resource leak - Paul Gortmaker
208 * v1.27 improved CSR/PROM address detection, lots of cleanups,
209 * new pcnet32vlb module option, HP-PARISC support,
210 * added module parameter descriptions,
211 * initial ethtool support - Helge Deller <deller@gmx.de>
212 * v1.27a Sun Feb 10 2002 Go Taniguchi <go@turbolinux.co.jp>
213 * use alloc_etherdev and register_netdev
214 * fix pci probe not increment cards_found
215 * FD auto negotiate error workaround for xSeries250
216 * clean up and using new mii module
217 * v1.27b Sep 30 2002 Kent Yoder <yoder1@us.ibm.com>
218 * Added timer for cable connection state changes.
223 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
224 * Reasonable default values are 4 Tx buffers, and 16 Rx buffers.
225 * That translates to 2 (4 == 2^^2) and 4 (16 == 2^^4).
227 #ifndef PCNET32_LOG_TX_BUFFERS
228 #define PCNET32_LOG_TX_BUFFERS 4
229 #define PCNET32_LOG_RX_BUFFERS 5
232 #define TX_RING_SIZE (1 << (PCNET32_LOG_TX_BUFFERS))
233 #define TX_RING_MOD_MASK (TX_RING_SIZE - 1)
234 #define TX_RING_LEN_BITS ((PCNET32_LOG_TX_BUFFERS) << 12)
236 #define RX_RING_SIZE (1 << (PCNET32_LOG_RX_BUFFERS))
237 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1)
238 #define RX_RING_LEN_BITS ((PCNET32_LOG_RX_BUFFERS) << 4)
240 #define PKT_BUF_SZ 1544
242 /* Offsets from base I/O address. */
243 #define PCNET32_WIO_RDP 0x10
244 #define PCNET32_WIO_RAP 0x12
245 #define PCNET32_WIO_RESET 0x14
246 #define PCNET32_WIO_BDP 0x16
248 #define PCNET32_DWIO_RDP 0x10
249 #define PCNET32_DWIO_RAP 0x14
250 #define PCNET32_DWIO_RESET 0x18
251 #define PCNET32_DWIO_BDP 0x1C
253 #define PCNET32_TOTAL_SIZE 0x20
255 /* The PCNET32 Rx and Tx ring descriptors. */
256 struct pcnet32_rx_head {
264 struct pcnet32_tx_head {
272 /* The PCNET32 32-Bit initialization block, described in databook. */
273 struct pcnet32_init_block {
279 /* Receive and transmit ring base, along with extra bits. */
284 /* PCnet32 access functions */
285 struct pcnet32_access {
286 u16 (*read_csr)(unsigned long, int);
287 void (*write_csr)(unsigned long, int, u16);
288 u16 (*read_bcr)(unsigned long, int);
289 void (*write_bcr)(unsigned long, int, u16);
290 u16 (*read_rap)(unsigned long);
291 void (*write_rap)(unsigned long, u16);
292 void (*reset)(unsigned long);
296 * The first three fields of pcnet32_private are read by the ethernet device
297 * so we allocate the structure should be allocated by pci_alloc_consistent().
299 struct pcnet32_private {
300 /* The Tx and Rx ring entries must be aligned on 16-byte boundaries in 32bit mode. */
301 struct pcnet32_rx_head rx_ring[RX_RING_SIZE];
302 struct pcnet32_tx_head tx_ring[TX_RING_SIZE];
303 struct pcnet32_init_block init_block;
304 dma_addr_t dma_addr; /* DMA address of beginning of this object,
305 returned by pci_alloc_consistent */
306 struct pci_dev *pci_dev; /* Pointer to the associated pci device structure */
308 /* The saved address of a sent-in-place packet/buffer, for skfree(). */
309 struct sk_buff *tx_skbuff[TX_RING_SIZE];
310 struct sk_buff *rx_skbuff[RX_RING_SIZE];
311 dma_addr_t tx_dma_addr[TX_RING_SIZE];
312 dma_addr_t rx_dma_addr[RX_RING_SIZE];
313 struct pcnet32_access a;
314 spinlock_t lock; /* Guard lock */
315 unsigned int cur_rx, cur_tx; /* The next free ring entry */
316 unsigned int dirty_rx, dirty_tx; /* The ring entries to be free()ed. */
317 struct net_device_stats stats;
320 int shared_irq:1, /* shared irq possible */
321 ltint:1, /* enable TxDone-intr inhibitor */
322 dxsuflo:1, /* disable transmit stop on uflo */
323 mii:1; /* mii port available */
324 struct net_device *next;
325 struct mii_if_info mii_if;
326 struct timer_list watchdog_timer;
329 static void pcnet32_probe_vlbus(void);
330 static int pcnet32_probe_pci(struct pci_dev *, const struct pci_device_id *);
331 static int pcnet32_probe1(unsigned long, unsigned int, int, struct pci_dev *);
332 static int pcnet32_open(struct net_device *);
333 static int pcnet32_init_ring(struct net_device *);
334 static int pcnet32_start_xmit(struct sk_buff *, struct net_device *);
335 static int pcnet32_rx(struct net_device *);
336 static void pcnet32_tx_timeout (struct net_device *dev);
337 static void pcnet32_interrupt(int, void *, struct pt_regs *);
338 static int pcnet32_close(struct net_device *);
339 static struct net_device_stats *pcnet32_get_stats(struct net_device *);
340 static void pcnet32_set_multicast_list(struct net_device *);
341 static int pcnet32_ioctl(struct net_device *, struct ifreq *, int);
342 static void pcnet32_watchdog(struct net_device *);
343 static int mdio_read(struct net_device *dev, int phy_id, int reg_num);
344 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val);
347 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
348 PCI_ADDR0=0x10<<0, PCI_ADDR1=0x10<<1, PCI_ADDR2=0x10<<2, PCI_ADDR3=0x10<<3,
352 static u16 pcnet32_wio_read_csr (unsigned long addr, int index)
354 outw (index, addr+PCNET32_WIO_RAP);
355 return inw (addr+PCNET32_WIO_RDP);
358 static void pcnet32_wio_write_csr (unsigned long addr, int index, u16 val)
360 outw (index, addr+PCNET32_WIO_RAP);
361 outw (val, addr+PCNET32_WIO_RDP);
364 static u16 pcnet32_wio_read_bcr (unsigned long addr, int index)
366 outw (index, addr+PCNET32_WIO_RAP);
367 return inw (addr+PCNET32_WIO_BDP);
370 static void pcnet32_wio_write_bcr (unsigned long addr, int index, u16 val)
372 outw (index, addr+PCNET32_WIO_RAP);
373 outw (val, addr+PCNET32_WIO_BDP);
376 static u16 pcnet32_wio_read_rap (unsigned long addr)
378 return inw (addr+PCNET32_WIO_RAP);
381 static void pcnet32_wio_write_rap (unsigned long addr, u16 val)
383 outw (val, addr+PCNET32_WIO_RAP);
386 static void pcnet32_wio_reset (unsigned long addr)
388 inw (addr+PCNET32_WIO_RESET);
391 static int pcnet32_wio_check (unsigned long addr)
393 outw (88, addr+PCNET32_WIO_RAP);
394 return (inw (addr+PCNET32_WIO_RAP) == 88);
397 static struct pcnet32_access pcnet32_wio = {
398 read_csr: pcnet32_wio_read_csr,
399 write_csr: pcnet32_wio_write_csr,
400 read_bcr: pcnet32_wio_read_bcr,
401 write_bcr: pcnet32_wio_write_bcr,
402 read_rap: pcnet32_wio_read_rap,
403 write_rap: pcnet32_wio_write_rap,
404 reset: pcnet32_wio_reset
407 static u16 pcnet32_dwio_read_csr (unsigned long addr, int index)
409 outl (index, addr+PCNET32_DWIO_RAP);
410 return (inl (addr+PCNET32_DWIO_RDP) & 0xffff);
413 static void pcnet32_dwio_write_csr (unsigned long addr, int index, u16 val)
415 outl (index, addr+PCNET32_DWIO_RAP);
416 outl (val, addr+PCNET32_DWIO_RDP);
419 static u16 pcnet32_dwio_read_bcr (unsigned long addr, int index)
421 outl (index, addr+PCNET32_DWIO_RAP);
422 return (inl (addr+PCNET32_DWIO_BDP) & 0xffff);
425 static void pcnet32_dwio_write_bcr (unsigned long addr, int index, u16 val)
427 outl (index, addr+PCNET32_DWIO_RAP);
428 outl (val, addr+PCNET32_DWIO_BDP);
431 static u16 pcnet32_dwio_read_rap (unsigned long addr)
433 return (inl (addr+PCNET32_DWIO_RAP) & 0xffff);
436 static void pcnet32_dwio_write_rap (unsigned long addr, u16 val)
438 outl (val, addr+PCNET32_DWIO_RAP);
441 static void pcnet32_dwio_reset (unsigned long addr)
443 inl (addr+PCNET32_DWIO_RESET);
446 static int pcnet32_dwio_check (unsigned long addr)
448 outl (88, addr+PCNET32_DWIO_RAP);
449 return ((inl (addr+PCNET32_DWIO_RAP) & 0xffff) == 88);
452 static struct pcnet32_access pcnet32_dwio = {
453 read_csr: pcnet32_dwio_read_csr,
454 write_csr: pcnet32_dwio_write_csr,
455 read_bcr: pcnet32_dwio_read_bcr,
456 write_bcr: pcnet32_dwio_write_bcr,
457 read_rap: pcnet32_dwio_read_rap,
458 write_rap: pcnet32_dwio_write_rap,
459 reset: pcnet32_dwio_reset
464 /* only probes for non-PCI devices, the rest are handled by
465 * pci_register_driver via pcnet32_probe_pci */
467 static void __devinit
468 pcnet32_probe_vlbus(void)
470 unsigned long ioaddr = 0; // FIXME dev ? dev->base_addr: 0;
472 unsigned int irq_line = 0; // FIXME dev ? dev->irq : 0;
476 printk(KERN_INFO "pcnet32_probe_vlbus: cards_found=%d\n", cards_found);
478 if (ioaddr > 0x1ff) {
479 if (check_region(ioaddr, PCNET32_TOTAL_SIZE) == 0)
480 return pcnet32_probe1(ioaddr, irq_line, 0, NULL);
488 /* now look for PCnet32 VLB cards */
489 for (port = pcnet32_portlist; *port; port++) {
490 unsigned long ioaddr = *port;
492 if ( check_region(ioaddr, PCNET32_TOTAL_SIZE) == 0) {
493 /* check if there is really a pcnet chip on that ioaddr */
494 if ((inb(ioaddr + 14) == 0x57) && (inb(ioaddr + 15) == 0x57))
495 pcnet32_probe1(ioaddr, 0, 0, NULL);
502 pcnet32_probe_pci(struct pci_dev *pdev, const struct pci_device_id *ent)
504 unsigned long ioaddr;
507 err = pci_enable_device(pdev);
509 printk(KERN_ERR PFX "failed to enable device -- err=%d\n", err);
512 pci_set_master(pdev);
514 ioaddr = pci_resource_start (pdev, 0);
516 printk (KERN_ERR PFX "card has no PCI IO resources, aborting\n");
520 if (!pci_dma_supported(pdev, PCNET32_DMA_MASK)) {
521 printk(KERN_ERR PFX "architecture does not support 32bit PCI busmaster DMA\n");
525 return pcnet32_probe1(ioaddr, pdev->irq, 1, pdev);
530 * Called from both pcnet32_probe_vlbus and pcnet_probe_pci.
531 * pdev will be NULL when called from pcnet32_probe_vlbus.
534 pcnet32_probe1(unsigned long ioaddr, unsigned int irq_line, int shared,
535 struct pci_dev *pdev)
537 struct pcnet32_private *lp;
538 dma_addr_t lp_dma_addr;
540 int fdx, mii, fset, dxsuflo, ltint;
543 struct net_device *dev;
544 struct pcnet32_access *a = NULL;
548 pcnet32_wio_reset(ioaddr);
550 /* NOTE: 16-bit check is first, otherwise some older PCnet chips fail */
551 if (pcnet32_wio_read_csr(ioaddr, 0) == 4 && pcnet32_wio_check(ioaddr)) {
554 pcnet32_dwio_reset(ioaddr);
555 if (pcnet32_dwio_read_csr(ioaddr, 0) == 4 && pcnet32_dwio_check(ioaddr)) {
558 printk(KERN_INFO "pcnet32: probe at %lx failed\n", ioaddr);
563 chip_version = a->read_csr(ioaddr, 88) | (a->read_csr(ioaddr,89) << 16);
564 if (pcnet32_debug > 2)
565 printk(KERN_INFO " PCnet chip version is %#x.\n", chip_version);
566 if ((chip_version & 0xfff) != 0x003)
569 /* initialize variables */
570 fdx = mii = fset = dxsuflo = ltint = 0;
571 chip_version = (chip_version >> 12) & 0xffff;
573 switch (chip_version) {
575 chipname = "PCnet/PCI 79C970"; /* PCI */
579 chipname = "PCnet/PCI 79C970"; /* 970 gives the wrong chip id back */
581 chipname = "PCnet/32 79C965"; /* 486/VL bus */
584 chipname = "PCnet/PCI II 79C970A"; /* PCI */
588 chipname = "PCnet/FAST 79C971"; /* PCI */
589 fdx = 1; mii = 1; fset = 1;
593 chipname = "PCnet/FAST+ 79C972"; /* PCI */
594 fdx = 1; mii = 1; fset = 1;
597 chipname = "PCnet/FAST III 79C973"; /* PCI */
601 chipname = "PCnet/Home 79C978"; /* PCI */
604 * This is based on specs published at www.amd.com. This section
605 * assumes that a card with a 79C978 wants to go into 1Mb HomePNA
606 * mode. The 79C978 can also go into standard ethernet, and there
607 * probably should be some sort of module option to select the
608 * mode by which the card should operate
610 /* switch to home wiring mode */
611 media = a->read_bcr(ioaddr, 49);
613 if (pcnet32_debug > 2)
614 printk(KERN_DEBUG PFX "media value %#x.\n", media);
618 if (pcnet32_debug > 2)
619 printk(KERN_DEBUG PFX "media reset to %#x.\n", media);
620 a->write_bcr(ioaddr, 49, media);
623 chipname = "PCnet/FAST III 79C975"; /* PCI */
627 printk(KERN_INFO PFX "PCnet version %#x, no PCnet32 chip.\n",
633 * On selected chips turn on the BCR18:NOUFLO bit. This stops transmit
634 * starting until the packet is loaded. Strike one for reliability, lose
635 * one for latency - although on PCI this isnt a big loss. Older chips
636 * have FIFO's smaller than a packet, so you can't do this.
641 a->write_bcr(ioaddr, 18, (a->read_bcr(ioaddr, 18) | 0x0800));
642 a->write_csr(ioaddr, 80, (a->read_csr(ioaddr, 80) & 0x0C00) | 0x0c00);
647 dev = alloc_etherdev(0);
651 printk(KERN_INFO PFX "%s at %#3lx,", chipname, ioaddr);
653 /* In most chips, after a chip reset, the ethernet address is read from the
654 * station address PROM at the base address and programmed into the
655 * "Physical Address Registers" CSR12-14.
656 * As a precautionary measure, we read the PROM values and complain if
657 * they disagree with the CSRs. Either way, we use the CSR values, and
658 * double check that they are valid.
660 for (i = 0; i < 3; i++) {
662 val = a->read_csr(ioaddr, i+12) & 0x0ffff;
663 /* There may be endianness issues here. */
664 dev->dev_addr[2*i] = val & 0x0ff;
665 dev->dev_addr[2*i+1] = (val >> 8) & 0x0ff;
668 /* read PROM address and compare with CSR address */
669 for (i = 0; i < 6; i++)
670 promaddr[i] = inb(ioaddr + i);
672 if( memcmp( promaddr, dev->dev_addr, 6)
673 || !is_valid_ether_addr(dev->dev_addr) ) {
675 if( is_valid_ether_addr(promaddr) ){
677 if( !is_valid_ether_addr(dev->dev_addr)
678 && is_valid_ether_addr(promaddr)) {
680 printk(" warning: CSR address invalid,\n");
681 printk(KERN_INFO " using instead PROM address of");
682 memcpy(dev->dev_addr, promaddr, 6);
686 /* if the ethernet address is not valid, force to 00:00:00:00:00:00 */
687 if( !is_valid_ether_addr(dev->dev_addr) )
688 memset(dev->dev_addr, 0, sizeof(dev->dev_addr));
690 for (i = 0; i < 6; i++)
691 printk(" %2.2x", dev->dev_addr[i] );
693 if (((chip_version + 1) & 0xfffe) == 0x2624) { /* Version 0x2623 or 0x2624 */
694 i = a->read_csr(ioaddr, 80) & 0x0C00; /* Check tx_start_pt */
695 printk("\n" KERN_INFO " tx_start_pt(0x%04x):",i);
697 case 0: printk(" 20 bytes,"); break;
698 case 1: printk(" 64 bytes,"); break;
699 case 2: printk(" 128 bytes,"); break;
700 case 3: printk("~220 bytes,"); break;
702 i = a->read_bcr(ioaddr, 18); /* Check Burst/Bus control */
703 printk(" BCR18(%x):",i&0xffff);
704 if (i & (1<<5)) printk("BurstWrEn ");
705 if (i & (1<<6)) printk("BurstRdEn ");
706 if (i & (1<<7)) printk("DWordIO ");
707 if (i & (1<<11)) printk("NoUFlow ");
708 i = a->read_bcr(ioaddr, 25);
709 printk("\n" KERN_INFO " SRAMSIZE=0x%04x,",i<<8);
710 i = a->read_bcr(ioaddr, 26);
711 printk(" SRAM_BND=0x%04x,",i<<8);
712 i = a->read_bcr(ioaddr, 27);
713 if (i & (1<<14)) printk("LowLatRx");
716 dev->base_addr = ioaddr;
717 if (request_region(ioaddr, PCNET32_TOTAL_SIZE, chipname) == NULL)
720 /* pci_alloc_consistent returns page-aligned memory, so we do not have to check the alignment */
721 if ((lp = pci_alloc_consistent(pdev, sizeof(*lp), &lp_dma_addr)) == NULL) {
722 release_region(ioaddr, PCNET32_TOTAL_SIZE);
726 memset(lp, 0, sizeof(*lp));
727 lp->dma_addr = lp_dma_addr;
730 spin_lock_init(&lp->lock);
734 lp->shared_irq = shared;
735 lp->mii_if.full_duplex = fdx;
736 lp->dxsuflo = dxsuflo;
739 if ((cards_found >= MAX_UNITS) || (options[cards_found] > sizeof(options_mapping)))
740 lp->options = PCNET32_PORT_ASEL;
742 lp->options = options_mapping[options[cards_found]];
743 lp->mii_if.dev = dev;
744 lp->mii_if.mdio_read = mdio_read;
745 lp->mii_if.mdio_write = mdio_write;
747 if (fdx && !(lp->options & PCNET32_PORT_ASEL) &&
748 ((cards_found>=MAX_UNITS) || full_duplex[cards_found]))
749 lp->options |= PCNET32_PORT_FD;
752 printk(KERN_ERR PFX "No access methods\n");
753 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
754 release_region(ioaddr, PCNET32_TOTAL_SIZE);
759 /* detect special T1/E1 WAN card by checking for MAC address */
760 if (dev->dev_addr[0] == 0x00 && dev->dev_addr[1] == 0xe0 && dev->dev_addr[2] == 0x75)
761 lp->options = PCNET32_PORT_FD | PCNET32_PORT_GPSI;
763 lp->init_block.mode = le16_to_cpu(0x0003); /* Disable Rx and Tx. */
764 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
765 for (i = 0; i < 6; i++)
766 lp->init_block.phys_addr[i] = dev->dev_addr[i];
767 lp->init_block.filter[0] = 0x00000000;
768 lp->init_block.filter[1] = 0x00000000;
769 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
770 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
772 /* switch pcnet32 to 32bit mode */
773 a->write_bcr (ioaddr, 20, 2);
775 a->write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) & 0xffff);
776 a->write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
783 printk(" assigned IRQ %d.\n", dev->irq);
785 unsigned long irq_mask = probe_irq_on();
788 * To auto-IRQ we enable the initialization-done and DMA error
789 * interrupts. For ISA boards we get a DMA error, but VLB and PCI
792 /* Trigger an initialization just for the interrupt. */
793 a->write_csr (ioaddr, 0, 0x41);
796 dev->irq = probe_irq_off (irq_mask);
798 printk(", probed IRQ %d.\n", dev->irq);
800 printk(", failed to detect IRQ line.\n");
801 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
802 release_region(ioaddr, PCNET32_TOTAL_SIZE);
807 /* Set the mii phy_id so that we can query the link state */
809 lp->mii_if.phy_id = ((lp->a.read_bcr (ioaddr, 33)) >> 5) & 0x1f;
811 init_timer (&lp->watchdog_timer);
812 lp->watchdog_timer.data = (unsigned long) dev;
813 lp->watchdog_timer.function = (void *) &pcnet32_watchdog;
815 /* The PCNET32-specific entries in the device structure. */
816 dev->open = &pcnet32_open;
817 dev->hard_start_xmit = &pcnet32_start_xmit;
818 dev->stop = &pcnet32_close;
819 dev->get_stats = &pcnet32_get_stats;
820 dev->set_multicast_list = &pcnet32_set_multicast_list;
821 dev->do_ioctl = &pcnet32_ioctl;
822 dev->tx_timeout = pcnet32_tx_timeout;
823 dev->watchdog_timeo = (5*HZ);
825 lp->next = pcnet32_dev;
828 /* Fill in the generic fields of the device structure. */
829 register_netdev(dev);
830 printk(KERN_INFO "%s: registered as %s\n",dev->name, lp->name);
837 pcnet32_open(struct net_device *dev)
839 struct pcnet32_private *lp = dev->priv;
840 unsigned long ioaddr = dev->base_addr;
845 request_irq(dev->irq, &pcnet32_interrupt,
846 lp->shared_irq ? SA_SHIRQ : 0, lp->name, (void *)dev)) {
850 /* Check for a valid station address */
851 if( !is_valid_ether_addr(dev->dev_addr) )
854 /* Reset the PCNET32 */
855 lp->a.reset (ioaddr);
857 /* switch pcnet32 to 32bit mode */
858 lp->a.write_bcr (ioaddr, 20, 2);
860 if (pcnet32_debug > 1)
861 printk(KERN_DEBUG "%s: pcnet32_open() irq %d tx/rx rings %#x/%#x init %#x.\n",
863 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, tx_ring)),
864 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, rx_ring)),
865 (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)));
867 /* set/reset autoselect bit */
868 val = lp->a.read_bcr (ioaddr, 2) & ~2;
869 if (lp->options & PCNET32_PORT_ASEL)
871 lp->a.write_bcr (ioaddr, 2, val);
873 /* handle full duplex setting */
874 if (lp->mii_if.full_duplex) {
875 val = lp->a.read_bcr (ioaddr, 9) & ~3;
876 if (lp->options & PCNET32_PORT_FD) {
878 if (lp->options == (PCNET32_PORT_FD | PCNET32_PORT_AUI))
880 } else if (lp->options & PCNET32_PORT_ASEL) {
881 /* workaround of xSeries250, turn on for 79C975 only */
882 i = ((lp->a.read_csr(ioaddr, 88) | (lp->a.read_csr(ioaddr,89) << 16)) >> 12) & 0xffff;
883 if (i == 0x2627) val |= 3;
885 lp->a.write_bcr (ioaddr, 9, val);
888 /* set/reset GPSI bit in test register */
889 val = lp->a.read_csr (ioaddr, 124) & ~0x10;
890 if ((lp->options & PCNET32_PORT_PORTSEL) == PCNET32_PORT_GPSI)
892 lp->a.write_csr (ioaddr, 124, val);
894 if (lp->mii && !(lp->options & PCNET32_PORT_ASEL)) {
895 val = lp->a.read_bcr (ioaddr, 32) & ~0x38; /* disable Auto Negotiation, set 10Mpbs, HD */
896 if (lp->options & PCNET32_PORT_FD)
898 if (lp->options & PCNET32_PORT_100)
900 lp->a.write_bcr (ioaddr, 32, val);
902 if (lp->options & PCNET32_PORT_ASEL) { /* enable auto negotiate, setup, disable fd */
903 val = lp->a.read_bcr(ioaddr, 32) & ~0x98;
905 lp->a.write_bcr(ioaddr, 32, val);
910 if (lp->dxsuflo) { /* Disable transmit stop on underflow */
911 val = lp->a.read_csr (ioaddr, 3);
913 lp->a.write_csr (ioaddr, 3, val);
917 if (lp->ltint) { /* Enable TxDone-intr inhibitor */
918 val = lp->a.read_csr (ioaddr, 5);
920 lp->a.write_csr (ioaddr, 5, val);
923 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
924 lp->init_block.filter[0] = 0x00000000;
925 lp->init_block.filter[1] = 0x00000000;
926 if (pcnet32_init_ring(dev))
929 /* Re-initialize the PCNET32, and start it when done. */
930 lp->a.write_csr (ioaddr, 1, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) &0xffff);
931 lp->a.write_csr (ioaddr, 2, (lp->dma_addr + offsetof(struct pcnet32_private, init_block)) >> 16);
933 lp->a.write_csr (ioaddr, 4, 0x0915);
934 lp->a.write_csr (ioaddr, 0, 0x0001);
936 netif_start_queue(dev);
938 /* If we have mii, print the link status and start the watchdog */
940 mii_check_media (&lp->mii_if, 1, 1);
941 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
946 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
949 * We used to clear the InitDone bit, 0x0100, here but Mark Stockton
950 * reports that doing so triggers a bug in the '974.
952 lp->a.write_csr (ioaddr, 0, 0x0042);
954 if (pcnet32_debug > 2)
955 printk(KERN_DEBUG "%s: pcnet32 open after %d ticks, init block %#x csr0 %4.4x.\n",
956 dev->name, i, (u32) (lp->dma_addr + offsetof(struct pcnet32_private, init_block)),
957 lp->a.read_csr(ioaddr, 0));
962 return 0; /* Always succeed */
966 * The LANCE has been halted for one reason or another (busmaster memory
967 * arbitration error, Tx FIFO underflow, driver stopped it to reconfigure,
968 * etc.). Modern LANCE variants always reload their ring-buffer
969 * configuration when restarted, so we must reinitialize our ring
970 * context before restarting. As part of this reinitialization,
971 * find all packets still on the Tx ring and pretend that they had been
972 * sent (in effect, drop the packets on the floor) - the higher-level
973 * protocols will time out and retransmit. It'd be better to shuffle
974 * these skbs to a temp list and then actually re-Tx them after
975 * restarting the chip, but I'm too lazy to do so right now. dplatt@3do.com
979 pcnet32_purge_tx_ring(struct net_device *dev)
981 struct pcnet32_private *lp = dev->priv;
984 for (i = 0; i < TX_RING_SIZE; i++) {
985 if (lp->tx_skbuff[i]) {
986 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
987 dev_kfree_skb_any(lp->tx_skbuff[i]);
988 lp->tx_skbuff[i] = NULL;
989 lp->tx_dma_addr[i] = 0;
995 /* Initialize the PCNET32 Rx and Tx rings. */
997 pcnet32_init_ring(struct net_device *dev)
999 struct pcnet32_private *lp = dev->priv;
1003 lp->cur_rx = lp->cur_tx = 0;
1004 lp->dirty_rx = lp->dirty_tx = 0;
1006 for (i = 0; i < RX_RING_SIZE; i++) {
1007 struct sk_buff *rx_skbuff = lp->rx_skbuff[i];
1008 if (rx_skbuff == NULL) {
1009 if (!(rx_skbuff = lp->rx_skbuff[i] = dev_alloc_skb (PKT_BUF_SZ))) {
1010 /* there is not much, we can do at this point */
1011 printk(KERN_ERR "%s: pcnet32_init_ring dev_alloc_skb failed.\n",dev->name);
1014 skb_reserve (rx_skbuff, 2);
1016 lp->rx_dma_addr[i] = pci_map_single(lp->pci_dev, rx_skbuff->tail, rx_skbuff->len, PCI_DMA_FROMDEVICE);
1017 lp->rx_ring[i].base = (u32)le32_to_cpu(lp->rx_dma_addr[i]);
1018 lp->rx_ring[i].buf_length = le16_to_cpu(-PKT_BUF_SZ);
1019 lp->rx_ring[i].status = le16_to_cpu(0x8000);
1021 /* The Tx buffer address is filled in as needed, but we do need to clear
1022 the upper ownership bit. */
1023 for (i = 0; i < TX_RING_SIZE; i++) {
1024 lp->tx_ring[i].base = 0;
1025 lp->tx_ring[i].status = 0;
1026 lp->tx_dma_addr[i] = 0;
1029 lp->init_block.tlen_rlen = le16_to_cpu(TX_RING_LEN_BITS | RX_RING_LEN_BITS);
1030 for (i = 0; i < 6; i++)
1031 lp->init_block.phys_addr[i] = dev->dev_addr[i];
1032 lp->init_block.rx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, rx_ring));
1033 lp->init_block.tx_ring = (u32)le32_to_cpu(lp->dma_addr + offsetof(struct pcnet32_private, tx_ring));
1038 pcnet32_restart(struct net_device *dev, unsigned int csr0_bits)
1040 struct pcnet32_private *lp = dev->priv;
1041 unsigned long ioaddr = dev->base_addr;
1044 pcnet32_purge_tx_ring(dev);
1045 if (pcnet32_init_ring(dev))
1049 lp->a.write_csr (ioaddr, 0, 1);
1052 if (lp->a.read_csr (ioaddr, 0) & 0x0100)
1055 lp->a.write_csr (ioaddr, 0, csr0_bits);
1060 pcnet32_tx_timeout (struct net_device *dev)
1062 struct pcnet32_private *lp = dev->priv;
1063 unsigned long ioaddr = dev->base_addr, flags;
1065 spin_lock_irqsave(&lp->lock, flags);
1066 /* Transmitter timeout, serious problems. */
1067 printk(KERN_ERR "%s: transmit timed out, status %4.4x, resetting.\n",
1068 dev->name, lp->a.read_csr(ioaddr, 0));
1069 lp->a.write_csr (ioaddr, 0, 0x0004);
1070 lp->stats.tx_errors++;
1071 if (pcnet32_debug > 2) {
1073 printk(KERN_DEBUG " Ring data dump: dirty_tx %d cur_tx %d%s cur_rx %d.",
1074 lp->dirty_tx, lp->cur_tx, lp->tx_full ? " (full)" : "",
1076 for (i = 0 ; i < RX_RING_SIZE; i++)
1077 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1078 lp->rx_ring[i].base, -lp->rx_ring[i].buf_length,
1079 lp->rx_ring[i].msg_length, (unsigned)lp->rx_ring[i].status);
1080 for (i = 0 ; i < TX_RING_SIZE; i++)
1081 printk("%s %08x %04x %08x %04x", i & 1 ? "" : "\n ",
1082 lp->tx_ring[i].base, -lp->tx_ring[i].length,
1083 lp->tx_ring[i].misc, (unsigned)lp->tx_ring[i].status);
1086 pcnet32_restart(dev, 0x0042);
1088 dev->trans_start = jiffies;
1089 netif_start_queue(dev);
1091 spin_unlock_irqrestore(&lp->lock, flags);
1096 pcnet32_start_xmit(struct sk_buff *skb, struct net_device *dev)
1098 struct pcnet32_private *lp = dev->priv;
1099 unsigned long ioaddr = dev->base_addr;
1102 unsigned long flags;
1104 if (pcnet32_debug > 3) {
1105 printk(KERN_DEBUG "%s: pcnet32_start_xmit() called, csr0 %4.4x.\n",
1106 dev->name, lp->a.read_csr(ioaddr, 0));
1109 spin_lock_irqsave(&lp->lock, flags);
1111 /* Default status -- will not enable Successful-TxDone
1112 * interrupt when that option is available to us.
1116 ((lp->cur_tx - lp->dirty_tx == TX_RING_SIZE/2) ||
1117 (lp->cur_tx - lp->dirty_tx >= TX_RING_SIZE-2)))
1119 /* Enable Successful-TxDone interrupt if we have
1120 * 1/2 of, or nearly all of, our ring buffer Tx'd
1121 * but not yet cleaned up. Thus, most of the time,
1122 * we will not enable Successful-TxDone interrupts.
1127 /* Fill in a Tx ring entry */
1129 /* Mask to ring buffer boundary. */
1130 entry = lp->cur_tx & TX_RING_MOD_MASK;
1132 /* Caution: the write order is important here, set the base address
1133 with the "ownership" bits last. */
1135 lp->tx_ring[entry].length = le16_to_cpu(-skb->len);
1137 lp->tx_ring[entry].misc = 0x00000000;
1139 lp->tx_skbuff[entry] = skb;
1140 lp->tx_dma_addr[entry] = pci_map_single(lp->pci_dev, skb->data, skb->len, PCI_DMA_TODEVICE);
1141 lp->tx_ring[entry].base = (u32)le32_to_cpu(lp->tx_dma_addr[entry]);
1142 lp->tx_ring[entry].status = le16_to_cpu(status);
1145 lp->stats.tx_bytes += skb->len;
1147 /* Trigger an immediate send poll. */
1148 lp->a.write_csr (ioaddr, 0, 0x0048);
1150 dev->trans_start = jiffies;
1152 if (lp->tx_ring[(entry+1) & TX_RING_MOD_MASK].base == 0)
1153 netif_start_queue(dev);
1156 netif_stop_queue(dev);
1158 spin_unlock_irqrestore(&lp->lock, flags);
1162 /* The PCNET32 interrupt handler. */
1164 pcnet32_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1166 struct net_device *dev = dev_id;
1167 struct pcnet32_private *lp;
1168 unsigned long ioaddr;
1170 int boguscnt = max_interrupt_work;
1174 printk (KERN_DEBUG "%s(): irq %d for unknown device\n",
1179 ioaddr = dev->base_addr;
1182 spin_lock(&lp->lock);
1184 rap = lp->a.read_rap(ioaddr);
1185 while ((csr0 = lp->a.read_csr (ioaddr, 0)) & 0x8600 && --boguscnt >= 0) {
1186 /* Acknowledge all of the current interrupt sources ASAP. */
1187 lp->a.write_csr (ioaddr, 0, csr0 & ~0x004f);
1191 if (pcnet32_debug > 5)
1192 printk(KERN_DEBUG "%s: interrupt csr0=%#2.2x new csr=%#2.2x.\n",
1193 dev->name, csr0, lp->a.read_csr (ioaddr, 0));
1195 if (csr0 & 0x0400) /* Rx interrupt */
1198 if (csr0 & 0x0200) { /* Tx-done interrupt */
1199 unsigned int dirty_tx = lp->dirty_tx;
1201 while (dirty_tx < lp->cur_tx) {
1202 int entry = dirty_tx & TX_RING_MOD_MASK;
1203 int status = (short)le16_to_cpu(lp->tx_ring[entry].status);
1206 break; /* It still hasn't been Txed */
1208 lp->tx_ring[entry].base = 0;
1210 if (status & 0x4000) {
1211 /* There was an major error, log it. */
1212 int err_status = le32_to_cpu(lp->tx_ring[entry].misc);
1213 lp->stats.tx_errors++;
1214 if (err_status & 0x04000000) lp->stats.tx_aborted_errors++;
1215 if (err_status & 0x08000000) lp->stats.tx_carrier_errors++;
1216 if (err_status & 0x10000000) lp->stats.tx_window_errors++;
1218 if (err_status & 0x40000000) {
1219 lp->stats.tx_fifo_errors++;
1220 /* Ackk! On FIFO errors the Tx unit is turned off! */
1221 /* Remove this verbosity later! */
1222 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1227 if (err_status & 0x40000000) {
1228 lp->stats.tx_fifo_errors++;
1229 if (! lp->dxsuflo) { /* If controller doesn't recover ... */
1230 /* Ackk! On FIFO errors the Tx unit is turned off! */
1231 /* Remove this verbosity later! */
1232 printk(KERN_ERR "%s: Tx FIFO error! CSR0=%4.4x\n",
1239 if (status & 0x1800)
1240 lp->stats.collisions++;
1241 lp->stats.tx_packets++;
1244 /* We must free the original skb */
1245 if (lp->tx_skbuff[entry]) {
1246 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[entry],
1247 lp->tx_skbuff[entry]->len, PCI_DMA_TODEVICE);
1248 dev_kfree_skb_irq(lp->tx_skbuff[entry]);
1249 lp->tx_skbuff[entry] = 0;
1250 lp->tx_dma_addr[entry] = 0;
1255 if (lp->cur_tx - dirty_tx >= TX_RING_SIZE) {
1256 printk(KERN_ERR "%s: out-of-sync dirty pointer, %d vs. %d, full=%d.\n",
1257 dev->name, dirty_tx, lp->cur_tx, lp->tx_full);
1258 dirty_tx += TX_RING_SIZE;
1262 netif_queue_stopped(dev) &&
1263 dirty_tx > lp->cur_tx - TX_RING_SIZE + 2) {
1264 /* The ring is no longer full, clear tbusy. */
1266 netif_wake_queue (dev);
1268 lp->dirty_tx = dirty_tx;
1271 /* Log misc errors. */
1272 if (csr0 & 0x4000) lp->stats.tx_errors++; /* Tx babble. */
1273 if (csr0 & 0x1000) {
1275 * this happens when our receive ring is full. This shouldn't
1276 * be a problem as we will see normal rx interrupts for the frames
1277 * in the receive ring. But there are some PCI chipsets (I can reproduce
1278 * this on SP3G with Intel saturn chipset) which have sometimes problems
1279 * and will fill up the receive ring with error descriptors. In this
1280 * situation we don't get a rx interrupt, but a missed frame interrupt sooner
1281 * or later. So we try to clean up our receive ring here.
1284 lp->stats.rx_errors++; /* Missed a Rx frame. */
1286 if (csr0 & 0x0800) {
1287 printk(KERN_ERR "%s: Bus master arbitration failure, status %4.4x.\n",
1289 /* unlike for the lance, there is no restart needed */
1293 /* stop the chip to clear the error condition, then restart */
1294 lp->a.write_csr (ioaddr, 0, 0x0004);
1295 pcnet32_restart(dev, 0x0002);
1299 /* Clear any other interrupt, and set interrupt enable. */
1300 lp->a.write_csr (ioaddr, 0, 0x7940);
1301 lp->a.write_rap (ioaddr,rap);
1303 if (pcnet32_debug > 4)
1304 printk(KERN_DEBUG "%s: exiting interrupt, csr0=%#4.4x.\n",
1305 dev->name, lp->a.read_csr (ioaddr, 0));
1307 spin_unlock(&lp->lock);
1311 pcnet32_rx(struct net_device *dev)
1313 struct pcnet32_private *lp = dev->priv;
1314 int entry = lp->cur_rx & RX_RING_MOD_MASK;
1316 /* If we own the next entry, it's a new packet. Send it up. */
1317 while ((short)le16_to_cpu(lp->rx_ring[entry].status) >= 0) {
1318 int status = (short)le16_to_cpu(lp->rx_ring[entry].status) >> 8;
1320 if (status != 0x03) { /* There was an error. */
1322 * There is a tricky error noted by John Murphy,
1323 * <murf@perftech.com> to Russ Nelson: Even with full-sized
1324 * buffers it's possible for a jabber packet to use two
1325 * buffers, with only the last correctly noting the error.
1327 if (status & 0x01) /* Only count a general error at the */
1328 lp->stats.rx_errors++; /* end of a packet.*/
1329 if (status & 0x20) lp->stats.rx_frame_errors++;
1330 if (status & 0x10) lp->stats.rx_over_errors++;
1331 if (status & 0x08) lp->stats.rx_crc_errors++;
1332 if (status & 0x04) lp->stats.rx_fifo_errors++;
1333 lp->rx_ring[entry].status &= le16_to_cpu(0x03ff);
1335 /* Malloc up new buffer, compatible with net-2e. */
1336 short pkt_len = (le32_to_cpu(lp->rx_ring[entry].msg_length) & 0xfff)-4;
1337 struct sk_buff *skb;
1340 printk(KERN_ERR "%s: Runt packet!\n",dev->name);
1341 lp->stats.rx_errors++;
1343 int rx_in_place = 0;
1345 if (pkt_len > rx_copybreak) {
1346 struct sk_buff *newskb;
1348 if ((newskb = dev_alloc_skb (PKT_BUF_SZ))) {
1349 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry], lp->rx_skbuff[entry]->len, PCI_DMA_FROMDEVICE);
1350 skb_reserve (newskb, 2);
1351 skb = lp->rx_skbuff[entry];
1352 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[entry], skb->len, PCI_DMA_FROMDEVICE);
1353 skb_put (skb, pkt_len);
1354 lp->rx_skbuff[entry] = newskb;
1356 lp->rx_dma_addr[entry] =
1357 pci_map_single(lp->pci_dev, newskb->tail,
1358 newskb->len, PCI_DMA_FROMDEVICE);
1359 lp->rx_ring[entry].base = le32_to_cpu(lp->rx_dma_addr[entry]);
1364 skb = dev_alloc_skb(pkt_len+2);
1369 printk(KERN_ERR "%s: Memory squeeze, deferring packet.\n", dev->name);
1370 for (i = 0; i < RX_RING_SIZE; i++)
1371 if ((short)le16_to_cpu(lp->rx_ring[(entry+i) & RX_RING_MOD_MASK].status) < 0)
1374 if (i > RX_RING_SIZE -2) {
1375 lp->stats.rx_dropped++;
1376 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1383 skb_reserve(skb,2); /* 16 byte align */
1384 skb_put(skb,pkt_len); /* Make room */
1385 eth_copy_and_sum(skb,
1386 (unsigned char *)(lp->rx_skbuff[entry]->tail),
1389 lp->stats.rx_bytes += skb->len;
1390 skb->protocol=eth_type_trans(skb,dev);
1392 dev->last_rx = jiffies;
1393 lp->stats.rx_packets++;
1397 * The docs say that the buffer length isn't touched, but Andrew Boyd
1398 * of QNX reports that some revs of the 79C965 clear it.
1400 lp->rx_ring[entry].buf_length = le16_to_cpu(-PKT_BUF_SZ);
1401 lp->rx_ring[entry].status |= le16_to_cpu(0x8000);
1402 entry = (++lp->cur_rx) & RX_RING_MOD_MASK;
1409 pcnet32_close(struct net_device *dev)
1411 unsigned long ioaddr = dev->base_addr;
1412 struct pcnet32_private *lp = dev->priv;
1415 del_timer_sync(&lp->watchdog_timer);
1417 netif_stop_queue(dev);
1419 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1421 if (pcnet32_debug > 1)
1422 printk(KERN_DEBUG "%s: Shutting down ethercard, status was %2.2x.\n",
1423 dev->name, lp->a.read_csr (ioaddr, 0));
1425 /* We stop the PCNET32 here -- it occasionally polls memory if we don't. */
1426 lp->a.write_csr (ioaddr, 0, 0x0004);
1429 * Switch back to 16bit mode to avoid problems with dumb
1430 * DOS packet driver after a warm reboot
1432 lp->a.write_bcr (ioaddr, 20, 4);
1434 free_irq(dev->irq, dev);
1436 /* free all allocated skbuffs */
1437 for (i = 0; i < RX_RING_SIZE; i++) {
1438 lp->rx_ring[i].status = 0;
1439 if (lp->rx_skbuff[i]) {
1440 pci_unmap_single(lp->pci_dev, lp->rx_dma_addr[i], lp->rx_skbuff[i]->len, PCI_DMA_FROMDEVICE);
1441 dev_kfree_skb(lp->rx_skbuff[i]);
1443 lp->rx_skbuff[i] = NULL;
1444 lp->rx_dma_addr[i] = 0;
1447 for (i = 0; i < TX_RING_SIZE; i++) {
1448 if (lp->tx_skbuff[i]) {
1449 pci_unmap_single(lp->pci_dev, lp->tx_dma_addr[i], lp->tx_skbuff[i]->len, PCI_DMA_TODEVICE);
1450 dev_kfree_skb(lp->tx_skbuff[i]);
1452 lp->tx_skbuff[i] = NULL;
1453 lp->tx_dma_addr[i] = 0;
1461 static struct net_device_stats *
1462 pcnet32_get_stats(struct net_device *dev)
1464 struct pcnet32_private *lp = dev->priv;
1465 unsigned long ioaddr = dev->base_addr;
1467 unsigned long flags;
1469 spin_lock_irqsave(&lp->lock, flags);
1470 saved_addr = lp->a.read_rap(ioaddr);
1471 lp->stats.rx_missed_errors = lp->a.read_csr (ioaddr, 112);
1472 lp->a.write_rap(ioaddr, saved_addr);
1473 spin_unlock_irqrestore(&lp->lock, flags);
1478 /* taken from the sunlance driver, which it took from the depca driver */
1479 static void pcnet32_load_multicast (struct net_device *dev)
1481 struct pcnet32_private *lp = dev->priv;
1482 volatile struct pcnet32_init_block *ib = &lp->init_block;
1483 volatile u16 *mcast_table = (u16 *)&ib->filter;
1484 struct dev_mc_list *dmi=dev->mc_list;
1489 /* set all multicast bits */
1490 if (dev->flags & IFF_ALLMULTI){
1491 ib->filter[0] = 0xffffffff;
1492 ib->filter[1] = 0xffffffff;
1495 /* clear the multicast filter */
1500 for (i = 0; i < dev->mc_count; i++){
1501 addrs = dmi->dmi_addr;
1504 /* multicast address? */
1508 crc = ether_crc_le(6, addrs);
1510 mcast_table [crc >> 4] |= 1 << (crc & 0xf);
1517 * Set or clear the multicast filter for this adaptor.
1519 static void pcnet32_set_multicast_list(struct net_device *dev)
1521 unsigned long ioaddr = dev->base_addr, flags;
1522 struct pcnet32_private *lp = dev->priv;
1524 spin_lock_irqsave(&lp->lock, flags);
1525 if (dev->flags&IFF_PROMISC) {
1526 /* Log any net taps. */
1527 printk(KERN_INFO "%s: Promiscuous mode enabled.\n", dev->name);
1528 lp->init_block.mode = le16_to_cpu(0x8000 | (lp->options & PCNET32_PORT_PORTSEL) << 7);
1530 lp->init_block.mode = le16_to_cpu((lp->options & PCNET32_PORT_PORTSEL) << 7);
1531 pcnet32_load_multicast (dev);
1534 lp->a.write_csr (ioaddr, 0, 0x0004); /* Temporarily stop the lance. */
1536 pcnet32_restart(dev, 0x0042); /* Resume normal operation */
1537 spin_unlock_irqrestore(&lp->lock, flags);
1540 static int mdio_read(struct net_device *dev, int phy_id, int reg_num)
1542 struct pcnet32_private *lp = dev->priv;
1543 unsigned long ioaddr = dev->base_addr;
1550 phyaddr = lp->a.read_bcr(ioaddr, 33);
1552 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
1553 val_out = lp->a.read_bcr(ioaddr, 34);
1554 lp->a.write_bcr(ioaddr, 33, phyaddr);
1559 static void mdio_write(struct net_device *dev, int phy_id, int reg_num, int val)
1561 struct pcnet32_private *lp = dev->priv;
1562 unsigned long ioaddr = dev->base_addr;
1568 phyaddr = lp->a.read_bcr(ioaddr, 33);
1570 lp->a.write_bcr(ioaddr, 33, ((phy_id & 0x1f) << 5) | (reg_num & 0x1f));
1571 lp->a.write_bcr(ioaddr, 34, val);
1572 lp->a.write_bcr(ioaddr, 33, phyaddr);
1575 static int pcnet32_ethtool_ioctl (struct net_device *dev, void *useraddr)
1577 struct pcnet32_private *lp = dev->priv;
1581 unsigned long ioaddr = dev->base_addr;
1584 phyaddr = lp->a.read_bcr (ioaddr, 33);
1585 phy_id = (phyaddr >> 5) & 0x1f;
1586 lp->mii_if.phy_id = phy_id;
1589 if (copy_from_user (ðcmd, useraddr, sizeof (ethcmd)))
1593 case ETHTOOL_GDRVINFO: {
1594 struct ethtool_drvinfo info = { ETHTOOL_GDRVINFO };
1595 strcpy (info.driver, DRV_NAME);
1596 strcpy (info.version, DRV_VERSION);
1598 strcpy (info.bus_info, lp->pci_dev->slot_name);
1600 sprintf(info.bus_info, "VLB 0x%lx", dev->base_addr);
1601 if (copy_to_user (useraddr, &info, sizeof (info)))
1607 case ETHTOOL_GSET: {
1608 struct ethtool_cmd ecmd = { ETHTOOL_GSET };
1609 spin_lock_irq(&lp->lock);
1610 mii_ethtool_gset(&lp->mii_if, &ecmd);
1611 spin_unlock_irq(&lp->lock);
1612 if (copy_to_user(useraddr, &ecmd, sizeof(ecmd)))
1617 case ETHTOOL_SSET: {
1619 struct ethtool_cmd ecmd;
1620 if (copy_from_user(&ecmd, useraddr, sizeof(ecmd)))
1622 spin_lock_irq(&lp->lock);
1623 r = mii_ethtool_sset(&lp->mii_if, &ecmd);
1624 spin_unlock_irq(&lp->lock);
1627 /* restart autonegotiation */
1628 case ETHTOOL_NWAY_RST: {
1629 return mii_nway_restart(&lp->mii_if);
1631 /* get link status */
1632 case ETHTOOL_GLINK: {
1633 struct ethtool_value edata = {ETHTOOL_GLINK};
1634 edata.data = mii_link_ok(&lp->mii_if);
1635 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1640 /* get message-level */
1641 case ETHTOOL_GMSGLVL: {
1642 struct ethtool_value edata = {ETHTOOL_GMSGLVL};
1643 edata.data = pcnet32_debug;
1644 if (copy_to_user(useraddr, &edata, sizeof(edata)))
1648 /* set message-level */
1649 case ETHTOOL_SMSGLVL: {
1650 struct ethtool_value edata;
1651 if (copy_from_user(&edata, useraddr, sizeof(edata)))
1653 pcnet32_debug = edata.data;
1663 static int pcnet32_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
1665 unsigned long ioaddr = dev->base_addr;
1666 struct pcnet32_private *lp = dev->priv;
1667 struct mii_ioctl_data *data = (struct mii_ioctl_data *)&rq->ifr_data;
1668 int phyaddr = lp->a.read_bcr (ioaddr, 33);
1670 if (cmd == SIOCETHTOOL)
1671 return pcnet32_ethtool_ioctl(dev, (void *) rq->ifr_data);
1675 case SIOCGMIIPHY: /* Get address of MII PHY in use. */
1676 data->phy_id = (phyaddr >> 5) & 0x1f;
1678 case SIOCGMIIREG: /* Read MII PHY register. */
1679 lp->a.write_bcr (ioaddr, 33, ((data->phy_id & 0x1f) << 5) | (data->reg_num & 0x1f));
1680 data->val_out = lp->a.read_bcr (ioaddr, 34);
1681 lp->a.write_bcr (ioaddr, 33, phyaddr);
1683 case SIOCSMIIREG: /* Write MII PHY register. */
1684 if (!capable(CAP_NET_ADMIN))
1686 lp->a.write_bcr (ioaddr, 33, ((data->phy_id & 0x1f) << 5) | (data->reg_num & 0x1f));
1687 lp->a.write_bcr (ioaddr, 34, data->val_in);
1688 lp->a.write_bcr (ioaddr, 33, phyaddr);
1697 static void pcnet32_watchdog(struct net_device *dev)
1699 struct pcnet32_private *lp = dev->priv;
1701 /* Print the link status if it has changed */
1703 mii_check_media (&lp->mii_if, 1, 0);
1705 mod_timer (&(lp->watchdog_timer), PCNET32_WATCHDOG_TIMEOUT);
1708 static struct pci_driver pcnet32_driver = {
1710 probe: pcnet32_probe_pci,
1711 id_table: pcnet32_pci_tbl,
1714 MODULE_PARM(debug, "i");
1715 MODULE_PARM_DESC(debug, DRV_NAME " debug level (0-6)");
1716 MODULE_PARM(max_interrupt_work, "i");
1717 MODULE_PARM_DESC(max_interrupt_work, DRV_NAME " maximum events handled per interrupt");
1718 MODULE_PARM(rx_copybreak, "i");
1719 MODULE_PARM_DESC(rx_copybreak, DRV_NAME " copy breakpoint for copy-only-tiny-frames");
1720 MODULE_PARM(tx_start_pt, "i");
1721 MODULE_PARM_DESC(tx_start_pt, DRV_NAME " transmit start point (0-3)");
1722 MODULE_PARM(pcnet32vlb, "i");
1723 MODULE_PARM_DESC(pcnet32vlb, DRV_NAME " Vesa local bus (VLB) support (0/1)");
1724 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
1725 MODULE_PARM_DESC(options, DRV_NAME " initial option setting(s) (0-15)");
1726 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
1727 MODULE_PARM_DESC(full_duplex, DRV_NAME " full duplex setting(s) (1)");
1729 MODULE_AUTHOR("Thomas Bogendoerfer");
1730 MODULE_DESCRIPTION("Driver for PCnet32 and PCnetPCI based ethercards");
1731 MODULE_LICENSE("GPL");
1733 /* An additional parameter that may be passed in... */
1734 static int debug = -1;
1735 static int tx_start_pt = -1;
1737 static int __init pcnet32_init_module(void)
1739 printk(KERN_INFO "%s", version);
1742 pcnet32_debug = debug;
1744 if ((tx_start_pt >= 0) && (tx_start_pt <= 3))
1745 tx_start = tx_start_pt;
1747 /* find the PCI devices */
1748 pci_module_init(&pcnet32_driver);
1750 /* should we find any remaining VLbus devices ? */
1752 pcnet32_probe_vlbus();
1755 printk(KERN_INFO PFX "%d cards_found.\n", cards_found);
1757 return cards_found ? 0 : -ENODEV;
1760 static void __exit pcnet32_cleanup_module(void)
1762 struct net_device *next_dev;
1764 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1765 while (pcnet32_dev) {
1766 struct pcnet32_private *lp = pcnet32_dev->priv;
1767 next_dev = lp->next;
1768 unregister_netdev(pcnet32_dev);
1769 release_region(pcnet32_dev->base_addr, PCNET32_TOTAL_SIZE);
1771 pci_unregister_driver(&pcnet32_driver);
1772 pci_free_consistent(lp->pci_dev, sizeof(*lp), lp, lp->dma_addr);
1774 pcnet32_dev = next_dev;
1778 module_init(pcnet32_init_module);
1779 module_exit(pcnet32_cleanup_module);
1783 * compile-command: "gcc -D__KERNEL__ -I/usr/src/linux/net/inet -Wall -Wstrict-prototypes -O6 -m486 -c pcnet32.c"