drivers/net/sb1250-mac.c

   1 /*
   2  * Copyright (C) 2001 Broadcom Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * as published by the Free Software Foundation; either version 2
   7  * of the License, or (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  17  */
  18
  19 /*
  20   This driver is designed for the Broadcom BCM12500 SOC chip's built-in
  21   Ethernet controllers.
  22
  23   The author may be reached as mpl@broadcom.com
  24 */
  25
  26
  27
  28 #define CONFIG_SBMAC_COALESCE
  29
  30 /* A few user-configurable values.
  31    These may be modified when a driver module is loaded. */
  32
  33 static int debug = 1;                   /* 1 normal messages, 0 quiet .. 7 verbose. */
  34
  35 /* Used to pass the media type, etc.
  36    Both 'options[]' and 'full_duplex[]' should exist for driver
  37    interoperability.
  38    The media type is usually passed in 'options[]'.
  39 */
  40
  41 #define MAX_UNITS 3             /* More are supported, limit only on options */
  42 #ifdef MODULE
  43 static int options[MAX_UNITS] = {-1, -1, -1};
  44 static int full_duplex[MAX_UNITS] = {-1, -1, -1};
  45 #endif
  46
  47 static int int_pktcnt = 0;
  48 static int int_timeout = 0;
  49
  50 /* Operational parameters that usually are not changed. */
  51
  52 /* Time in jiffies before concluding the transmitter is hung. */
  53 #define TX_TIMEOUT  (2*HZ)
  54
  55 #if !defined(__OPTIMIZE__)  ||  !defined(__KERNEL__)
  56 #warning  You must compile this file with the correct options!
  57 #warning  See the last lines of the source file.
  58 #error  You must compile this driver with "-O".
  59 #endif
  60
  61 #include <linux/module.h>
  62 #include <linux/kernel.h>
  63 #include <linux/string.h>
  64 #include <linux/timer.h>
  65 #include <linux/errno.h>
  66 #include <linux/ioport.h>
  67 #include <linux/slab.h>
  68 #include <linux/interrupt.h>
  69 #include <linux/netdevice.h>
  70 #include <linux/etherdevice.h>
  71 #include <linux/skbuff.h>
  72 #include <linux/init.h>
  73 #include <linux/config.h>
  74 #include <asm/processor.h>              /* Processor type for cache alignment. */
  75 #include <asm/bitops.h>
  76 #include <asm/io.h>
  77 #include <asm/sibyte/sb1250.h>
  78 #include <asm/sibyte/64bit.h>
  79
  80 /* This is only here until the firmware is ready.  In that case,
  81    the firmware leaves the ethernet address in the register for us. */
  82 #ifdef CONFIG_SIBYTE_STANDALONE
  83 #define SBMAC_ETH0_HWADDR "40:00:00:00:01:00"
  84 #define SBMAC_ETH1_HWADDR "40:00:00:00:01:01"
  85 #define SBMAC_ETH2_HWADDR "40:00:00:00:01:02"
  86 #endif
  87
  88
  89 /* These identify the driver base version and may not be removed. */
  90 #if 0
  91 static char version1[] __devinitdata =
  92 "sb1250-mac.c:1.00 1/11/2001 Written by Mitch Lichtenberg (mpl@broadcom.com)\n";
  93 #endif
  94
  95
  96
  97 MODULE_AUTHOR("Mitch Lichtenberg (mpl@broadcom.com)");
  98 MODULE_DESCRIPTION("Broadcom BCM12500 SOC GB Ethernet driver");
  99 MODULE_PARM(debug, "i");
 100 MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");
 101 MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");
 102
 103 MODULE_PARM(int_pktcnt, "i");
 104 MODULE_PARM(int_timeout, "i");
 105
 106 #include <asm/sibyte/sb1250_defs.h>
 107 #include <asm/sibyte/sb1250_regs.h>
 108 #include <asm/sibyte/sb1250_mac.h>
 109 #include <asm/sibyte/sb1250_dma.h>
 110 #include <asm/sibyte/sb1250_int.h>
 111 #include <asm/sibyte/sb1250_scd.h>              /* Only to check SOC part number. */
 112
 113
 114 /**********************************************************************
 115  *  Simple types
 116  ********************************************************************* */
 117
 118
 119 typedef unsigned long sbmac_port_t;
 120 typedef uint64_t sbmac_physaddr_t;
 121 typedef uint64_t sbmac_enetaddr_t;
 122
 123 typedef enum { sbmac_speed_auto, sbmac_speed_10,
 124                sbmac_speed_100, sbmac_speed_1000 } sbmac_speed_t;
 125
 126 typedef enum { sbmac_duplex_auto, sbmac_duplex_half,
 127                sbmac_duplex_full } sbmac_duplex_t;
 128
 129 typedef enum { sbmac_fc_auto, sbmac_fc_disabled, sbmac_fc_frame,
 130                sbmac_fc_collision, sbmac_fc_carrier } sbmac_fc_t;
 131
 132 typedef enum { sbmac_state_uninit, sbmac_state_off, sbmac_state_on,
 133                sbmac_state_broken } sbmac_state_t;
 134
 135
 136 /**********************************************************************
 137  *  Macros
 138  ********************************************************************* */
 139
 140
 141 #define SBDMA_NEXTBUF(d,f) ((((d)->f+1) == (d)->sbdma_dscrtable_end) ? \
 142                           (d)->sbdma_dscrtable : (d)->f+1)
 143
 144
 145 #define CACHELINESIZE 32
 146 #define NUMCACHEBLKS(x) (((x)+CACHELINESIZE-1)/CACHELINESIZE)
 147 #define KMALLOC(x) kmalloc((x),GFP_KERNEL)
 148 #define KFREE(x) kfree(x)
 149 #define KVTOPHYS(x) virt_to_bus((void *)(x))
 150
 151
 152 #define SBMAC_READCSR(t)    (in64((unsigned long)(t)))
 153 #define SBMAC_WRITECSR(t,v) (out64(v, (unsigned long)(t)))
 154
 155 #define PKSEG1(x) ((sbmac_port_t) KSEG1ADDR(x))
 156
 157 #define SBMAC_MAX_TXDESCR       32
 158 #define SBMAC_MAX_RXDESCR       32
 159
 160 #define ETHER_ALIGN     2
 161 #define ETHER_ADDR_LEN  6
 162 #define ENET_PACKET_SIZE        1518
 163 /*#define ENET_PACKET_SIZE      9216 */
 164
 165 /**********************************************************************
 166  *  DMA Descriptor structure
 167  ********************************************************************* */
 168
 169 typedef struct sbdmadscr_s {
 170         uint64_t  dscr_a;
 171         uint64_t  dscr_b;
 172 } sbdmadscr_t;
 173
 174 typedef unsigned long paddr_t;
 175 typedef unsigned long vaddr_t;
 176
 177 /**********************************************************************
 178  *  DMA Controller structure
 179  ********************************************************************* */
 180
 181 typedef struct sbmacdma_s {
 182
 183         /*
 184          * This stuff is used to identify the channel and the registers
 185          * associated with it.
 186          */
 187
 188         struct sbmac_softc *sbdma_eth;          /* back pointer to associated MAC */
 189         int              sbdma_channel; /* channel number */
 190         int              sbdma_txdir;       /* direction (1=transmit) */
 191         int              sbdma_maxdescr;        /* total # of descriptors in ring */
 192 #ifdef CONFIG_SBMAC_COALESCE
 193         int              sbdma_int_pktcnt;  /* # descriptors rx before interrupt*/
 194         int              sbdma_int_timeout; /* # usec rx interrupt */
 195 #endif
 196
 197         sbmac_port_t     sbdma_config0; /* DMA config register 0 */
 198         sbmac_port_t     sbdma_config1; /* DMA config register 1 */
 199         sbmac_port_t     sbdma_dscrbase;        /* Descriptor base address */
 200         sbmac_port_t     sbdma_dscrcnt;     /* Descriptor count register */
 201         sbmac_port_t     sbdma_curdscr; /* current descriptor address */
 202
 203         /*
 204          * This stuff is for maintenance of the ring
 205          */
 206
 207         sbdmadscr_t     *sbdma_dscrtable;       /* base of descriptor table */
 208         sbdmadscr_t     *sbdma_dscrtable_end; /* end of descriptor table */
 209
 210         struct sk_buff **sbdma_ctxtable;    /* context table, one per descr */
 211
 212         paddr_t          sbdma_dscrtable_phys; /* and also the phys addr */
 213         sbdmadscr_t     *sbdma_addptr;  /* next dscr for sw to add */
 214         sbdmadscr_t     *sbdma_remptr;  /* next dscr for sw to remove */
 215
 216 } sbmacdma_t;
 217
 218
 219 /**********************************************************************
 220  *  Ethernet softc structure
 221  ********************************************************************* */
 222
 223 struct sbmac_softc {
 224
 225         /*
 226          * Linux-specific things
 227          */
 228
 229         struct net_device *sbm_dev;             /* pointer to linux device */
 230         spinlock_t sbm_lock;            /* spin lock */
 231         struct timer_list sbm_timer;            /* for monitoring MII */
 232         struct net_device_stats sbm_stats;
 233         int sbm_devflags;                       /* current device flags */
 234
 235         int          sbm_phy_oldbmsr;
 236         int          sbm_phy_oldanlpar;
 237         int          sbm_phy_oldk1stsr;
 238         int          sbm_phy_oldlinkstat;
 239         int sbm_buffersize;
 240
 241         unsigned char sbm_phys[2];
 242
 243         /*
 244          * Controller-specific things
 245          */
 246
 247         sbmac_port_t     sbm_base;          /* MAC's base address */
 248         sbmac_state_t    sbm_state;         /* current state */
 249
 250         sbmac_port_t     sbm_macenable; /* MAC Enable Register */
 251         sbmac_port_t     sbm_maccfg;    /* MAC Configuration Register */
 252         sbmac_port_t     sbm_fifocfg;   /* FIFO configuration register */
 253         sbmac_port_t     sbm_framecfg;  /* Frame configuration register */
 254         sbmac_port_t     sbm_rxfilter;  /* receive filter register */
 255         sbmac_port_t     sbm_isr;               /* Interrupt status register */
 256         sbmac_port_t     sbm_imr;               /* Interrupt mask register */
 257         sbmac_port_t     sbm_mdio;              /* MDIO register */
 258
 259         sbmac_speed_t    sbm_speed;             /* current speed */
 260         sbmac_duplex_t   sbm_duplex;    /* current duplex */
 261         sbmac_fc_t       sbm_fc;                /* current flow control setting */
 262
 263         u_char           sbm_hwaddr[ETHER_ADDR_LEN];
 264
 265         sbmacdma_t       sbm_txdma;             /* for now, only use channel 0 */
 266         sbmacdma_t       sbm_rxdma;
 267         int              rx_hw_checksum;
 268         int              sbe_idx;
 269
 270 };
 271
 272
 273 /**********************************************************************
 274  *  Externs
 275  ********************************************************************* */
 276
 277 /**********************************************************************
 278  *  Prototypes
 279  ********************************************************************* */
 280
 281 static void sbdma_initctx(sbmacdma_t *d,
 282                           struct sbmac_softc *s,
 283                           int chan,
 284                           int txrx,
 285                           int maxdescr);
 286 static void sbdma_channel_start(sbmacdma_t *d, int rxtx);
 287 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *m);
 288 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *m);
 289 static void sbdma_emptyring(sbmacdma_t *d);
 290 static void sbdma_fillring(sbmacdma_t *d);
 291 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 292 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d);
 293 static int sbmac_initctx(struct sbmac_softc *s);
 294 static void sbmac_channel_start(struct sbmac_softc *s);
 295 static void sbmac_channel_stop(struct sbmac_softc *s);
 296 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *,sbmac_state_t);
 297 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff);
 298 /*static void sbmac_init_and_start(struct sbmac_softc *sc);*/
 299 static uint64_t sbmac_addr2reg(unsigned char *ptr);
 300 static void sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs);
 301 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev);
 302 static void sbmac_setmulti(struct sbmac_softc *sc);
 303 static int sbmac_init(struct net_device *dev);
 304 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed);
 305 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc);
 306
 307 static int sbmac_open(struct net_device *dev);
 308 static void sbmac_timer(unsigned long data);
 309 static void sbmac_tx_timeout (struct net_device *dev);
 310 static struct net_device_stats *sbmac_get_stats(struct net_device *dev);
 311 static void sbmac_set_rx_mode(struct net_device *dev);
 312 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
 313 static int sbmac_close(struct net_device *dev);
 314 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy);
 315
 316 static void sbmac_mii_sync(struct sbmac_softc *s);
 317 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt);
 318 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx);
 319 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 320                             unsigned int regval);
 321
 322
 323 /**********************************************************************
 324  *  Globals
 325  ********************************************************************* */
 326
 327 static uint64_t sbmac_orig_hwaddr[MAX_UNITS];
 328 static uint64_t chip_revision;
 329
 330
 331 /**********************************************************************
 332  *  MDIO constants
 333  ********************************************************************* */
 334
 335 #define MII_COMMAND_START       0x01
 336 #define MII_COMMAND_READ        0x02
 337 #define MII_COMMAND_WRITE       0x01
 338 #define MII_COMMAND_ACK         0x02
 339
 340 #define BMCR_RESET     0x8000
 341 #define BMCR_LOOPBACK  0x4000
 342 #define BMCR_SPEED0    0x2000
 343 #define BMCR_ANENABLE  0x1000
 344 #define BMCR_POWERDOWN 0x0800
 345 #define BMCR_ISOLATE   0x0400
 346 #define BMCR_RESTARTAN 0x0200
 347 #define BMCR_DUPLEX    0x0100
 348 #define BMCR_COLTEST   0x0080
 349 #define BMCR_SPEED1    0x0040
 350 #define BMCR_SPEED1000 (BMCR_SPEED1)
 351 #define BMCR_SPEED100  (BMCR_SPEED0)
 352 #define BMCR_SPEED10    0
 353
 354 #define BMSR_100BT4     0x8000
 355 #define BMSR_100BT_FDX  0x4000
 356 #define BMSR_100BT_HDX  0x2000
 357 #define BMSR_10BT_FDX   0x1000
 358 #define BMSR_10BT_HDX   0x0800
 359 #define BMSR_100BT2_FDX 0x0400
 360 #define BMSR_100BT2_HDX 0x0200
 361 #define BMSR_1000BT_XSR 0x0100
 362 #define BMSR_PRESUP     0x0040
 363 #define BMSR_ANCOMPLT   0x0020
 364 #define BMSR_REMFAULT   0x0010
 365 #define BMSR_AUTONEG    0x0008
 366 #define BMSR_LINKSTAT   0x0004
 367 #define BMSR_JABDETECT  0x0002
 368 #define BMSR_EXTCAPAB   0x0001
 369
 370 #define PHYIDR1         0x2000
 371 #define PHYIDR2         0x5C60
 372
 373 #define ANAR_NP         0x8000
 374 #define ANAR_RF         0x2000
 375 #define ANAR_ASYPAUSE   0x0800
 376 #define ANAR_PAUSE      0x0400
 377 #define ANAR_T4         0x0200
 378 #define ANAR_TXFD       0x0100
 379 #define ANAR_TXHD       0x0080
 380 #define ANAR_10FD       0x0040
 381 #define ANAR_10HD       0x0020
 382 #define ANAR_PSB        0x0001
 383
 384 #define ANLPAR_NP       0x8000
 385 #define ANLPAR_ACK      0x4000
 386 #define ANLPAR_RF       0x2000
 387 #define ANLPAR_ASYPAUSE 0x0800
 388 #define ANLPAR_PAUSE    0x0400
 389 #define ANLPAR_T4       0x0200
 390 #define ANLPAR_TXFD     0x0100
 391 #define ANLPAR_TXHD     0x0080
 392 #define ANLPAR_10FD     0x0040
 393 #define ANLPAR_10HD     0x0020
 394 #define ANLPAR_PSB      0x0001  /* 802.3 */
 395
 396 #define ANER_PDF        0x0010
 397 #define ANER_LPNPABLE   0x0008
 398 #define ANER_NPABLE     0x0004
 399 #define ANER_PAGERX     0x0002
 400 #define ANER_LPANABLE   0x0001
 401
 402 #define ANNPTR_NP       0x8000
 403 #define ANNPTR_MP       0x2000
 404 #define ANNPTR_ACK2     0x1000
 405 #define ANNPTR_TOGTX    0x0800
 406 #define ANNPTR_CODE     0x0008
 407
 408 #define ANNPRR_NP       0x8000
 409 #define ANNPRR_MP       0x2000
 410 #define ANNPRR_ACK3     0x1000
 411 #define ANNPRR_TOGTX    0x0800
 412 #define ANNPRR_CODE     0x0008
 413
 414 #define K1TCR_TESTMODE  0x0000
 415 #define K1TCR_MSMCE     0x1000
 416 #define K1TCR_MSCV      0x0800
 417 #define K1TCR_RPTR      0x0400
 418 #define K1TCR_1000BT_FDX 0x200
 419 #define K1TCR_1000BT_HDX 0x100
 420
 421 #define K1STSR_MSMCFLT  0x8000
 422 #define K1STSR_MSCFGRES 0x4000
 423 #define K1STSR_LRSTAT   0x2000
 424 #define K1STSR_RRSTAT   0x1000
 425 #define K1STSR_LP1KFD   0x0800
 426 #define K1STSR_LP1KHD   0x0400
 427 #define K1STSR_LPASMDIR 0x0200
 428
 429 #define K1SCR_1KX_FDX   0x8000
 430 #define K1SCR_1KX_HDX   0x4000
 431 #define K1SCR_1KT_FDX   0x2000
 432 #define K1SCR_1KT_HDX   0x1000
 433
 434 #define STRAP_PHY1      0x0800
 435 #define STRAP_NCMODE    0x0400
 436 #define STRAP_MANMSCFG  0x0200
 437 #define STRAP_ANENABLE  0x0100
 438 #define STRAP_MSVAL     0x0080
 439 #define STRAP_1KHDXADV  0x0010
 440 #define STRAP_1KFDXADV  0x0008
 441 #define STRAP_100ADV    0x0004
 442 #define STRAP_SPEEDSEL  0x0000
 443 #define STRAP_SPEED100  0x0001
 444
 445 #define PHYSUP_SPEED1000 0x10
 446 #define PHYSUP_SPEED100  0x08
 447 #define PHYSUP_SPEED10   0x00
 448 #define PHYSUP_LINKUP    0x04
 449 #define PHYSUP_FDX       0x02
 450
 451 #define MII_BMCR        0x00    /* Basic mode control register (rw) */
 452 #define MII_BMSR        0x01    /* Basic mode status register (ro) */
 453 #define MII_K1STSR      0x0A    /* 1K Status Register (ro) */
 454 #define MII_ANLPAR      0x05    /* Autonegotiation lnk partner abilities (rw) */
 455
 456
 457 #define M_MAC_MDIO_DIR_OUTPUT   0               /* for clarity */
 458
 459 #define ENABLE          1
 460 #define DISABLE         0
 461
 462 /**********************************************************************
 463  *  SBMAC_MII_SYNC(s)
 464  *
 465  *  Synchronize with the MII - send a pattern of bits to the MII
 466  *  that will guarantee that it is ready to accept a command.
 467  *
 468  *  Input parameters:
 469  *         s - sbmac structure
 470  *
 471  *  Return value:
 472  *         nothing
 473  ********************************************************************* */
 474
 475 static void sbmac_mii_sync(struct sbmac_softc *s)
 476 {
 477         int cnt;
 478         uint64_t bits;
 479
 480         bits = M_MAC_MDIO_DIR_OUTPUT | M_MAC_MDIO_OUT;
 481
 482         SBMAC_WRITECSR(s->sbm_mdio,bits);
 483
 484         for (cnt = 0; cnt < 32; cnt++) {
 485                 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC);
 486                 SBMAC_WRITECSR(s->sbm_mdio,bits);
 487         }
 488 }
 489
 490 /**********************************************************************
 491  *  SBMAC_MII_SENDDATA(s,data,bitcnt)
 492  *
 493  *  Send some bits to the MII.  The bits to be sent are right-
 494  *  justified in the 'data' parameter.
 495  *
 496  *  Input parameters:
 497  *         s - sbmac structure
 498  *         data - data to send
 499  *         bitcnt - number of bits to send
 500  ********************************************************************* */
 501
 502 static void sbmac_mii_senddata(struct sbmac_softc *s,unsigned int data, int bitcnt)
 503 {
 504         int i;
 505         uint64_t bits;
 506         unsigned int curmask;
 507
 508         bits = M_MAC_MDIO_DIR_OUTPUT;
 509         SBMAC_WRITECSR(s->sbm_mdio,bits);
 510
 511         curmask = 1 << (bitcnt - 1);
 512
 513         for (i = 0; i < bitcnt; i++) {
 514                 if (data & curmask) bits |= M_MAC_MDIO_OUT;
 515                 else bits &= ~M_MAC_MDIO_OUT;
 516                 SBMAC_WRITECSR(s->sbm_mdio,bits);
 517                 SBMAC_WRITECSR(s->sbm_mdio,bits | M_MAC_MDC);
 518                 SBMAC_WRITECSR(s->sbm_mdio,bits);
 519                 curmask >>= 1;
 520         }
 521 }
 522
 523
 524
 525 /**********************************************************************
 526  *  SBMAC_MII_READ(s,phyaddr,regidx)
 527  *
 528  *  Read a PHY register.
 529  *
 530  *  Input parameters:
 531  *         s - sbmac structure
 532  *         phyaddr - PHY's address
 533  *         regidx = index of register to read
 534  *
 535  *  Return value:
 536  *         value read, or 0 if an error occured.
 537  ********************************************************************* */
 538
 539 static unsigned int sbmac_mii_read(struct sbmac_softc *s,int phyaddr,int regidx)
 540 {
 541         int idx;
 542         int error;
 543         int regval;
 544
 545         /*
 546          * Synchronize ourselves so that the PHY knows the next
 547          * thing coming down is a command
 548          */
 549
 550         sbmac_mii_sync(s);
 551
 552         /*
 553          * Send the data to the PHY.  The sequence is
 554          * a "start" command (2 bits)
 555          * a "read" command (2 bits)
 556          * the PHY addr (5 bits)
 557          * the register index (5 bits)
 558          */
 559
 560         sbmac_mii_senddata(s,MII_COMMAND_START, 2);
 561         sbmac_mii_senddata(s,MII_COMMAND_READ, 2);
 562         sbmac_mii_senddata(s,phyaddr, 5);
 563         sbmac_mii_senddata(s,regidx, 5);
 564
 565         /*
 566          * Switch the port around without a clock transition.
 567          */
 568         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
 569
 570         /*
 571          * Send out a clock pulse to signal we want the status
 572          */
 573
 574         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC);
 575         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
 576
 577         /*
 578          * If an error occured, the PHY will signal '1' back
 579          */
 580         error = SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN;
 581
 582         /*
 583          * Issue an 'idle' clock pulse, but keep the direction
 584          * the same.
 585          */
 586         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC);
 587         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
 588
 589         regval = 0;
 590
 591         for (idx = 0; idx < 16; idx++) {
 592                 regval <<= 1;
 593
 594                 if (error == 0) {
 595                         if (SBMAC_READCSR(s->sbm_mdio) & M_MAC_MDIO_IN) regval |= 1;
 596                 }
 597
 598                 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT | M_MAC_MDC);
 599                 SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_INPUT);
 600         }
 601
 602         /* Switch back to output */
 603         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT);
 604
 605         if (error == 0) return regval;
 606         return 0;
 607 }
 608
 609
 610 /**********************************************************************
 611  *  SBMAC_MII_WRITE(s,phyaddr,regidx,regval)
 612  *
 613  *  Write a value to a PHY register.
 614  *
 615  *  Input parameters:
 616  *         s - sbmac structure
 617  *         phyaddr - PHY to use
 618  *         regidx - register within the PHY
 619  *         regval - data to write to register
 620  *
 621  *  Return value:
 622  *         nothing
 623  ********************************************************************* */
 624
 625 static void sbmac_mii_write(struct sbmac_softc *s,int phyaddr,int regidx,
 626                             unsigned int regval)
 627 {
 628
 629         sbmac_mii_sync(s);
 630
 631         sbmac_mii_senddata(s,MII_COMMAND_START,2);
 632         sbmac_mii_senddata(s,MII_COMMAND_WRITE,2);
 633         sbmac_mii_senddata(s,phyaddr, 5);
 634         sbmac_mii_senddata(s,regidx, 5);
 635         sbmac_mii_senddata(s,MII_COMMAND_ACK,2);
 636         sbmac_mii_senddata(s,regval,16);
 637
 638         SBMAC_WRITECSR(s->sbm_mdio,M_MAC_MDIO_DIR_OUTPUT);
 639 }
 640
 641
 642
 643 /**********************************************************************
 644  *  SBDMA_INITCTX(d,s,chan,txrx,maxdescr)
 645  *
 646  *  Initialize a DMA channel context.  Since there are potentially
 647  *  eight DMA channels per MAC, it's nice to do this in a standard
 648  *  way.
 649  *
 650  *  Input parameters:
 651  *         d - sbmacdma_t structure (DMA channel context)
 652  *         s - sbmac_softc structure (pointer to a MAC)
 653  *         chan - channel number (0..1 right now)
 654  *         txrx - Identifies DMA_TX or DMA_RX for channel direction
 655  *      maxdescr - number of descriptors
 656  *
 657  *  Return value:
 658  *         nothing
 659  ********************************************************************* */
 660
 661 static void sbdma_initctx(sbmacdma_t *d,
 662                           struct sbmac_softc *s,
 663                           int chan,
 664                           int txrx,
 665                           int maxdescr)
 666 {
 667         /*
 668          * Save away interesting stuff in the structure
 669          */
 670
 671         d->sbdma_eth       = s;
 672         d->sbdma_channel   = chan;
 673         d->sbdma_txdir     = txrx;
 674
 675         /* RMON clearing */
 676         s->sbe_idx =(s->sbm_base - A_MAC_BASE_0)/MAC_SPACING;
 677
 678         SBMAC_WRITECSR(PKSEG1(
 679         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BYTES)), 0);
 680         SBMAC_WRITECSR(PKSEG1(
 681         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_COLLISIONS)), 0);
 682         SBMAC_WRITECSR(PKSEG1(
 683         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_LATE_COL)), 0);
 684         SBMAC_WRITECSR(PKSEG1(
 685         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_EX_COL)), 0);
 686         SBMAC_WRITECSR(PKSEG1(
 687         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_FCS_ERROR)), 0);
 688         SBMAC_WRITECSR(PKSEG1(
 689         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_ABORT)), 0);
 690         SBMAC_WRITECSR(PKSEG1(
 691         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_BAD)), 0);
 692         SBMAC_WRITECSR(PKSEG1(
 693         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_GOOD)), 0);
 694         SBMAC_WRITECSR(PKSEG1(
 695         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_RUNT)), 0);
 696         SBMAC_WRITECSR(PKSEG1(
 697         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_TX_OVERSIZE)), 0);
 698         SBMAC_WRITECSR(PKSEG1(
 699         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BYTES)), 0);
 700         SBMAC_WRITECSR(PKSEG1(
 701         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_MCAST)), 0);
 702         SBMAC_WRITECSR(PKSEG1(
 703         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BCAST)), 0);
 704         SBMAC_WRITECSR(PKSEG1(
 705         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_BAD)), 0);
 706         SBMAC_WRITECSR(PKSEG1(
 707         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_GOOD)), 0);
 708         SBMAC_WRITECSR(PKSEG1(
 709         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_RUNT)), 0);
 710         SBMAC_WRITECSR(PKSEG1(
 711         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_OVERSIZE)), 0);
 712         SBMAC_WRITECSR(PKSEG1(
 713         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_FCS_ERROR)), 0);
 714         SBMAC_WRITECSR(PKSEG1(
 715         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_LENGTH_ERROR)), 0);
 716         SBMAC_WRITECSR(PKSEG1(
 717         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_CODE_ERROR)), 0);
 718         SBMAC_WRITECSR(PKSEG1(
 719         A_MAC_REGISTER(s->sbe_idx, R_MAC_RMON_RX_ALIGN_ERROR)), 0);
 720
 721         /*
 722          * initialize register pointers
 723          */
 724
 725         d->sbdma_config0 =
 726                 PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG0));
 727         d->sbdma_config1 =
 728                 PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CONFIG1));
 729         d->sbdma_dscrbase =
 730                 PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_BASE));
 731         d->sbdma_dscrcnt =
 732                 PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_DSCR_CNT));
 733         d->sbdma_curdscr =
 734                 PKSEG1(s->sbm_base + R_MAC_DMA_REGISTER(txrx,chan,R_MAC_DMA_CUR_DSCRADDR));
 735
 736         /*
 737          * Allocate memory for the ring
 738          */
 739
 740         d->sbdma_maxdescr = maxdescr;
 741
 742         d->sbdma_dscrtable = (sbdmadscr_t *)
 743                 KMALLOC(d->sbdma_maxdescr*sizeof(sbdmadscr_t));
 744
 745         memset(d->sbdma_dscrtable,0,d->sbdma_maxdescr*sizeof(sbdmadscr_t));
 746
 747         d->sbdma_dscrtable_end = d->sbdma_dscrtable + d->sbdma_maxdescr;
 748
 749         d->sbdma_dscrtable_phys = KVTOPHYS(d->sbdma_dscrtable);
 750
 751         /*
 752          * And context table
 753          */
 754
 755         d->sbdma_ctxtable = (struct sk_buff **)
 756                 KMALLOC(d->sbdma_maxdescr*sizeof(struct sk_buff *));
 757
 758         memset(d->sbdma_ctxtable,0,d->sbdma_maxdescr*sizeof(struct sk_buff *));
 759
 760 #ifdef CONFIG_SBMAC_COALESCE
 761         /*
 762          * Setup Rx DMA coalescing defaults
 763          */
 764
 765         if ( txrx == DMA_RX ) {
 766                 if ( int_pktcnt ) {
 767                         d->sbdma_int_pktcnt = int_pktcnt;
 768                         }
 769                 else {
 770                         d->sbdma_int_pktcnt = 1;
 771                         }
 772
 773                 if ( int_timeout ) {
 774                         d->sbdma_int_timeout = int_timeout;
 775                         }
 776                 else {
 777                         d->sbdma_int_timeout = 0;
 778                     }
 779                 }
 780         else {
 781                 d->sbdma_int_pktcnt = 0;
 782                 d->sbdma_int_timeout = 0;
 783                 }
 784 #endif
 785
 786 }
 787
 788 /**********************************************************************
 789  *  SBDMA_CHANNEL_START(d)
 790  *
 791  *  Initialize the hardware registers for a DMA channel.
 792  *
 793  *  Input parameters:
 794  *         d - DMA channel to init (context must be previously init'd
 795  *         rxtx - DMA_RX or DMA_TX depending on what type of channel
 796  *
 797  *  Return value:
 798  *         nothing
 799  ********************************************************************* */
 800
 801 static void sbdma_channel_start(sbmacdma_t *d, int rxtx )
 802 {
 803     /*
 804      * Turn on the DMA channel
 805      */
 806
 807 #ifdef CONFIG_SBMAC_COALESCE
 808     if (rxtx == DMA_RX) {
 809         SBMAC_WRITECSR(d->sbdma_config1,
 810                        V_DMA_INT_TIMEOUT(d->sbdma_int_timeout) |
 811                        0);
 812         SBMAC_WRITECSR(d->sbdma_config0,
 813                        M_DMA_EOP_INT_EN |
 814                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 815                        V_DMA_INT_PKTCNT(d->sbdma_int_pktcnt) |
 816                        0);
 817         }
 818     else {
 819         SBMAC_WRITECSR(d->sbdma_config1,0);
 820         SBMAC_WRITECSR(d->sbdma_config0,
 821                        V_DMA_RINGSZ(d->sbdma_maxdescr) |
 822                        0);
 823         }
 824 #else
 825     SBMAC_WRITECSR(d->sbdma_config1,0);
 826     SBMAC_WRITECSR(d->sbdma_config0,
 827                    V_DMA_RINGSZ(d->sbdma_maxdescr) |
 828                    0);
 829 #endif
 830
 831
 832     SBMAC_WRITECSR(d->sbdma_dscrbase,d->sbdma_dscrtable_phys);
 833
 834     /*
 835      * Initialize ring pointers
 836      */
 837
 838     d->sbdma_addptr = d->sbdma_dscrtable;
 839     d->sbdma_remptr = d->sbdma_dscrtable;
 840 }
 841
 842 /**********************************************************************
 843  *  SBDMA_CHANNEL_STOP(d)
 844  *
 845  *  Initialize the hardware registers for a DMA channel.
 846  *
 847  *  Input parameters:
 848  *         d - DMA channel to init (context must be previously init'd
 849  *
 850  *  Return value:
 851  *         nothing
 852  ********************************************************************* */
 853
 854 static void sbdma_channel_stop(sbmacdma_t *d)
 855 {
 856         /*
 857          * Turn off the DMA channel
 858          */
 859
 860         SBMAC_WRITECSR(d->sbdma_config1,0);
 861
 862         SBMAC_WRITECSR(d->sbdma_dscrbase,0);
 863
 864         SBMAC_WRITECSR(d->sbdma_config0,0);
 865
 866         /*
 867          * Zero ring pointers
 868          */
 869
 870         d->sbdma_addptr = 0;
 871         d->sbdma_remptr = 0;
 872 }
 873
 874 static void sbdma_align_skb(struct sk_buff *skb,int power2,int offset)
 875 {
 876         unsigned long addr;
 877         unsigned long newaddr;
 878
 879         addr = (unsigned long) skb->data;
 880
 881         newaddr = (addr + power2 - 1) & ~(power2 - 1);
 882
 883         skb_reserve(skb,newaddr-addr+offset);
 884 }
 885
 886
 887 /**********************************************************************
 888  *  SBDMA_ADD_RCVBUFFER(d,sb)
 889  *
 890  *  Add a buffer to the specified DMA channel.   For receive channels,
 891  *  this queues a buffer for inbound packets.
 892  *
 893  *  Input parameters:
 894  *         d - DMA channel descriptor
 895  *         sb - sk_buff to add, or NULL if we should allocate one
 896  *
 897  *  Return value:
 898  *         0 if buffer could not be added (ring is full)
 899  *         1 if buffer added successfully
 900  ********************************************************************* */
 901
 902
 903 static int sbdma_add_rcvbuffer(sbmacdma_t *d,struct sk_buff *sb)
 904 {
 905         sbdmadscr_t *dsc;
 906         sbdmadscr_t *nextdsc;
 907         struct sk_buff *sb_new = NULL;
 908         int pktsize = ENET_PACKET_SIZE;
 909
 910         /* get pointer to our current place in the ring */
 911
 912         dsc = d->sbdma_addptr;
 913         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
 914
 915         /*
 916          * figure out if the ring is full - if the next descriptor
 917          * is the same as the one that we're going to remove from
 918          * the ring, the ring is full
 919          */
 920
 921         if (nextdsc == d->sbdma_remptr) {
 922                 return -ENOSPC;
 923         }
 924
 925         /*
 926          * Allocate a sk_buff if we don't already have one.
 927          * If we do have an sk_buff, reset it so that it's empty.
 928          *
 929          * Note: sk_buffs don't seem to be guaranteed to have any sort
 930          * of alignment when they are allocated.  Therefore, allocate enough
 931          * extra space to make sure that:
 932          *
 933          *    1. the data does not start in the middle of a cache line.
 934          *    2. The data does not end in the middle of a cache line
 935          *    3. The buffer can be aligned such that the IP addresses are
 936          *       naturally aligned.
 937          *
 938          *  Remember, the SB1250's MAC writes whole cache lines at a time,
 939          *  without reading the old contents first.  So, if the sk_buff's
 940          *  data portion starts in the middle of a cache line, the SB1250
 941          *  DMA will trash the beginning (and ending) portions.
 942          */
 943
 944         if (sb == NULL) {
 945                 sb_new = dev_alloc_skb(ENET_PACKET_SIZE + CACHELINESIZE*2 + ETHER_ALIGN);
 946                 if (sb_new == NULL) {
 947                         printk(KERN_INFO "%s: sk_buff allocation failed\n",
 948                                d->sbdma_eth->sbm_dev->name);
 949                         return -ENOBUFS;
 950                 }
 951
 952                 sbdma_align_skb(sb_new,CACHELINESIZE,ETHER_ALIGN);
 953
 954                 /* mark skbuff owned by our device */
 955                 sb_new->dev = d->sbdma_eth->sbm_dev;
 956         }
 957         else {
 958                 sb_new = sb;
 959                 /*
 960                  * nothing special to reinit buffer, it's already aligned
 961                  * and sb->tail already points to a good place.
 962                  */
 963         }
 964
 965         /*
 966          * fill in the descriptor
 967          */
 968
 969 #ifdef CONFIG_SBMAC_COALESCE
 970         /*
 971          * Do not interrupt per DMA transfer.
 972          */
 973         dsc->dscr_a = KVTOPHYS(sb_new->tail) |
 974                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 975                 0;
 976 #else
 977         dsc->dscr_a = KVTOPHYS(sb_new->tail) |
 978                 V_DMA_DSCRA_A_SIZE(NUMCACHEBLKS(pktsize+ETHER_ALIGN)) |
 979                 M_DMA_DSCRA_INTERRUPT;
 980 #endif
 981
 982         /* receiving: no options */
 983         dsc->dscr_b = 0;
 984
 985         /*
 986          * fill in the context
 987          */
 988
 989         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb_new;
 990
 991         /*
 992          * point at next packet
 993          */
 994
 995         d->sbdma_addptr = nextdsc;
 996
 997         /*
 998          * Give the buffer to the DMA engine.
 999          */
1000
1001         SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1002
1003         return 0;                                       /* we did it */
1004 }
1005
1006 /**********************************************************************
1007  *  SBDMA_ADD_TXBUFFER(d,sb)
1008  *
1009  *  Add a transmit buffer to the specified DMA channel, causing a
1010  *  transmit to start.
1011  *
1012  *  Input parameters:
1013  *         d - DMA channel descriptor
1014  *         sb - sk_buff to add
1015  *
1016  *  Return value:
1017  *         0 transmit queued successfully
1018  *         otherwise error code
1019  ********************************************************************* */
1020
1021
1022 static int sbdma_add_txbuffer(sbmacdma_t *d,struct sk_buff *sb)
1023 {
1024         sbdmadscr_t *dsc;
1025         sbdmadscr_t *nextdsc;
1026         uint64_t phys;
1027         uint64_t ncb;
1028         int length;
1029
1030         /* get pointer to our current place in the ring */
1031
1032         dsc = d->sbdma_addptr;
1033         nextdsc = SBDMA_NEXTBUF(d,sbdma_addptr);
1034
1035         /*
1036          * figure out if the ring is full - if the next descriptor
1037          * is the same as the one that we're going to remove from
1038          * the ring, the ring is full
1039          */
1040
1041         if (nextdsc == d->sbdma_remptr) {
1042                 return -ENOSPC;
1043         }
1044
1045         /*
1046          * Under Linux, it's not necessary to copy/coalesce buffers
1047          * like it is on NetBSD.  We think they're all contiguous,
1048          * but that may not be true for GBE.
1049          */
1050
1051         length = sb->len;
1052
1053         /*
1054          * fill in the descriptor.  Note that the number of cache
1055          * blocks in the descriptor is the number of blocks
1056          * *spanned*, so we need to add in the offset (if any)
1057          * while doing the calculation.
1058          */
1059
1060         phys = KVTOPHYS(sb->data);
1061         ncb = NUMCACHEBLKS(length+(phys & (CACHELINESIZE-1)));
1062
1063         dsc->dscr_a = phys |
1064                 V_DMA_DSCRA_A_SIZE(ncb) |
1065                 M_DMA_DSCRA_INTERRUPT |
1066                 M_DMA_ETHTX_SOP;
1067
1068         /* transmitting: set outbound options and length */
1069
1070         dsc->dscr_b = V_DMA_DSCRB_OPTIONS(K_DMA_ETHTX_APPENDCRC_APPENDPAD) |
1071                 V_DMA_DSCRB_PKT_SIZE(length);
1072
1073         /*
1074          * fill in the context
1075          */
1076
1077         d->sbdma_ctxtable[dsc-d->sbdma_dscrtable] = sb;
1078
1079         /*
1080          * point at next packet
1081          */
1082
1083         d->sbdma_addptr = nextdsc;
1084
1085         /*
1086          * Give the buffer to the DMA engine.
1087          */
1088
1089         SBMAC_WRITECSR(d->sbdma_dscrcnt,1);
1090
1091         return 0;                                       /* we did it */
1092 }
1093
1094
1095
1096
1097 /**********************************************************************
1098  *  SBDMA_EMPTYRING(d)
1099  *
1100  *  Free all allocated sk_buffs on the specified DMA channel;
1101  *
1102  *  Input parameters:
1103  *         d  - DMA channel
1104  *
1105  *  Return value:
1106  *         nothing
1107  ********************************************************************* */
1108
1109 static void sbdma_emptyring(sbmacdma_t *d)
1110 {
1111         int idx;
1112         struct sk_buff *sb;
1113
1114         for (idx = 0; idx < d->sbdma_maxdescr; idx++) {
1115                 sb = d->sbdma_ctxtable[idx];
1116                 if (sb) {
1117                         dev_kfree_skb(sb);
1118                         d->sbdma_ctxtable[idx] = NULL;
1119                 }
1120         }
1121 }
1122
1123
1124 /**********************************************************************
1125  *  SBDMA_FILLRING(d)
1126  *
1127  *  Fill the specified DMA channel (must be receive channel)
1128  *  with sk_buffs
1129  *
1130  *  Input parameters:
1131  *         d - DMA channel
1132  *
1133  *  Return value:
1134  *         nothing
1135  ********************************************************************* */
1136
1137 static void sbdma_fillring(sbmacdma_t *d)
1138 {
1139         int idx;
1140
1141         for (idx = 0; idx < SBMAC_MAX_RXDESCR-1; idx++) {
1142                 if (sbdma_add_rcvbuffer(d,NULL) != 0) break;
1143         }
1144 }
1145
1146
1147 /**********************************************************************
1148  *  SBDMA_RX_PROCESS(sc,d)
1149  *
1150  *  Process "completed" receive buffers on the specified DMA channel.
1151  *  Note that this isn't really ideal for priority channels, since
1152  *  it processes all of the packets on a given channel before
1153  *  returning.
1154  *
1155  *  Input parameters:
1156  *         sc - softc structure
1157  *         d - DMA channel context
1158  *
1159  *  Return value:
1160  *         nothing
1161  ********************************************************************* */
1162
1163 static void sbdma_rx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1164 {
1165         int curidx;
1166         int hwidx;
1167         sbdmadscr_t *dsc;
1168         struct sk_buff *sb;
1169         int len;
1170
1171         for (;;) {
1172                 /*
1173                  * figure out where we are (as an index) and where
1174                  * the hardware is (also as an index)
1175                  *
1176                  * This could be done faster if (for example) the
1177                  * descriptor table was page-aligned and contiguous in
1178                  * both virtual and physical memory -- you could then
1179                  * just compare the low-order bits of the virtual address
1180                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1181                  */
1182
1183                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1184                 hwidx = (int) (((SBMAC_READCSR(d->sbdma_curdscr) & M_DMA_CURDSCR_ADDR) -
1185                                 d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1186
1187                 /*
1188                  * If they're the same, that means we've processed all
1189                  * of the descriptors up to (but not including) the one that
1190                  * the hardware is working on right now.
1191                  */
1192
1193                 if (curidx == hwidx) break;
1194
1195                 /*
1196                  * Otherwise, get the packet's sk_buff ptr back
1197                  */
1198
1199                 dsc = &(d->sbdma_dscrtable[curidx]);
1200                 sb = d->sbdma_ctxtable[curidx];
1201                 d->sbdma_ctxtable[curidx] = NULL;
1202
1203                 len = (int)G_DMA_DSCRB_PKT_SIZE(dsc->dscr_b) - 4;
1204
1205                 /*
1206                  * Check packet status.  If good, process it.
1207                  * If not, silently drop it and put it back on the
1208                  * receive ring.
1209                  */
1210
1211                 if (!(dsc->dscr_a & M_DMA_ETHRX_BAD)) {
1212
1213                         /*
1214                          * Set length into the packet
1215                          */
1216                         skb_put(sb,len);
1217
1218                         /*
1219                          * Add a new buffer to replace the old one.  If we fail
1220                          * to allocate a buffer, we're going to drop this
1221                          * packet and put it right back on the receive ring.
1222                          */
1223
1224                         if (sbdma_add_rcvbuffer(d,NULL) == -ENOBUFS) {
1225                             sbdma_add_rcvbuffer(d,sb);  /* re-add old buffer */
1226                             }
1227                         else {
1228                             /*
1229                              * Buffer has been replaced on the receive ring.
1230                              * Pass the buffer to the kernel
1231                              */
1232                             sc->sbm_stats.rx_bytes += len;
1233                             sc->sbm_stats.rx_packets++;
1234                             sb->protocol = eth_type_trans(sb,d->sbdma_eth->sbm_dev);
1235                             if (sc->rx_hw_checksum == ENABLE) {
1236                             /* if the ip checksum is good indicate in skb.
1237                                 else set CHECKSUM_NONE as device failed to
1238                                         checksum the packet */
1239
1240                                if (((dsc->dscr_b) |M_DMA_ETHRX_BADTCPCS) ||
1241                                   ((dsc->dscr_a)| M_DMA_ETHRX_BADIP4CS)){
1242                                   sb->ip_summed = CHECKSUM_NONE;
1243                                } else {
1244                                  printk(KERN_DEBUG "hw checksum fail .\n");
1245                                  sb->ip_summed = CHECKSUM_UNNECESSARY;
1246                                }
1247                             } /*rx_hw_checksum */
1248
1249                             netif_rx(sb);
1250                             }
1251                 }
1252                 else {
1253                         /*
1254                          * Packet was mangled somehow.  Just drop it and
1255                          * put it back on the receive ring.
1256                          */
1257                         sbdma_add_rcvbuffer(d,sb);
1258                 }
1259
1260
1261                 /*
1262                  * .. and advance to the next buffer.
1263                  */
1264
1265                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1266
1267         }
1268 }
1269
1270
1271
1272 /**********************************************************************
1273  *  SBDMA_TX_PROCESS(sc,d)
1274  *
1275  *  Process "completed" transmit buffers on the specified DMA channel.
1276  *  This is normally called within the interrupt service routine.
1277  *  Note that this isn't really ideal for priority channels, since
1278  *  it processes all of the packets on a given channel before
1279  *  returning.
1280  *
1281  *  Input parameters:
1282  *      sc - softc structure
1283  *         d - DMA channel context
1284  *
1285  *  Return value:
1286  *         nothing
1287  ********************************************************************* */
1288
1289 static void sbdma_tx_process(struct sbmac_softc *sc,sbmacdma_t *d)
1290 {
1291         int curidx;
1292         int hwidx;
1293         sbdmadscr_t *dsc;
1294         struct sk_buff *sb;
1295         unsigned long flags;
1296
1297         spin_lock_irqsave(&(sc->sbm_lock), flags);
1298
1299         for (;;) {
1300                 /*
1301                  * figure out where we are (as an index) and where
1302                  * the hardware is (also as an index)
1303                  *
1304                  * This could be done faster if (for example) the
1305                  * descriptor table was page-aligned and contiguous in
1306                  * both virtual and physical memory -- you could then
1307                  * just compare the low-order bits of the virtual address
1308                  * (sbdma_remptr) and the physical address (sbdma_curdscr CSR)
1309                  */
1310
1311                 curidx = d->sbdma_remptr - d->sbdma_dscrtable;
1312                 {
1313                         /* XXX This is gross, ugly, and only here because justin hacked it
1314                            in to fix a problem without really understanding it.
1315
1316                            It seems that, for whatever reason, this routine is invoked immediately upon the enabling of interrupts.
1317                            So then the Read below returns zero, making hwidx a negative number, and anti-hilarity
1318                            ensues.
1319
1320                            I'm guessing there's a proper fix involving clearing out interrupt state from old packets
1321                            before enabling interrupts, but I'm not sure.
1322
1323                            Anyways, this hack seems to work, and is Good Enough for 11 PM.  :)
1324
1325                            -Justin
1326                         */
1327
1328                         uint64_t tmp = SBMAC_READCSR(d->sbdma_curdscr);
1329                         if (!tmp) {
1330                                 break;
1331                         }
1332                         hwidx = (int) (((tmp & M_DMA_CURDSCR_ADDR) -
1333                                         d->sbdma_dscrtable_phys) / sizeof(sbdmadscr_t));
1334                 }
1335                 /*
1336                  * If they're the same, that means we've processed all
1337                  * of the descriptors up to (but not including) the one that
1338                  * the hardware is working on right now.
1339                  */
1340
1341                 if (curidx == hwidx) break;
1342
1343                 /*
1344                  * Otherwise, get the packet's sk_buff ptr back
1345                  */
1346
1347                 dsc = &(d->sbdma_dscrtable[curidx]);
1348                 sb = d->sbdma_ctxtable[curidx];
1349                 d->sbdma_ctxtable[curidx] = NULL;
1350
1351                 /*
1352                  * Stats
1353                  */
1354
1355                 sc->sbm_stats.tx_bytes += sb->len;
1356                 sc->sbm_stats.tx_packets++;
1357
1358                 /*
1359                  * for transmits, we just free buffers.
1360                  */
1361
1362                 dev_kfree_skb_irq(sb);
1363
1364                 /*
1365                  * .. and advance to the next buffer.
1366                  */
1367
1368                 d->sbdma_remptr = SBDMA_NEXTBUF(d,sbdma_remptr);
1369
1370         }
1371
1372         /*
1373          * Decide if we should wake up the protocol or not.
1374          * Other drivers seem to do this when we reach a low
1375          * watermark on the transmit queue.
1376          */
1377
1378         netif_wake_queue(d->sbdma_eth->sbm_dev);
1379
1380         spin_unlock_irqrestore(&(sc->sbm_lock), flags);
1381
1382 }
1383
1384
1385
1386 /**********************************************************************
1387  *  SBMAC_INITCTX(s)
1388  *
1389  *  Initialize an Ethernet context structure - this is called
1390  *  once per MAC on the 1250.  Memory is allocated here, so don't
1391  *  call it again from inside the ioctl routines that bring the
1392  *  interface up/down
1393  *
1394  *  Input parameters:
1395  *         s - sbmac context structure
1396  *
1397  *  Return value:
1398  *         0
1399  ********************************************************************* */
1400
1401 static int sbmac_initctx(struct sbmac_softc *s)
1402 {
1403
1404         /*
1405          * figure out the addresses of some ports
1406          */
1407
1408         s->sbm_macenable = PKSEG1(s->sbm_base + R_MAC_ENABLE);
1409         s->sbm_maccfg    = PKSEG1(s->sbm_base + R_MAC_CFG);
1410         s->sbm_fifocfg   = PKSEG1(s->sbm_base + R_MAC_THRSH_CFG);
1411         s->sbm_framecfg  = PKSEG1(s->sbm_base + R_MAC_FRAMECFG);
1412         s->sbm_rxfilter  = PKSEG1(s->sbm_base + R_MAC_ADFILTER_CFG);
1413         s->sbm_isr       = PKSEG1(s->sbm_base + R_MAC_STATUS);
1414         s->sbm_imr       = PKSEG1(s->sbm_base + R_MAC_INT_MASK);
1415         s->sbm_mdio      = PKSEG1(s->sbm_base + R_MAC_MDIO);
1416
1417         s->sbm_phys[0]   = 1;
1418         s->sbm_phys[1]   = 0;
1419
1420         s->sbm_phy_oldbmsr = 0;
1421         s->sbm_phy_oldanlpar = 0;
1422         s->sbm_phy_oldk1stsr = 0;
1423         s->sbm_phy_oldlinkstat = 0;
1424
1425         /*
1426          * Initialize the DMA channels.  Right now, only one per MAC is used
1427          * Note: Only do this _once_, as it allocates memory from the kernel!
1428          */
1429
1430         sbdma_initctx(&(s->sbm_txdma),s,0,DMA_TX,SBMAC_MAX_TXDESCR);
1431         sbdma_initctx(&(s->sbm_rxdma),s,0,DMA_RX,SBMAC_MAX_RXDESCR);
1432
1433         /*
1434          * initial state is OFF
1435          */
1436
1437         s->sbm_state = sbmac_state_off;
1438
1439         /*
1440          * Initial speed is (XXX TEMP) 10MBit/s HDX no FC
1441          */
1442
1443         s->sbm_speed = sbmac_speed_10;
1444         s->sbm_duplex = sbmac_duplex_half;
1445         s->sbm_fc = sbmac_fc_disabled;
1446
1447         return 0;
1448 }
1449
1450
1451 static void sbdma_uninitctx(struct sbmacdma_s *d)
1452 {
1453         if (d->sbdma_dscrtable) {
1454                 KFREE(d->sbdma_dscrtable);
1455                 d->sbdma_dscrtable = NULL;
1456         }
1457
1458         if (d->sbdma_ctxtable) {
1459                 KFREE(d->sbdma_ctxtable);
1460                 d->sbdma_ctxtable = NULL;
1461         }
1462 }
1463
1464
1465 static void sbmac_uninitctx(struct sbmac_softc *sc)
1466 {
1467         sbdma_uninitctx(&(sc->sbm_txdma));
1468         sbdma_uninitctx(&(sc->sbm_rxdma));
1469 }
1470
1471
1472 /**********************************************************************
1473  *  SBMAC_CHANNEL_START(s)
1474  *
1475  *  Start packet processing on this MAC.
1476  *
1477  *  Input parameters:
1478  *         s - sbmac structure
1479  *
1480  *  Return value:
1481  *         nothing
1482  ********************************************************************* */
1483
1484 static void sbmac_channel_start(struct sbmac_softc *s)
1485 {
1486         uint64_t reg;
1487         sbmac_port_t port;
1488         uint64_t cfg,fifo,framecfg;
1489         int idx;
1490
1491         /*
1492          * Don't do this if running
1493          */
1494
1495         if (s->sbm_state == sbmac_state_on) return;
1496
1497         /*
1498          * Bring the controller out of reset, but leave it off.
1499          */
1500
1501         SBMAC_WRITECSR(s->sbm_macenable,0);
1502
1503         /*
1504          * Ignore all received packets
1505          */
1506
1507         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1508
1509         /*
1510          * Calculate values for various control registers.
1511          */
1512
1513         cfg = M_MAC_RETRY_EN |
1514                 M_MAC_TX_HOLD_SOP_EN |
1515                 V_MAC_TX_PAUSE_CNT_16K |
1516                 M_MAC_AP_STAT_EN |
1517                 M_MAC_FAST_SYNC |
1518                 M_MAC_SS_EN |
1519                 0;
1520
1521         /*
1522          * Be sure that RD_THRSH+WR_THRSH <= 32
1523          * Use a larger RD_THRSH for gigabit
1524          */
1525
1526         fifo = V_MAC_TX_WR_THRSH(4) |   /* Must be '4' or '8' */
1527                 ((s->sbm_speed == sbmac_speed_1000)
1528                  ? V_MAC_TX_RD_THRSH(28) : V_MAC_TX_RD_THRSH(4)) |
1529                 V_MAC_TX_RL_THRSH(4) |
1530                 V_MAC_RX_PL_THRSH(4) |
1531                 V_MAC_RX_RD_THRSH(4) |  /* Must be '4' */
1532                 V_MAC_RX_PL_THRSH(4) |
1533                 V_MAC_RX_RL_THRSH(8) |
1534                 0;
1535
1536         framecfg = V_MAC_MIN_FRAMESZ_DEFAULT |
1537                 V_MAC_MAX_FRAMESZ_DEFAULT |
1538                 V_MAC_BACKOFF_SEL(1);
1539
1540
1541         /*
1542          * Clear out the hash address map
1543          */
1544
1545         port = PKSEG1(s->sbm_base + R_MAC_HASH_BASE);
1546         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
1547                 SBMAC_WRITECSR(port,0);
1548                 port += sizeof(uint64_t);
1549         }
1550
1551         /*
1552          * Clear out the exact-match table
1553          */
1554
1555         port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE);
1556         for (idx = 0; idx < MAC_ADDR_COUNT; idx++) {
1557                 SBMAC_WRITECSR(port,0);
1558                 port += sizeof(uint64_t);
1559         }
1560
1561         /*
1562          * Clear out the DMA Channel mapping table registers
1563          */
1564
1565         port = PKSEG1(s->sbm_base + R_MAC_CHUP0_BASE);
1566         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1567                 SBMAC_WRITECSR(port,0);
1568                 port += sizeof(uint64_t);
1569         }
1570
1571
1572         port = PKSEG1(s->sbm_base + R_MAC_CHLO0_BASE);
1573         for (idx = 0; idx < MAC_CHMAP_COUNT; idx++) {
1574                 SBMAC_WRITECSR(port,0);
1575                 port += sizeof(uint64_t);
1576         }
1577
1578         /*
1579          * Program the hardware address.  It goes into the hardware-address
1580          * register as well as the first filter register.
1581          */
1582
1583         reg = sbmac_addr2reg(s->sbm_hwaddr);
1584
1585         port = PKSEG1(s->sbm_base + R_MAC_ADDR_BASE);
1586         SBMAC_WRITECSR(port,reg);
1587         port = PKSEG1(s->sbm_base + R_MAC_ETHERNET_ADDR);
1588
1589 #ifdef CONFIG_SB1_PASS_1_WORKAROUNDS
1590         /*
1591          * Pass1 SB1250s do not receive packets addressed to the
1592          * destination address in the R_MAC_ETHERNET_ADDR register.
1593          * Set the value to zero.
1594          */
1595         SBMAC_WRITECSR(port,0);
1596 #else
1597         SBMAC_WRITECSR(port,reg);
1598 #endif
1599
1600         /*
1601          * Set the receive filter for no packets, and write values
1602          * to the various config registers
1603          */
1604
1605         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1606         SBMAC_WRITECSR(s->sbm_imr,0);
1607         SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1608         SBMAC_WRITECSR(s->sbm_fifocfg,fifo);
1609         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1610
1611         /*
1612          * Initialize DMA channels (rings should be ok now)
1613          */
1614
1615         sbdma_channel_start(&(s->sbm_rxdma), DMA_RX);
1616         sbdma_channel_start(&(s->sbm_txdma), DMA_TX);
1617
1618         /*
1619          * Configure the speed, duplex, and flow control
1620          */
1621
1622         sbmac_set_speed(s,s->sbm_speed);
1623         sbmac_set_duplex(s,s->sbm_duplex,s->sbm_fc);
1624
1625         /*
1626          * Fill the receive ring
1627          */
1628
1629         sbdma_fillring(&(s->sbm_rxdma));
1630
1631         /*
1632          * Turn on the rest of the bits in the enable register
1633          */
1634
1635         SBMAC_WRITECSR(s->sbm_macenable,
1636                        M_MAC_RXDMA_EN0 |
1637                        M_MAC_TXDMA_EN0 |
1638                        M_MAC_RX_ENABLE |
1639                        M_MAC_TX_ENABLE);
1640
1641
1642
1643
1644 #ifdef CONFIG_SBMAC_COALESCE
1645         /*
1646          * Accept any TX interrupt and EOP count/timer RX interrupts on ch 0
1647          */
1648         SBMAC_WRITECSR(s->sbm_imr,
1649                        (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1650                        ((M_MAC_INT_EOP_COUNT | M_MAC_INT_EOP_TIMER) << S_MAC_RX_CH0));
1651 #else
1652         /*
1653          * Accept any kind of interrupt on TX and RX DMA channel 0
1654          */
1655         SBMAC_WRITECSR(s->sbm_imr,
1656                        (M_MAC_INT_CHANNEL << S_MAC_TX_CH0) |
1657                        (M_MAC_INT_CHANNEL << S_MAC_RX_CH0));
1658 #endif
1659
1660         /*
1661          * Enable receiving unicasts and broadcasts
1662          */
1663
1664         SBMAC_WRITECSR(s->sbm_rxfilter,M_MAC_UCAST_EN | M_MAC_BCAST_EN);
1665
1666         /*
1667          * we're running now.
1668          */
1669
1670         s->sbm_state = sbmac_state_on;
1671
1672         /*
1673          * Program multicast addresses
1674          */
1675
1676         sbmac_setmulti(s);
1677
1678         /*
1679          * If channel was in promiscuous mode before, turn that on
1680          */
1681
1682         if (s->sbm_devflags & IFF_PROMISC) {
1683                 sbmac_promiscuous_mode(s,1);
1684         }
1685
1686 }
1687
1688
1689 /**********************************************************************
1690  *  SBMAC_CHANNEL_STOP(s)
1691  *
1692  *  Stop packet processing on this MAC.
1693  *
1694  *  Input parameters:
1695  *         s - sbmac structure
1696  *
1697  *  Return value:
1698  *         nothing
1699  ********************************************************************* */
1700
1701 static void sbmac_channel_stop(struct sbmac_softc *s)
1702 {
1703         /* don't do this if already stopped */
1704
1705         if (s->sbm_state == sbmac_state_off) return;
1706
1707         /* don't accept any packets, disable all interrupts */
1708
1709         SBMAC_WRITECSR(s->sbm_rxfilter,0);
1710         SBMAC_WRITECSR(s->sbm_imr,0);
1711
1712         /* Turn off ticker */
1713
1714         /* XXX */
1715
1716         /* turn off receiver and transmitter */
1717
1718         SBMAC_WRITECSR(s->sbm_macenable,0);
1719
1720         /* We're stopped now. */
1721
1722         s->sbm_state = sbmac_state_off;
1723
1724         /*
1725          * Stop DMA channels (rings should be ok now)
1726          */
1727
1728         sbdma_channel_stop(&(s->sbm_rxdma));
1729         sbdma_channel_stop(&(s->sbm_txdma));
1730
1731         /* Empty the receive and transmit rings */
1732
1733         sbdma_emptyring(&(s->sbm_rxdma));
1734         sbdma_emptyring(&(s->sbm_txdma));
1735
1736 }
1737
1738 /**********************************************************************
1739  *  SBMAC_SET_CHANNEL_STATE(state)
1740  *
1741  *  Set the channel's state ON or OFF
1742  *
1743  *  Input parameters:
1744  *         state - new state
1745  *
1746  *  Return value:
1747  *         old state
1748  ********************************************************************* */
1749 static sbmac_state_t sbmac_set_channel_state(struct sbmac_softc *sc,
1750                                              sbmac_state_t state)
1751 {
1752         sbmac_state_t oldstate = sc->sbm_state;
1753
1754         /*
1755          * If same as previous state, return
1756          */
1757
1758         if (state == oldstate) {
1759                 return oldstate;
1760         }
1761
1762         /*
1763          * If new state is ON, turn channel on
1764          */
1765
1766         if (state == sbmac_state_on) {
1767                 sbmac_channel_start(sc);
1768         }
1769         else {
1770                 sbmac_channel_stop(sc);
1771         }
1772
1773         /*
1774          * Return previous state
1775          */
1776
1777         return oldstate;
1778 }
1779
1780
1781 /**********************************************************************
1782  *  SBMAC_PROMISCUOUS_MODE(sc,onoff)
1783  *
1784  *  Turn on or off promiscuous mode
1785  *
1786  *  Input parameters:
1787  *         sc - softc
1788  *      onoff - 1 to turn on, 0 to turn off
1789  *
1790  *  Return value:
1791  *         nothing
1792  ********************************************************************* */
1793
1794 static void sbmac_promiscuous_mode(struct sbmac_softc *sc,int onoff)
1795 {
1796         uint64_t reg;
1797
1798         if (sc->sbm_state != sbmac_state_on) return;
1799
1800         if (onoff) {
1801                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1802                 reg |= M_MAC_ALLPKT_EN;
1803                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1804         }
1805         else {
1806                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
1807                 reg &= ~M_MAC_ALLPKT_EN;
1808                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1809         }
1810 }
1811
1812 /**********************************************************************
1813  *  SBMAC_SETIPHDR_OFFSET(sc,onoff)
1814  *
1815  *  Set the iphdr offset as 15 assuming ethernet encapsulation
1816  *
1817  *  Input parameters:
1818  *         sc - softc
1819  *
1820  *  Return value:
1821  *         nothing
1822  ********************************************************************* */
1823
1824 static void sbmac_set_iphdr_offset(struct sbmac_softc *sc)
1825 {
1826         uint64_t reg;
1827
1828         reg = SBMAC_READCSR(sc->sbm_rxfilter);
1829         reg &= ~M_MAC_IPHDR_OFFSET;
1830         /* Hard code the off set to 15 for now */
1831         reg |= 15 << S_MAC_IPHDR_OFFSET;
1832         SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
1833
1834         /* read system identification to determine revision */
1835         if (sb1250_pass >= K_SYS_REVISION_PASS2) {
1836                 printk(KERN_INFO "pass2 - enabling Rx rcv tcp checksum\n");
1837                 sc->rx_hw_checksum = ENABLE;
1838         } else {
1839                 sc->rx_hw_checksum = DISABLE;
1840         }
1841 }
1842
1843
1844 #if 0
1845 /**********************************************************************
1846  *  SBMAC_INIT_AND_START(sc)
1847  *
1848  *  Stop the channel and restart it.  This is generally used
1849  *  when we have to do something to the channel that requires
1850  *  a swift kick.
1851  *
1852  *  Input parameters:
1853  *         sc - softc
1854  ********************************************************************* */
1855
1856 static void sbmac_init_and_start(struct sbmac_softc *sc)
1857 {
1858         unsigned long flags;
1859
1860         spin_lock_irqsave(&(sc->sbm_lock),flags);
1861
1862         sbmac_set_channel_state(sc,sbmac_state_on);
1863
1864         spin_unlock_irqrestore(&(sc->sbm_lock),flags);
1865 }
1866 #endif
1867
1868
1869 /**********************************************************************
1870  *  SBMAC_ADDR2REG(ptr)
1871  *
1872  *  Convert six bytes into the 64-bit register value that
1873  *  we typically write into the SBMAC's address/mcast registers
1874  *
1875  *  Input parameters:
1876  *         ptr - pointer to 6 bytes
1877  *
1878  *  Return value:
1879  *         register value
1880  ********************************************************************* */
1881
1882 static uint64_t sbmac_addr2reg(unsigned char *ptr)
1883 {
1884         uint64_t reg = 0;
1885
1886         ptr += 6;
1887
1888         reg |= (uint64_t) *(--ptr);
1889         reg <<= 8;
1890         reg |= (uint64_t) *(--ptr);
1891         reg <<= 8;
1892         reg |= (uint64_t) *(--ptr);
1893         reg <<= 8;
1894         reg |= (uint64_t) *(--ptr);
1895         reg <<= 8;
1896         reg |= (uint64_t) *(--ptr);
1897         reg <<= 8;
1898         reg |= (uint64_t) *(--ptr);
1899
1900         return reg;
1901 }
1902
1903
1904 /**********************************************************************
1905  *  SBMAC_SET_SPEED(s,speed)
1906  *
1907  *  Configure LAN speed for the specified MAC.
1908  *  Warning: must be called when MAC is off!
1909  *
1910  *  Input parameters:
1911  *         s - sbmac structure
1912  *         speed - speed to set MAC to (see sbmac_speed_t enum)
1913  *
1914  *  Return value:
1915  *         1 if successful
1916  *      0 indicates invalid parameters
1917  ********************************************************************* */
1918
1919 static int sbmac_set_speed(struct sbmac_softc *s,sbmac_speed_t speed)
1920 {
1921         uint64_t cfg;
1922         uint64_t framecfg;
1923
1924         /*
1925          * Save new current values
1926          */
1927
1928         s->sbm_speed = speed;
1929
1930         if (s->sbm_state == sbmac_state_on) return 0;   /* save for next restart */
1931
1932         /*
1933          * Read current register values
1934          */
1935
1936         cfg = SBMAC_READCSR(s->sbm_maccfg);
1937         framecfg = SBMAC_READCSR(s->sbm_framecfg);
1938
1939         /*
1940          * Mask out the stuff we want to change
1941          */
1942
1943         cfg &= ~(M_MAC_BURST_EN | M_MAC_SPEED_SEL);
1944         framecfg &= ~(M_MAC_IFG_RX | M_MAC_IFG_TX | M_MAC_IFG_THRSH |
1945                       M_MAC_SLOT_SIZE);
1946
1947         /*
1948          * Now add in the new bits
1949          */
1950
1951         switch (speed) {
1952         case sbmac_speed_10:
1953                 framecfg |= V_MAC_IFG_RX_10 |
1954                         V_MAC_IFG_TX_10 |
1955                         K_MAC_IFG_THRSH_10 |
1956                         V_MAC_SLOT_SIZE_10;
1957                 cfg |= V_MAC_SPEED_SEL_10MBPS;
1958                 break;
1959
1960         case sbmac_speed_100:
1961                 framecfg |= V_MAC_IFG_RX_100 |
1962                         V_MAC_IFG_TX_100 |
1963                         V_MAC_IFG_THRSH_100 |
1964                         V_MAC_SLOT_SIZE_100;
1965                 cfg |= V_MAC_SPEED_SEL_100MBPS ;
1966                 break;
1967
1968         case sbmac_speed_1000:
1969                 framecfg |= V_MAC_IFG_RX_1000 |
1970                         V_MAC_IFG_TX_1000 |
1971                         V_MAC_IFG_THRSH_1000 |
1972                         V_MAC_SLOT_SIZE_1000;
1973                 cfg |= V_MAC_SPEED_SEL_1000MBPS | M_MAC_BURST_EN;
1974                 break;
1975
1976         case sbmac_speed_auto:          /* XXX not implemented */
1977                 /* fall through */
1978         default:
1979                 return 0;
1980         }
1981
1982         /*
1983          * Send the bits back to the hardware
1984          */
1985
1986         SBMAC_WRITECSR(s->sbm_framecfg,framecfg);
1987         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
1988
1989         return 1;
1990
1991 }
1992
1993 /**********************************************************************
1994  *  SBMAC_SET_DUPLEX(s,duplex,fc)
1995  *
1996  *  Set Ethernet duplex and flow control options for this MAC
1997  *  Warning: must be called when MAC is off!
1998  *
1999  *  Input parameters:
2000  *         s - sbmac structure
2001  *         duplex - duplex setting (see sbmac_duplex_t)
2002  *         fc - flow control setting (see sbmac_fc_t)
2003  *
2004  *  Return value:
2005  *         1 if ok
2006  *         0 if an invalid parameter combination was specified
2007  ********************************************************************* */
2008
2009 static int sbmac_set_duplex(struct sbmac_softc *s,sbmac_duplex_t duplex,sbmac_fc_t fc)
2010 {
2011         uint64_t cfg;
2012
2013         /*
2014          * Save new current values
2015          */
2016
2017         s->sbm_duplex = duplex;
2018         s->sbm_fc = fc;
2019
2020         if (s->sbm_state == sbmac_state_on) return 0;   /* save for next restart */
2021
2022         /*
2023          * Read current register values
2024          */
2025
2026         cfg = SBMAC_READCSR(s->sbm_maccfg);
2027
2028         /*
2029          * Mask off the stuff we're about to change
2030          */
2031
2032         cfg &= ~(M_MAC_FC_SEL | M_MAC_FC_CMD | M_MAC_HDX_EN);
2033
2034
2035         switch (duplex) {
2036         case sbmac_duplex_half:
2037                 switch (fc) {
2038                 case sbmac_fc_disabled:
2039                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_DISABLED;
2040                         break;
2041
2042                 case sbmac_fc_collision:
2043                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENABLED;
2044                         break;
2045
2046                 case sbmac_fc_carrier:
2047                         cfg |= M_MAC_HDX_EN | V_MAC_FC_CMD_ENAB_FALSECARR;
2048                         break;
2049
2050                 case sbmac_fc_auto:             /* XXX not implemented */
2051                         /* fall through */
2052                 case sbmac_fc_frame:            /* not valid in half duplex */
2053                 default:                        /* invalid selection */
2054                         return 0;
2055                 }
2056                 break;
2057
2058         case sbmac_duplex_full:
2059                 switch (fc) {
2060                 case sbmac_fc_disabled:
2061                         cfg |= V_MAC_FC_CMD_DISABLED;
2062                         break;
2063
2064                 case sbmac_fc_frame:
2065                         cfg |= V_MAC_FC_CMD_ENABLED;
2066                         break;
2067
2068                 case sbmac_fc_collision:        /* not valid in full duplex */
2069                 case sbmac_fc_carrier:          /* not valid in full duplex */
2070                 case sbmac_fc_auto:             /* XXX not implemented */
2071                         /* fall through */
2072                 default:
2073                         return 0;
2074                 }
2075                 break;
2076         case sbmac_duplex_auto:
2077                 /* XXX not implemented */
2078                 break;
2079         }
2080
2081         /*
2082          * Send the bits back to the hardware
2083          */
2084
2085         SBMAC_WRITECSR(s->sbm_maccfg,cfg);
2086
2087         return 1;
2088 }
2089
2090
2091
2092
2093 /**********************************************************************
2094  *  SBMAC_INTR()
2095  *
2096  *  Interrupt handler for MAC interrupts
2097  *
2098  *  Input parameters:
2099  *         MAC structure
2100  *
2101  *  Return value:
2102  *         nothing
2103  ********************************************************************* */
2104 static void sbmac_intr(int irq,void *dev_instance,struct pt_regs *rgs)
2105 {
2106         struct net_device *dev = (struct net_device *) dev_instance;
2107         struct sbmac_softc *sc = (struct sbmac_softc *) (dev->priv);
2108         uint64_t isr;
2109
2110         for (;;) {
2111
2112                 /*
2113                  * Read the ISR (this clears the bits in the real
2114                  * register, except for counter addr)
2115                  */
2116
2117                 isr = SBMAC_READCSR(sc->sbm_isr) & ~M_MAC_COUNTER_ADDR;
2118
2119                 if (isr == 0) break;
2120
2121                 /*
2122                  * Transmits on channel 0
2123                  */
2124
2125                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_TX_CH0)) {
2126                         sbdma_tx_process(sc,&(sc->sbm_txdma));
2127                 }
2128
2129                 /*
2130                  * Receives on channel 0
2131                  */
2132
2133                 /*
2134                  * It's important to test all the bits (or at least the
2135                  * EOP_SEEN bit) when deciding to do the RX process
2136                  * particularly when coalescing, to make sure we
2137                  * take care of the following:
2138                  *
2139                  * If you have some packets waiting (have been received
2140                  * but no interrupt) and get a TX interrupt before
2141                  * the RX timer or counter expires, reading the ISR
2142                  * above will clear the timer and counter, and you
2143                  * won't get another interrupt until a packet shows
2144                  * up to start the timer again.  Testing
2145                  * EOP_SEEN here takes care of this case.
2146                  * (EOP_SEEN is part of M_MAC_INT_CHANNEL << S_MAC_RX_CH0)
2147                  */
2148
2149
2150                 if (isr & (M_MAC_INT_CHANNEL << S_MAC_RX_CH0)) {
2151                         sbdma_rx_process(sc,&(sc->sbm_rxdma));
2152                 }
2153         }
2154
2155 }
2156
2157
2158 /**********************************************************************
2159  *  SBMAC_START_TX(skb,dev)
2160  *
2161  *  Start output on the specified interface.  Basically, we
2162  *  queue as many buffers as we can until the ring fills up, or
2163  *  we run off the end of the queue, whichever comes first.
2164  *
2165  *  Input parameters:
2166  *
2167  *
2168  *  Return value:
2169  *         nothing
2170  ********************************************************************* */
2171 static int sbmac_start_tx(struct sk_buff *skb, struct net_device *dev)
2172 {
2173         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2174
2175         /* lock eth irq */
2176         spin_lock_irq (&sc->sbm_lock);
2177
2178         /*
2179          * Put the buffer on the transmit ring.  If we
2180          * don't have room, stop the queue.
2181          */
2182
2183         if (sbdma_add_txbuffer(&(sc->sbm_txdma),skb)) {
2184                 /* XXX save skb that we could not send */
2185                 netif_stop_queue(dev);
2186                 spin_unlock_irq(&sc->sbm_lock);
2187
2188                 return 1;
2189         }
2190
2191         dev->trans_start = jiffies;
2192
2193         spin_unlock_irq (&sc->sbm_lock);
2194
2195         return 0;
2196 }
2197
2198 /**********************************************************************
2199  *  SBMAC_SETMULTI(sc)
2200  *
2201  *  Reprogram the multicast table into the hardware, given
2202  *  the list of multicasts associated with the interface
2203  *  structure.
2204  *
2205  *  Input parameters:
2206  *         sc - softc
2207  *
2208  *  Return value:
2209  *         nothing
2210  ********************************************************************* */
2211
2212 static void sbmac_setmulti(struct sbmac_softc *sc)
2213 {
2214         uint64_t reg;
2215         sbmac_port_t port;
2216         int idx;
2217         struct dev_mc_list *mclist;
2218         struct net_device *dev = sc->sbm_dev;
2219
2220         /*
2221          * Clear out entire multicast table.  We do this by nuking
2222          * the entire hash table and all the direct matches except
2223          * the first one, which is used for our station address
2224          */
2225
2226         for (idx = 1; idx < MAC_ADDR_COUNT; idx++) {
2227                 port = PKSEG1(sc->sbm_base + R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)));
2228                 SBMAC_WRITECSR(port,0);
2229         }
2230
2231         for (idx = 0; idx < MAC_HASH_COUNT; idx++) {
2232                 port = PKSEG1(sc->sbm_base + R_MAC_HASH_BASE+(idx*sizeof(uint64_t)));
2233                 SBMAC_WRITECSR(port,0);
2234         }
2235
2236         /*
2237          * Clear the filter to say we don't want any multicasts.
2238          */
2239
2240         reg = SBMAC_READCSR(sc->sbm_rxfilter);
2241         reg &= ~(M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2242         SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2243
2244         if (dev->flags & IFF_ALLMULTI) {
2245                 /*
2246                  * Enable ALL multicasts.  Do this by inverting the
2247                  * multicast enable bit.
2248                  */
2249                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2250                 reg |= (M_MAC_MCAST_INV | M_MAC_MCAST_EN);
2251                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2252                 return;
2253         }
2254
2255
2256         /*
2257          * Progam new multicast entries.  For now, only use the
2258          * perfect filter.  In the future we'll need to use the
2259          * hash filter if the perfect filter overflows
2260          */
2261
2262         /* XXX only using perfect filter for now, need to use hash
2263          * XXX if the table overflows */
2264
2265         idx = 1;                /* skip station address */
2266         mclist = dev->mc_list;
2267         while (mclist && (idx < MAC_ADDR_COUNT)) {
2268                 reg = sbmac_addr2reg(mclist->dmi_addr);
2269                 port = PKSEG1(sc->sbm_base +
2270                               R_MAC_ADDR_BASE+(idx*sizeof(uint64_t)));
2271                 SBMAC_WRITECSR(port,reg);
2272                 idx++;
2273                 mclist = mclist->next;
2274         }
2275
2276         /*
2277          * Enable the "accept multicast bits" if we programmed at least one
2278          * multicast.
2279          */
2280
2281         if (idx > 1) {
2282                 reg = SBMAC_READCSR(sc->sbm_rxfilter);
2283                 reg |= M_MAC_MCAST_EN;
2284                 SBMAC_WRITECSR(sc->sbm_rxfilter,reg);
2285         }
2286 }
2287
2288
2289
2290 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2291 /**********************************************************************
2292  *  SBMAC_PARSE_XDIGIT(str)
2293  *
2294  *  Parse a hex digit, returning its value
2295  *
2296  *  Input parameters:
2297  *         str - character
2298  *
2299  *  Return value:
2300  *         hex value, or -1 if invalid
2301  ********************************************************************* */
2302
2303 static int sbmac_parse_xdigit(char str)
2304 {
2305         int digit;
2306
2307         if ((str >= '0') && (str <= '9')) digit = str - '0';
2308         else if ((str >= 'a') && (str <= 'f')) digit = str - 'a' + 10;
2309         else if ((str >= 'A') && (str <= 'F')) digit = str - 'A' + 10;
2310         else return -1;
2311
2312         return digit;
2313 }
2314
2315 /**********************************************************************
2316  *  SBMAC_PARSE_HWADDR(str,hwaddr)
2317  *
2318  *  Convert a string in the form xx:xx:xx:xx:xx:xx into a 6-byte
2319  *  Ethernet address.
2320  *
2321  *  Input parameters:
2322  *         str - string
2323  *         hwaddr - pointer to hardware address
2324  *
2325  *  Return value:
2326  *         0 if ok, else -1
2327  ********************************************************************* */
2328
2329 static int sbmac_parse_hwaddr(char *str,u_char *hwaddr)
2330 {
2331         int digit1,digit2;
2332         int idx = 6;
2333
2334         while (*str && (idx > 0)) {
2335                 digit1 = sbmac_parse_xdigit(*str);
2336                 if (digit1 < 0) return -1;
2337                 str++;
2338                 if (!*str) return -1;
2339
2340                 if ((*str == ':') || (*str == '-')) {
2341                         digit2 = digit1;
2342                         digit1 = 0;
2343                 }
2344                 else {
2345                         digit2 = sbmac_parse_xdigit(*str);
2346                         if (digit2 < 0) return -1;
2347                         str++;
2348                 }
2349
2350                 *hwaddr++ = (digit1 << 4) | digit2;
2351                 idx--;
2352
2353                 if (*str == '-') str++;
2354                 if (*str == ':') str++;
2355         }
2356         return 0;
2357 }
2358 #endif
2359
2360 static int sb1250_change_mtu(struct net_device *_dev, int new_mtu)
2361 {
2362         if (new_mtu >  ENET_PACKET_SIZE)
2363                 return -EINVAL;
2364         _dev->mtu = new_mtu;
2365         printk(KERN_INFO "changing the mtu to %d\n", new_mtu);
2366         return 0;
2367 }
2368
2369 /**********************************************************************
2370  *  SBMAC_INIT(dev)
2371  *
2372  *  Attach routine - init hardware and hook ourselves into linux
2373  *
2374  *  Input parameters:
2375  *         dev - net_device structure
2376  *
2377  *  Return value:
2378  *         status
2379  ********************************************************************* */
2380
2381 static int sbmac_init(struct net_device *dev)
2382 {
2383         struct sbmac_softc *sc;
2384         u_char *eaddr;
2385         uint64_t ea_reg;
2386         int idx;
2387
2388         sc = (struct sbmac_softc *)dev->priv;
2389
2390         /* Determine controller base address */
2391
2392         sc->sbm_base = (sbmac_port_t) dev->base_addr;
2393         sc->sbm_dev = dev;
2394
2395         eaddr = sc->sbm_hwaddr;
2396
2397         /*
2398          * Read the ethernet address.  The firwmare left this programmed
2399          * for us in the ethernet address register for each mac.
2400          */
2401
2402         ea_reg = SBMAC_READCSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR));
2403         SBMAC_WRITECSR(PKSEG1(sc->sbm_base + R_MAC_ETHERNET_ADDR), 0);
2404         for (idx = 0; idx < 6; idx++) {
2405                 eaddr[idx] = (uint8_t) (ea_reg & 0xFF);
2406                 ea_reg >>= 8;
2407         }
2408
2409
2410         for (idx = 0; idx < 6; idx++) {
2411                 dev->dev_addr[idx] = eaddr[idx];
2412         }
2413
2414
2415         /*
2416          * Init packet size
2417          */
2418
2419         sc->sbm_buffersize = ENET_PACKET_SIZE + CACHELINESIZE*2 + ETHER_ALIGN;
2420
2421         /*
2422          * Initialize context (get pointers to registers and stuff), then
2423          * allocate the memory for the descriptor tables.
2424          */
2425
2426         sbmac_initctx(sc);
2427
2428
2429         /*
2430          * Display Ethernet address (this is called during the config process
2431          * so we need to finish off the config message that was being displayed)
2432          */
2433         printk(KERN_INFO
2434                "%s: SB1250 Ethernet at 0x%08lX, address: %02X-%02X-%02X-%02X-%02X-%02X\n",
2435                dev->name,
2436                (unsigned long) sc->sbm_base,
2437                eaddr[0],eaddr[1],eaddr[2],eaddr[3],eaddr[4],eaddr[5]);
2438
2439         /*
2440          * Set up Linux device callins
2441          */
2442
2443         spin_lock_init(&(sc->sbm_lock));
2444
2445         ether_setup(dev);
2446         dev->open               = sbmac_open;
2447         dev->hard_start_xmit    = sbmac_start_tx;
2448         dev->stop               = sbmac_close;
2449         dev->get_stats          = sbmac_get_stats;
2450         dev->set_multicast_list = sbmac_set_rx_mode;
2451         dev->do_ioctl           = sbmac_mii_ioctl;
2452         dev->tx_timeout         = sbmac_tx_timeout;
2453         dev->watchdog_timeo     = TX_TIMEOUT;
2454
2455         dev->change_mtu         = sb1250_change_mtu;
2456
2457         if (sb1250_pass >= K_SYS_REVISION_PASS3) {
2458                 /* In pass3 we do dumb checksum in TX */
2459                 dev->features |= NETIF_F_IP_CSUM;
2460         }
2461
2462         /* This is needed for PASS2 for Rx H/W checksum feature */
2463         sbmac_set_iphdr_offset( sc);
2464
2465         return 0;
2466
2467 }
2468
2469
2470 static int sbmac_open(struct net_device *dev)
2471 {
2472         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2473
2474         MOD_INC_USE_COUNT;
2475
2476         if (debug > 1) {
2477                 printk(KERN_DEBUG "%s: sbmac_open() irq %d.\n", dev->name, dev->irq);
2478         }
2479
2480         /*
2481          * map/route interrupt
2482          */
2483
2484         if (request_irq(dev->irq, &sbmac_intr, SA_SHIRQ, dev->name, dev)) {
2485                 MOD_DEC_USE_COUNT;
2486                 return -EBUSY;
2487         }
2488
2489         /*
2490          * Configure default speed
2491          */
2492
2493         sbmac_mii_poll(sc,1);
2494
2495         /*
2496          * Turn on the channel
2497          */
2498
2499         sbmac_set_channel_state(sc,sbmac_state_on);
2500
2501         /*
2502          * XXX Station address is in dev->dev_addr
2503          */
2504
2505         if (dev->if_port == 0)
2506                 dev->if_port = 0;
2507
2508         netif_start_queue(dev);
2509
2510         sbmac_set_rx_mode(dev);
2511
2512         /* Set the timer to check for link beat. */
2513         init_timer(&sc->sbm_timer);
2514         sc->sbm_timer.expires = jiffies + 2;
2515         sc->sbm_timer.data = (unsigned long)dev;
2516         sc->sbm_timer.function = &sbmac_timer;
2517         add_timer(&sc->sbm_timer);
2518
2519         return 0;
2520 }
2521
2522
2523
2524 static int sbmac_mii_poll(struct sbmac_softc *s,int noisy)
2525 {
2526     int bmsr,bmcr,k1stsr,anlpar;
2527     int chg;
2528     char buffer[100];
2529     char *p = buffer;
2530
2531     /* Read the mode status and mode control registers. */
2532     bmsr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMSR);
2533     bmcr = sbmac_mii_read(s,s->sbm_phys[0],MII_BMCR);
2534
2535     /* get the link partner status */
2536     anlpar = sbmac_mii_read(s,s->sbm_phys[0],MII_ANLPAR);
2537
2538     /* if supported, read the 1000baseT register */
2539     if (bmsr & BMSR_1000BT_XSR) {
2540         k1stsr = sbmac_mii_read(s,s->sbm_phys[0],MII_K1STSR);
2541         }
2542     else {
2543         k1stsr = 0;
2544         }
2545
2546     chg = 0;
2547
2548     if ((bmsr & BMSR_LINKSTAT) == 0) {
2549         /*
2550          * If link status is down, clear out old info so that when
2551          * it comes back up it will force us to reconfigure speed
2552          */
2553         s->sbm_phy_oldbmsr = 0;
2554         s->sbm_phy_oldanlpar = 0;
2555         s->sbm_phy_oldk1stsr = 0;
2556         return 0;
2557         }
2558
2559     if ((s->sbm_phy_oldbmsr != bmsr) ||
2560         (s->sbm_phy_oldanlpar != anlpar) ||
2561         (s->sbm_phy_oldk1stsr != k1stsr)) {
2562         if (debug > 1) {
2563             printk(KERN_DEBUG "%s: bmsr:%x/%x anlpar:%x/%x  k1stsr:%x/%x\n",
2564                s->sbm_dev->name,
2565                s->sbm_phy_oldbmsr,bmsr,
2566                s->sbm_phy_oldanlpar,anlpar,
2567                s->sbm_phy_oldk1stsr,k1stsr);
2568             }
2569         s->sbm_phy_oldbmsr = bmsr;
2570         s->sbm_phy_oldanlpar = anlpar;
2571         s->sbm_phy_oldk1stsr = k1stsr;
2572         chg = 1;
2573         }
2574
2575     if (chg == 0) return 0;
2576
2577     p += sprintf(p,"Link speed: ");
2578
2579     if (k1stsr & K1STSR_LP1KFD) {
2580         s->sbm_speed = sbmac_speed_1000;
2581         s->sbm_duplex = sbmac_duplex_full;
2582         s->sbm_fc = sbmac_fc_frame;
2583         p += sprintf(p,"1000BaseT FDX");
2584         }
2585     else if (k1stsr & K1STSR_LP1KHD) {
2586         s->sbm_speed = sbmac_speed_1000;
2587         s->sbm_duplex = sbmac_duplex_half;
2588         s->sbm_fc = sbmac_fc_disabled;
2589         p += sprintf(p,"1000BaseT HDX");
2590         }
2591     else if (anlpar & ANLPAR_TXFD) {
2592         s->sbm_speed = sbmac_speed_100;
2593         s->sbm_duplex = sbmac_duplex_full;
2594         s->sbm_fc = (anlpar & ANLPAR_PAUSE) ? sbmac_fc_frame : sbmac_fc_disabled;
2595         p += sprintf(p,"100BaseT FDX");
2596         }
2597     else if (anlpar & ANLPAR_TXHD) {
2598         s->sbm_speed = sbmac_speed_100;
2599         s->sbm_duplex = sbmac_duplex_half;
2600         s->sbm_fc = sbmac_fc_disabled;
2601         p += sprintf(p,"100BaseT HDX");
2602         }
2603     else if (anlpar & ANLPAR_10FD) {
2604         s->sbm_speed = sbmac_speed_10;
2605         s->sbm_duplex = sbmac_duplex_full;
2606         s->sbm_fc = sbmac_fc_frame;
2607         p += sprintf(p,"10BaseT FDX");
2608         }
2609     else if (anlpar & ANLPAR_10HD) {
2610         s->sbm_speed = sbmac_speed_10;
2611         s->sbm_duplex = sbmac_duplex_half;
2612         s->sbm_fc = sbmac_fc_collision;
2613         p += sprintf(p,"10BaseT HDX");
2614         }
2615     else {
2616         p += sprintf(p,"Unknown");
2617         }
2618
2619 #ifdef CONFIG_NET_SB1250_MAC_QUIET
2620     noisy = 0;
2621 #endif
2622     if (noisy) {
2623             printk(KERN_INFO "%s: %s\n",s->sbm_dev->name,buffer);
2624             }
2625
2626     return 1;
2627 }
2628
2629
2630
2631
2632 static void sbmac_timer(unsigned long data)
2633 {
2634         struct net_device *dev = (struct net_device *)data;
2635         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2636         int next_tick = HZ;
2637         int mii_status;
2638
2639         spin_lock_irq (&sc->sbm_lock);
2640
2641         /* make IFF_RUNNING follow the MII status bit "Link established" */
2642         mii_status = sbmac_mii_read(sc, sc->sbm_phys[0], MII_BMSR);
2643
2644         if ( (mii_status & BMSR_LINKSTAT) != (sc->sbm_phy_oldlinkstat) ) {
2645                 sc->sbm_phy_oldlinkstat = mii_status & BMSR_LINKSTAT;
2646                 if (mii_status & BMSR_LINKSTAT) {
2647                         netif_carrier_on(dev);
2648                 }
2649                 else {
2650                         netif_carrier_off(dev);
2651                 }
2652         }
2653
2654         /*
2655          * Poll the PHY to see what speed we should be running at
2656          */
2657
2658         if (sbmac_mii_poll(sc,1)) {
2659             if (sc->sbm_state != sbmac_state_off) {
2660                 /*
2661                  * something changed, restart the channel
2662                  */
2663                 if (debug > 1) {
2664                     printk("%s: restarting channel because speed changed\n",
2665                            sc->sbm_dev->name);
2666                     }
2667                 sbmac_channel_stop(sc);
2668                 sbmac_channel_start(sc);
2669                 }
2670             }
2671
2672         spin_unlock_irq (&sc->sbm_lock);
2673
2674         sc->sbm_timer.expires = jiffies + next_tick;
2675         add_timer(&sc->sbm_timer);
2676 }
2677
2678
2679 static void sbmac_tx_timeout (struct net_device *dev)
2680 {
2681         struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv;
2682
2683         spin_lock_irq (&sc->sbm_lock);
2684
2685
2686         dev->trans_start = jiffies;
2687         sc->sbm_stats.tx_errors++;
2688
2689         spin_unlock_irq (&sc->sbm_lock);
2690
2691         printk (KERN_WARNING "%s: Transmit timed out\n",dev->name);
2692 }
2693
2694
2695
2696
2697 static struct net_device_stats *sbmac_get_stats(struct net_device *dev)
2698 {
2699         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2700         unsigned long flags;
2701
2702         spin_lock_irqsave(&sc->sbm_lock, flags);
2703
2704         /* XXX update other stats here */
2705
2706         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2707
2708         return &sc->sbm_stats;
2709 }
2710
2711
2712
2713 static void sbmac_set_rx_mode(struct net_device *dev)
2714 {
2715         unsigned long flags;
2716         int msg_flag = 0;
2717         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2718
2719         spin_lock_irqsave(&sc->sbm_lock, flags);
2720         if ((dev->flags ^ sc->sbm_devflags) & IFF_PROMISC) {
2721                 /*
2722                  * Promiscuous changed.
2723                  */
2724
2725                 if (dev->flags & IFF_PROMISC) {
2726                         /* Unconditionally log net taps. */
2727                         msg_flag = 1;
2728                         sbmac_promiscuous_mode(sc,1);
2729                 }
2730                 else {
2731                         msg_flag = 2;
2732                         sbmac_promiscuous_mode(sc,0);
2733                 }
2734         }
2735         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2736
2737         if (msg_flag) {
2738                 printk(KERN_NOTICE "%s: Promiscuous mode %sabled.\n", dev->name,(msg_flag==1)?"en":"dis");
2739         }
2740
2741         /*
2742          * Program the multicasts.  Do this every time.
2743          */
2744
2745         sbmac_setmulti(sc);
2746
2747 }
2748
2749 static int sbmac_mii_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
2750 {
2751         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2752         u16 *data = (u16 *)&rq->ifr_data;
2753         unsigned long flags;
2754         int retval;
2755
2756         spin_lock_irqsave(&sc->sbm_lock, flags);
2757         retval = 0;
2758
2759         switch(cmd) {
2760         case SIOCDEVPRIVATE:            /* Get the address of the PHY in use. */
2761                 data[0] = sc->sbm_phys[0] & 0x1f;
2762                 /* Fall Through */
2763         case SIOCDEVPRIVATE+1:          /* Read the specified MII register. */
2764                 data[3] = sbmac_mii_read(sc, data[0] & 0x1f, data[1] & 0x1f);
2765                 break;
2766         case SIOCDEVPRIVATE+2:          /* Write the specified MII register */
2767                 if (!capable(CAP_NET_ADMIN)) {
2768                         retval = -EPERM;
2769                         break;
2770                 }
2771                 if (debug > 1) {
2772                     printk(KERN_DEBUG "%s: sbmac_mii_ioctl: write %02X %02X %02X\n",dev->name,
2773                        data[0],data[1],data[2]);
2774                     }
2775                 sbmac_mii_write(sc, data[0] & 0x1f, data[1] & 0x1f, data[2]);
2776                 break;
2777         default:
2778                 retval = -EOPNOTSUPP;
2779         }
2780
2781         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2782         return retval;
2783 }
2784
2785 static int sbmac_close(struct net_device *dev)
2786 {
2787         struct sbmac_softc *sc = (struct sbmac_softc *)dev->priv;
2788         unsigned long flags;
2789
2790         sbmac_set_channel_state(sc,sbmac_state_off);
2791
2792         del_timer_sync(&sc->sbm_timer);
2793
2794         spin_lock_irqsave(&sc->sbm_lock, flags);
2795
2796         netif_stop_queue(dev);
2797
2798         if (debug > 1) {
2799                 printk(KERN_DEBUG "%s: Shutting down ethercard\n",dev->name);
2800         }
2801
2802         spin_unlock_irqrestore(&sc->sbm_lock, flags);
2803
2804         /* Make sure there is no irq-handler running on a different CPU. */
2805         synchronize_irq();
2806
2807         free_irq(dev->irq, dev);
2808
2809         sbdma_emptyring(&(sc->sbm_txdma));
2810         sbdma_emptyring(&(sc->sbm_rxdma));
2811
2812         MOD_DEC_USE_COUNT;
2813
2814         return 0;
2815 }
2816
2817
2818
2819 #if defined(SBMAC_ETH0_HWADDR) || defined(SBMAC_ETH1_HWADDR) || defined(SBMAC_ETH2_HWADDR)
2820 static void
2821 sbmac_setup_hwaddr(int chan,char *addr)
2822 {
2823         uint8_t eaddr[6];
2824         uint64_t val;
2825         sbmac_port_t port;
2826
2827         port = A_MAC_CHANNEL_BASE(chan);
2828         sbmac_parse_hwaddr(addr,eaddr);
2829         val = sbmac_addr2reg(eaddr);
2830         SBMAC_WRITECSR(PKSEG1(port+R_MAC_ETHERNET_ADDR),val);
2831         val = SBMAC_READCSR(PKSEG1(port+R_MAC_ETHERNET_ADDR));
2832 }
2833 #endif
2834
2835 static struct net_device *dev_sbmac[MAX_UNITS] = {0,0,0};
2836
2837 static int __init
2838 sbmac_init_module(void)
2839 {
2840         int idx;
2841         int macidx = 0;
2842         struct net_device *dev;
2843         sbmac_port_t port;
2844         int chip_max_units;
2845
2846         /*
2847          * For bringup when not using the firmware, we can pre-fill
2848          * the MAC addresses using the environment variables
2849          * specified in this file (or maybe from the config file?)
2850          */
2851 #ifdef SBMAC_ETH0_HWADDR
2852         sbmac_setup_hwaddr(0,SBMAC_ETH0_HWADDR);
2853 #endif
2854 #ifdef SBMAC_ETH1_HWADDR
2855         sbmac_setup_hwaddr(1,SBMAC_ETH1_HWADDR);
2856 #endif
2857 #ifdef SBMAC_ETH2_HWADDR
2858         sbmac_setup_hwaddr(2,SBMAC_ETH2_HWADDR);
2859 #endif
2860
2861         /*
2862          * Walk through the Ethernet controllers and find
2863          * those who have their MAC addresses set.
2864          */
2865         chip_revision = SBMAC_READCSR(PKSEG1(A_SCD_SYSTEM_REVISION));
2866         switch ((int)G_SYS_PART(chip_revision)) {
2867         case 0x1150:
2868         case 0x1250:
2869                 chip_max_units = 3;
2870                 break;
2871         case 0x1120:
2872         case 0x1125:
2873         case 0x1126:
2874                 chip_max_units = 2;
2875                 break;
2876         default:
2877                 chip_max_units = 0;
2878                 break;
2879         }
2880         if (chip_max_units > MAX_UNITS)
2881                 chip_max_units = MAX_UNITS;
2882
2883         for (idx = 0; idx < chip_max_units; idx++) {
2884
2885                 /*
2886                  * This is the base address of the MAC.
2887                  */
2888
2889                 port = A_MAC_CHANNEL_BASE(idx);
2890
2891                 /*
2892                  * The R_MAC_ETHERNET_ADDR register will be set to some nonzero
2893                  * value for us by the firmware if we're going to use this MAC.
2894                  * If we find a zero, skip this MAC.
2895                  */
2896
2897                 sbmac_orig_hwaddr[idx] = SBMAC_READCSR(PKSEG1(port+R_MAC_ETHERNET_ADDR));
2898                 if (sbmac_orig_hwaddr[idx] == 0) {
2899                     printk( KERN_DEBUG "sbmac: not configuring MAC at %x\n",(uint32_t)port);
2900                     continue;
2901                 }
2902
2903                 /*
2904                  * Okay, cool.  Initialize this MAC.
2905                  */
2906
2907                 dev = init_etherdev(NULL,sizeof(struct sbmac_softc));
2908                 if (!dev)
2909                   return -ENOMEM;       /* return ENOMEM */
2910
2911                 dev->irq = K_INT_MAC_0 + idx;
2912                 dev->base_addr = port;
2913                 dev->mem_end = 0;
2914                 /*dev->init = sbmac_init;*/
2915                 sbmac_init(dev);
2916
2917                 dev_sbmac[macidx] = dev;
2918                 macidx++;
2919
2920         }
2921
2922         /*
2923          * Should we care, 'macidx' is the total number of enabled MACs.
2924          */
2925
2926         return 0;
2927 }
2928
2929
2930 static void __exit
2931 sbmac_cleanup_module(void)
2932 {
2933         int idx;
2934         struct net_device *dev;
2935         sbmac_port_t port;
2936         for (idx = 0; idx < MAX_UNITS; idx++) {
2937                 dev = dev_sbmac[idx];
2938                 if (dev == NULL) continue;
2939                 if (dev->priv != NULL) {
2940                         struct sbmac_softc *sc = (struct sbmac_softc *) dev->priv;
2941
2942                         unregister_netdev(dev);
2943
2944                         sbmac_uninitctx(sc);
2945
2946                 }
2947
2948                 port = A_MAC_CHANNEL_BASE(idx);
2949                 SBMAC_WRITECSR(PKSEG1(port+R_MAC_ETHERNET_ADDR), sbmac_orig_hwaddr[idx] );
2950                 KFREE(dev);
2951                 dev_sbmac[idx] = NULL;
2952         }
2953 }
2954
2955 module_init(sbmac_init_module);
2956 module_exit(sbmac_cleanup_module);