1 /*------------------------------------------------------------------------
2 . smc91111.h - macros for the LAN91C111 Ethernet Driver
4 . Copyright (C) 2001 Standard Microsystems Corporation (SMSC)
5 . Developed by Simple Network Magic Corporation (SNMC)
6 . Copyright (C) 1996 by Erik Stahlman (ES)
8 . This program is free software; you can redistribute it and/or modify
9 . it under the terms of the GNU General Public License as published by
10 . the Free Software Foundation; either version 2 of the License, or
11 . (at your option) any later version.
13 . This program is distributed in the hope that it will be useful,
14 . but WITHOUT ANY WARRANTY; without even the implied warranty of
15 . MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 . GNU General Public License for more details.
18 . You should have received a copy of the GNU General Public License
19 . along with this program; if not, write to the Free Software
20 . Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 . This file contains register information and access macros for
23 . the LAN91C111 single chip ethernet controller. It is a modified
24 . version of the smc9194.h file.
26 . Information contained in this file was obtained from the LAN91C111
27 . manual from SMC. To get a copy, if you really want one, you can find
28 . information under www.smsc.com.
31 . Erik Stahlman ( erik@vt.edu )
32 . Daris A Nevil ( dnevil@snmc.com )
35 . 03/16/01 Daris A Nevil Modified for use with LAN91C111 device
37 ---------------------------------------------------------------------------*/
41 /* I want some simple types */
43 typedef unsigned char byte;
44 typedef unsigned short word;
45 typedef unsigned long int dword;
49 . Do you want to use 8 bit xfers? This should work on all chips, as the
50 . chipset is designed to accommodate them, although some hardware engineers
51 . do not connect byte enables so 8 bit xfers can not be used.
53 #ifdef CONFIG_SMC91111_USE_8_BIT
54 #define SMC_inb(port) inb(port)
55 #define SMC_insb(port,buf,ns) insb((port),(buf),(ns))
56 #define SMC_outb(val,port) outb((val),(port))
57 #define SMC_outsb(port,buf,ns) outsb((port),(buf),(ns))
58 #endif /* CONFIG_SMC91111_USE_8_BIT */
60 /* Define 16 bit xfers. */
61 #ifdef CONFIG_SMC91111_BYTE_SWAP
62 #define SMC_inw(port) swab16(inw(port))
63 #define SMC_insw(port,buf,ns) \
65 unsigned long __port = (port); \
66 word *__buf = (word *)(buf); \
68 insw(__port,__buf,__ns); \
70 *__buf = swab16(*__buf); \
75 #define SMC_outw(val,port) outw(swab16(val),(port))
76 #define SMC_outsw(port,buf,ns) \
78 unsigned long __port = (port); \
79 word *__buf = (word *)(buf); \
82 /* Believe it or not, the swab isn't needed. */ \
83 outw( /* swab16 */ (*__buf++), __port); \
87 #else /* CONFIG_SMC91111_BYTE_SWAP is not defined */
88 #define SMC_inw(port) inw(port)
89 #define SMC_insw(port,buf,ns) insw((port),(buf),(ns))
90 #define SMC_outw(val,port) outw((val),(port))
91 #define SMC_outsw(port,buf,ns) outsw((port),(buf),(ns))
92 #endif /* CONFIG_SMC91111_BYTE_SWAP */
95 . Do you want to use 32 bit xfers? This should work on all chips, as the
96 . chipset is designed to accommodate them, although some hardware engineers
97 . do not connect all 32 data bits so 32 bit xfers can not be used.
99 #ifdef CONFIG_SMC91111_USE_32_BIT
100 #ifdef CONFIG_SMC91111_BYTE_SWAP
101 #define SMC_inl(port) swab32(inl(port))
102 #define SMC_insl(port,buf,ns) \
104 unsigned long __port = (port); \
105 dword *__buf = (dword *)(buf); \
107 insl(__port,__buf,__ns); \
109 *__buf = swab32(*__buf); \
114 #define SMC_outl(val,port) outl(swab32(val),(port))
115 #define SMC_outsl(port,buf,ns) \
117 unsigned long __port = (port); \
118 dword *__buf = (dword *)(buf); \
121 /* Believe it or not, the swab isn't needed. */ \
122 outl( /* swab32 */ (*__buf++), __port); \
126 #else /* CONFIG_SMC91111_BYTE_SWAP is not defined */
127 #define SMC_inl(port) inl(port)
128 #define SMC_insl(port,buf,ns) insl((port),(buf),(ns))
129 #define SMC_outl(val,port) outl((val),(port))
130 #define SMC_outsl(port,buf,ns) outsl((port),(buf),(ns))
131 #endif /* CONFIG_SMC91111_BYTE_SWAP */
132 #endif /* CONFIG_SMC91111_USE_32_BIT */
135 /* Because of bank switching, the LAN91xxx uses only 16 I/O ports */
137 #define SMC_IO_EXTENT 16
140 /*---------------------------------------------------------------
142 . A description of the SMSC registers is probably in order here,
143 . although for details, the SMC datasheet is invaluable.
145 . Basically, the chip has 4 banks of registers ( 0 to 3 ), which
146 . are accessed by writing a number into the BANK_SELECT register
147 . ( I also use a SMC_SELECT_BANK macro for this ).
149 . The banks are configured so that for most purposes, bank 2 is all
150 . that is needed for simple run time tasks.
151 -----------------------------------------------------------------------*/
154 . Bank Select Register:
156 . yyyy yyyy 0000 00xx
158 . yyyy yyyy = 0x33, for identification purposes.
160 #define BANK_SELECT 14
162 // Transmit Control Register
164 #define TCR_REG 0x0000 // transmit control register
165 #define TCR_ENABLE 0x0001 // When 1 we can transmit
166 #define TCR_LOOP 0x0002 // Controls output pin LBK
167 #define TCR_FORCOL 0x0004 // When 1 will force a collision
168 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
169 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
170 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
171 #define TCR_FDUPLX 0x0800 // When 1 enables full duplex operation
172 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
173 #define TCR_EPH_LOOP 0x2000 // When 1 enables EPH block loopback
174 #define TCR_SWFDUP 0x8000 // When 1 enables Switched Full Duplex mode
176 #define TCR_CLEAR 0 /* do NOTHING */
177 /* the default settings for the TCR register : */
178 /* QUESTION: do I want to enable padding of short packets ? */
179 #define TCR_DEFAULT TCR_ENABLE
182 // EPH Status Register
184 #define EPH_STATUS_REG 0x0002
185 #define ES_TX_SUC 0x0001 // Last TX was successful
186 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
187 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
188 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
189 #define ES_16COL 0x0010 // 16 Collisions Reached
190 #define ES_SQET 0x0020 // Signal Quality Error Test
191 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
192 #define ES_TXDEFR 0x0080 // Transmit Deferred
193 #define ES_LATCOL 0x0200 // Late collision detected on last tx
194 #define ES_LOSTCARR 0x0400 // Lost Carrier Sense
195 #define ES_EXC_DEF 0x0800 // Excessive Deferral
196 #define ES_CTR_ROL 0x1000 // Counter Roll Over indication
197 #define ES_LINK_OK 0x4000 // Driven by inverted value of nLNK pin
198 #define ES_TXUNRN 0x8000 // Tx Underrun
201 // Receive Control Register
203 #define RCR_REG 0x0004
204 #define RCR_RX_ABORT 0x0001 // Set if a rx frame was aborted
205 #define RCR_PRMS 0x0002 // Enable promiscuous mode
206 #define RCR_ALMUL 0x0004 // When set accepts all multicast frames
207 #define RCR_RXEN 0x0100 // IFF this is set, we can receive packets
208 #define RCR_STRIP_CRC 0x0200 // When set strips CRC from rx packets
209 #define RCR_ABORT_ENB 0x0200 // When set will abort rx on collision
210 #define RCR_FILT_CAR 0x0400 // When set filters leading 12 bit s of carrier
211 #define RCR_SOFTRST 0x8000 // resets the chip
213 /* the normal settings for the RCR register : */
214 #define RCR_DEFAULT (RCR_STRIP_CRC | RCR_RXEN)
215 #define RCR_CLEAR 0x0 // set it to a base state
219 #define COUNTER_REG 0x0006
221 // Memory Information Register
223 #define MIR_REG 0x0008
225 // Receive/Phy Control Register
227 #define RPC_REG 0x000A
228 #define RPC_SPEED 0x2000 // When 1 PHY is in 100Mbps mode.
229 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
230 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
231 #define RPC_LSXA_SHFT 5 // Bits to shift LS2A,LS1A,LS0A to lsb
232 #define RPC_LSXB_SHFT 2 // Bits to get LS2B,LS1B,LS0B to lsb
233 #define RPC_LED_100_10 (0x00) // LED = 100Mbps OR's with 10Mbps link detect
234 #define RPC_LED_RES (0x01) // LED = Reserved
235 #define RPC_LED_10 (0x02) // LED = 10Mbps link detect
236 #define RPC_LED_FD (0x03) // LED = Full Duplex Mode
237 #define RPC_LED_TX_RX (0x04) // LED = TX or RX packet occurred
238 #define RPC_LED_100 (0x05) // LED = 100Mbps link dectect
239 #define RPC_LED_TX (0x06) // LED = TX packet occurred
240 #define RPC_LED_RX (0x07) // LED = RX packet occurred
241 #define RPC_DEFAULT (RPC_ANEG | (RPC_LED_100 << RPC_LSXA_SHFT) | (RPC_LED_FD << RPC_LSXB_SHFT) | RPC_SPEED | RPC_DPLX)
243 /* Bank 0 0x000C is reserved */
245 // Bank Select Register
247 #define BSR_REG 0x000E
252 #define CONFIG_REG 0x0000
253 #define CONFIG_EXT_PHY 0x0200 // 1=external MII, 0=internal Phy
254 #define CONFIG_GPCNTRL 0x0400 // Inverse value drives pin nCNTRL
255 #define CONFIG_NO_WAIT 0x1000 // When 1 no extra wait states on ISA bus
256 #define CONFIG_EPH_POWER_EN 0x8000 // When 0 EPH is placed into low power mode.
258 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
259 #define CONFIG_DEFAULT (CONFIG_EPH_POWER_EN)
262 // Base Address Register
264 #define BASE_REG 0x0002
267 // Individual Address Registers
269 #define ADDR0_REG 0x0004
270 #define ADDR1_REG 0x0006
271 #define ADDR2_REG 0x0008
274 // General Purpose Register
276 #define GP_REG 0x000A
281 #define CTL_REG 0x000C
282 #define CTL_RCV_BAD 0x4000 // When 1 bad CRC packets are received
283 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
284 #define CTL_LE_ENABLE 0x0080 // When 1 enables Link Error interrupt
285 #define CTL_CR_ENABLE 0x0040 // When 1 enables Counter Rollover interrupt
286 #define CTL_TE_ENABLE 0x0020 // When 1 enables Transmit Error interrupt
287 #define CTL_EEPROM_SELECT 0x0004 // Controls EEPROM reload & store
288 #define CTL_RELOAD 0x0002 // When set reads EEPROM into registers
289 #define CTL_STORE 0x0001 // When set stores registers into EEPROM
292 // MMU Command Register
294 #define MMU_CMD_REG 0x0000
295 #define MC_BUSY 1 // When 1 the last release has not completed
296 #define MC_NOP (0<<5) // No Op
297 #define MC_ALLOC (1<<5) // OR with number of 256 byte packets
298 #define MC_RESET (2<<5) // Reset MMU to initial state
299 #define MC_REMOVE (3<<5) // Remove the current rx packet
300 #define MC_RELEASE (4<<5) // Remove and release the current rx packet
301 #define MC_FREEPKT (5<<5) // Release packet in PNR register
302 #define MC_ENQUEUE (6<<5) // Enqueue the packet for transmit
303 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
306 // Packet Number Register
308 #define PN_REG 0x0002
311 // Allocation Result Register
313 #define AR_REG 0x0003
314 #define AR_FAILED 0x80 // Alocation Failed
317 // RX FIFO Ports Register
319 #define RXFIFO_REG 0x0004 // Must be read as a word
320 #define RXFIFO_REMPTY 0x8000 // RX FIFO Empty
323 // TX FIFO Ports Register
325 #define TXFIFO_REG RXFIFO_REG // Must be read as a word
326 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
331 #define PTR_REG 0x0006
332 #define PTR_RCV 0x8000 // 1=Receive area, 0=Transmit area
333 #define PTR_AUTOINC 0x4000 // Auto increment the pointer on each access
334 #define PTR_READ 0x2000 // When 1 the operation is a read
339 #define DATA_REG 0x0008
342 // Interrupt Status/Acknowledge Register
344 #define INT_REG 0x000C
347 // Interrupt Mask Register
349 #define IM_REG 0x000D
350 #define IM_MDINT 0x80 // PHY MI Register 18 Interrupt
351 #define IM_ERCV_INT 0x40 // Early Receive Interrupt
352 #define IM_EPH_INT 0x20 // Set by Etheret Protocol Handler section
353 #define IM_RX_OVRN_INT 0x10 // Set by Receiver Overruns
354 #define IM_ALLOC_INT 0x08 // Set when allocation request is completed
355 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
356 #define IM_TX_INT 0x02 // Transmit Interrrupt
357 #define IM_RCV_INT 0x01 // Receive Interrupt
360 // Multicast Table Registers
362 #define MCAST_REG1 0x0000
363 #define MCAST_REG2 0x0002
364 #define MCAST_REG3 0x0004
365 #define MCAST_REG4 0x0006
368 // Management Interface Register (MII)
370 #define MII_REG 0x0008
371 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
372 #define MII_MDOE 0x0008 // MII Output Enable
373 #define MII_MCLK 0x0004 // MII Clock, pin MDCLK
374 #define MII_MDI 0x0002 // MII Input, pin MDI
375 #define MII_MDO 0x0001 // MII Output, pin MDO
380 #define REV_REG 0x000A /* ( hi: chip id low: rev # ) */
383 // Early RCV Register
385 /* this is NOT on SMC9192 */
386 #define ERCV_REG 0x000C
387 #define ERCV_RCV_DISCRD 0x0080 // When 1 discards a packet being received
388 #define ERCV_THRESHOLD 0x001F // ERCV Threshold Mask
392 #define EXT_REG 0x0000
400 #define CHIP_91100FD 8
401 #define CHIP_91111FD 9
403 static const char * chip_ids[ 15 ] = {
405 /* 3 */ "SMC91C90/91C92",
410 /* 8 */ "SMC91C100FD",
411 /* 9 */ "SMC91C11xFD",
416 . Transmit status bits
418 #define TS_SUCCESS 0x0001
419 #define TS_LOSTCAR 0x0400
420 #define TS_LATCOL 0x0200
421 #define TS_16COL 0x0010
424 . Receive status bits
426 #define RS_ALGNERR 0x8000
427 #define RS_BRODCAST 0x4000
428 #define RS_BADCRC 0x2000
429 #define RS_ODDFRAME 0x1000 // bug: the LAN91C111 never sets this on receive
430 #define RS_TOOLONG 0x0800
431 #define RS_TOOSHORT 0x0400
432 #define RS_MULTICAST 0x0001
433 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT)
438 PHY_LAN83C183 = 1, // LAN91C111 Internal PHY
443 // PHY Register Addresses (LAN91C111 Internal PHY)
445 // PHY Control Register
446 #define PHY_CNTL_REG 0x00
447 #define PHY_CNTL_RST 0x8000 // 1=PHY Reset
448 #define PHY_CNTL_LPBK 0x4000 // 1=PHY Loopback
449 #define PHY_CNTL_SPEED 0x2000 // 1=100Mbps, 0=10Mpbs
450 #define PHY_CNTL_ANEG_EN 0x1000 // 1=Enable Auto negotiation
451 #define PHY_CNTL_PDN 0x0800 // 1=PHY Power Down mode
452 #define PHY_CNTL_MII_DIS 0x0400 // 1=MII 4 bit interface disabled
453 #define PHY_CNTL_ANEG_RST 0x0200 // 1=Reset Auto negotiate
454 #define PHY_CNTL_DPLX 0x0100 // 1=Full Duplex, 0=Half Duplex
455 #define PHY_CNTL_COLTST 0x0080 // 1= MII Colision Test
457 // PHY Status Register
458 #define PHY_STAT_REG 0x01
459 #define PHY_STAT_CAP_T4 0x8000 // 1=100Base-T4 capable
460 #define PHY_STAT_CAP_TXF 0x4000 // 1=100Base-X full duplex capable
461 #define PHY_STAT_CAP_TXH 0x2000 // 1=100Base-X half duplex capable
462 #define PHY_STAT_CAP_TF 0x1000 // 1=10Mbps full duplex capable
463 #define PHY_STAT_CAP_TH 0x0800 // 1=10Mbps half duplex capable
464 #define PHY_STAT_CAP_SUPR 0x0040 // 1=recv mgmt frames with not preamble
465 #define PHY_STAT_ANEG_ACK 0x0020 // 1=ANEG has completed
466 #define PHY_STAT_REM_FLT 0x0010 // 1=Remote Fault detected
467 #define PHY_STAT_CAP_ANEG 0x0008 // 1=Auto negotiate capable
468 #define PHY_STAT_LINK 0x0004 // 1=valid link
469 #define PHY_STAT_JAB 0x0002 // 1=10Mbps jabber condition
470 #define PHY_STAT_EXREG 0x0001 // 1=extended registers implemented
472 // PHY Identifier Registers
473 #define PHY_ID1_REG 0x02 // PHY Identifier 1
474 #define PHY_ID2_REG 0x03 // PHY Identifier 2
476 // PHY Auto-Negotiation Advertisement Register
477 #define PHY_AD_REG 0x04
478 #define PHY_AD_NP 0x8000 // 1=PHY requests exchange of Next Page
479 #define PHY_AD_ACK 0x4000 // 1=got link code word from remote
480 #define PHY_AD_RF 0x2000 // 1=advertise remote fault
481 #define PHY_AD_T4 0x0200 // 1=PHY is capable of 100Base-T4
482 #define PHY_AD_TX_FDX 0x0100 // 1=PHY is capable of 100Base-TX FDPLX
483 #define PHY_AD_TX_HDX 0x0080 // 1=PHY is capable of 100Base-TX HDPLX
484 #define PHY_AD_10_FDX 0x0040 // 1=PHY is capable of 10Base-T FDPLX
485 #define PHY_AD_10_HDX 0x0020 // 1=PHY is capable of 10Base-T HDPLX
486 #define PHY_AD_CSMA 0x0001 // 1=PHY is capable of 802.3 CMSA
488 // PHY Auto-negotiation Remote End Capability Register
489 #define PHY_RMT_REG 0x05
490 // Uses same bit definitions as PHY_AD_REG
492 // PHY Configuration Register 1
493 #define PHY_CFG1_REG 0x10
494 #define PHY_CFG1_LNKDIS 0x8000 // 1=Rx Link Detect Function disabled
495 #define PHY_CFG1_XMTDIS 0x4000 // 1=TP Transmitter Disabled
496 #define PHY_CFG1_XMTPDN 0x2000 // 1=TP Transmitter Powered Down
497 #define PHY_CFG1_BYPSCR 0x0400 // 1=Bypass scrambler/descrambler
498 #define PHY_CFG1_UNSCDS 0x0200 // 1=Unscramble Idle Reception Disable
499 #define PHY_CFG1_EQLZR 0x0100 // 1=Rx Equalizer Disabled
500 #define PHY_CFG1_CABLE 0x0080 // 1=STP(150ohm), 0=UTP(100ohm)
501 #define PHY_CFG1_RLVL0 0x0040 // 1=Rx Squelch level reduced by 4.5db
502 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
503 #define PHY_CFG1_TLVL_MASK 0x003C
504 #define PHY_CFG1_TRF_MASK 0x0003 // Transmitter Rise/Fall time
507 // PHY Configuration Register 2
508 #define PHY_CFG2_REG 0x11
509 #define PHY_CFG2_APOLDIS 0x0020 // 1=Auto Polarity Correction disabled
510 #define PHY_CFG2_JABDIS 0x0010 // 1=Jabber disabled
511 #define PHY_CFG2_MREG 0x0008 // 1=Multiple register access (MII mgt)
512 #define PHY_CFG2_INTMDIO 0x0004 // 1=Interrupt signaled with MDIO pulseo
514 // PHY Status Output (and Interrupt status) Register
515 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
516 #define PHY_INT_INT 0x8000 // 1=bits have changed since last read
517 #define PHY_INT_LNKFAIL 0x4000 // 1=Link Not detected
518 #define PHY_INT_LOSSSYNC 0x2000 // 1=Descrambler has lost sync
519 #define PHY_INT_CWRD 0x1000 // 1=Invalid 4B5B code detected on rx
520 #define PHY_INT_SSD 0x0800 // 1=No Start Of Stream detected on rx
521 #define PHY_INT_ESD 0x0400 // 1=No End Of Stream detected on rx
522 #define PHY_INT_RPOL 0x0200 // 1=Reverse Polarity detected
523 #define PHY_INT_JAB 0x0100 // 1=Jabber detected
524 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
525 #define PHY_INT_DPLXDET 0x0040 // 1=Device in Full Duplex
527 // PHY Interrupt/Status Mask Register
528 #define PHY_MASK_REG 0x13 // Interrupt Mask
529 // Uses the same bit definitions as PHY_INT_REG
533 /*-------------------------------------------------------------------------
534 . I define some macros to make it easier to do somewhat common
535 . or slightly complicated, repeated tasks.
536 --------------------------------------------------------------------------*/
538 /* select a register bank, 0 to 3 */
540 #define SMC_SELECT_BANK(x) { SMC_outw( x, ioaddr + BANK_SELECT ); }
541 #define SMC_CURRENT_BANK() SMC_inw( ioaddr + BANK_SELECT )
543 /* this enables an interrupt in the interrupt mask register */
544 #define SMC_ENABLE_INT(x) {\
547 mask = SMC_GET_INT_MASK();\
549 SMC_SET_INT_MASK(mask); \
552 /* this disables an interrupt from the interrupt mask register */
554 #define SMC_DISABLE_INT(x) {\
557 mask = SMC_GET_INT_MASK();\
559 SMC_SET_INT_MASK(mask); \
562 /* Note: the following macros do *not* select the bank. */
564 #define SMC_GET_PN() SMC_inb( ioaddr + PN_REG )
565 #define SMC_SET_PN(x) SMC_outb( (x), ioaddr + PN_REG )
566 #define SMC_GET_AR() SMC_inb( ioaddr + AR_REG )
567 #define SMC_GET_INT() SMC_inb( ioaddr + INT_REG )
568 #define SMC_ACK_INT(x) SMC_outb( (x), ioaddr + INT_REG )
569 #define SMC_GET_INT_MASK() SMC_inb( ioaddr + IM_REG )
570 #define SMC_SET_INT_MASK(x) SMC_outb( (x), ioaddr + IM_REG )
572 #define SMC_GET_PN() (SMC_inw( ioaddr + PN_REG ) & 0xFF)
573 #define SMC_SET_PN(x) SMC_outw( (x), ioaddr + PN_REG )
574 #define SMC_GET_AR() (SMC_inw( ioaddr + PN_REG ) >> 8)
575 #define SMC_GET_INT() (SMC_inw( ioaddr + INT_REG ) & 0xFF)
576 #define SMC_ACK_INT(x) SMC_outw( (SMC_GET_INT_MASK() << 8) | (x), \
578 #define SMC_GET_INT_MASK() (SMC_inw( ioaddr + INT_REG ) >> 8)
579 #define SMC_SET_INT_MASK(x) SMC_outw( (x) << 8, ioaddr + INT_REG )
582 #define SMC_GET_BASE() SMC_inw( ioaddr + BASE_REG)
583 #define SMC_SET_BASE(x) SMC_outw( (x), ioaddr + BASE_REG)
584 #define SMC_GET_CONFIG() SMC_inw( ioaddr + CONFIG_REG)
585 #define SMC_SET_CONFIG(x) SMC_outw( (x), ioaddr + CONFIG_REG)
586 #define SMC_GET_COUNTER() SMC_inw( ioaddr + COUNTER_REG)
587 #define SMC_SET_COUNTER(x) SMC_outw( (x), ioaddr + COUNTER_REG)
588 #define SMC_GET_CTL() SMC_inw( ioaddr + CTL_REG)
589 #define SMC_SET_CTL(x) SMC_outw( (x), ioaddr + CTL_REG)
590 #define SMC_GET_MII() SMC_inw( ioaddr + MII_REG)
591 #define SMC_SET_MII(x) SMC_outw( (x), ioaddr + MII_REG)
592 #define SMC_GET_MIR() SMC_inw( ioaddr + MIR_REG)
593 #define SMC_SET_MIR(x) SMC_outw( (x), ioaddr + MIR_REG)
594 #define SMC_GET_MMU_CMD() SMC_inw( ioaddr + MMU_CMD_REG)
595 #define SMC_SET_MMU_CMD(x) SMC_outw( (x), ioaddr + MMU_CMD_REG)
596 #define SMC_GET_PTR() SMC_inw( ioaddr + PTR_REG)
597 #define SMC_SET_PTR(x) SMC_outw( (x), ioaddr + PTR_REG)
598 #define SMC_GET_RCR() SMC_inw( ioaddr + RCR_REG)
599 #define SMC_SET_RCR(x) SMC_outw( (x), ioaddr + RCR_REG)
600 #define SMC_GET_REV() SMC_inw( ioaddr + REV_REG)
601 #define SMC_SET_REV(x) SMC_outw( (x), ioaddr + REV_REG)
602 #define SMC_GET_RPC() SMC_inw( ioaddr + RPC_REG)
603 #define SMC_SET_RPC(x) SMC_outw( (x), ioaddr + RPC_REG)
604 #define SMC_GET_RXFIFO() SMC_inw( ioaddr + RXFIFO_REG)
605 #define SMC_SET_RXFIFO(x) SMC_outw( (x), ioaddr + RXFIFO_REG)
606 #define SMC_GET_TCR() SMC_inw( ioaddr + TCR_REG)
607 #define SMC_SET_TCR(x) SMC_outw( (x), ioaddr + TCR_REG)
609 #define SMC_CLEAR_MCAST() {\
610 SMC_outw( 0, ioaddr + MCAST_REG1); \
611 SMC_outw( 0, ioaddr + MCAST_REG2); \
612 SMC_outw( 0, ioaddr + MCAST_REG3); \
613 SMC_outw( 0, ioaddr + MCAST_REG4); \
615 #define SMC_SET_MCAST(x) {\
618 unsigned char *mt = (x);\
619 for ( i = 0; i < 8; i += 2 ) {\
620 w = mt[i] | (mt[i + 1] << 8);\
621 SMC_outw( w, ioaddr + MCAST_REG1 + i );\
626 /*----------------------------------------------------------------------
627 . Define the interrupts that I want to receive from the card
630 . IM_EPH_INT, for nasty errors
631 . IM_RCV_INT, for happy received packets
632 . IM_RX_OVRN_INT, because I have to kick the receiver
633 . IM_MDINT, for PHY Register 18 Status Changes
634 --------------------------------------------------------------------------*/
635 #define SMC_INTERRUPT_MASK (IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | \
641 * Declarations for the sysctl interface, which allows users the ability to
642 * control the finer aspects of the LAN91C111 chip. Since the smc
643 * module currently registers its sysctl table dynamically, the sysctl path
644 * for module FOO is /proc/sys/dev/ethX/FOO
646 #define CTL_SMC (CTL_BUS+1389) // arbitrary and hopefully unused
649 CTL_SMC_INFO = 1, // Sysctl files information
650 CTL_SMC_SWVER, // Driver Software Version Info
651 CTL_SMC_SWFDUP, // Switched Full Duplex Mode
652 CTL_SMC_EPHLOOP, // EPH Block Internal Loopback
653 CTL_SMC_MIIOP, // MII Operation
654 CTL_SMC_AUTONEG, // Auto-negotiate Mode
655 CTL_SMC_RFDUPLX, // Request Full Duplex Mode
656 CTL_SMC_RSPEED, // Request Speed Selection
657 CTL_SMC_AFDUPLX, // Actual Full Duplex Mode
658 CTL_SMC_ASPEED, // Actual Speed Selection
659 CTL_SMC_LNKFAIL, // Link Failed
660 CTL_SMC_FORCOL, // Force a Collision
661 CTL_SMC_FILTCAR, // Filter Carrier
662 CTL_SMC_FREEMEM, // Free Buffer Memory
663 CTL_SMC_TOTMEM, // Total Buffer Memory
664 CTL_SMC_LEDA, // Output of LED-A
665 CTL_SMC_LEDB, // Output of LED-B
666 CTL_SMC_CHIPREV, // LAN91C111 Chip Revision ID
668 // Register access for debugging
669 CTL_SMC_REG_BSR, // Bank Select
670 CTL_SMC_REG_TCR, // Transmit Control
671 CTL_SMC_REG_ESR, // EPH Status
672 CTL_SMC_REG_RCR, // Receive Control
673 CTL_SMC_REG_CTRR, // Counter
674 CTL_SMC_REG_MIR, // Memory Information
675 CTL_SMC_REG_RPCR, // Receive/Phy Control
676 CTL_SMC_REG_CFGR, // Configuration
677 CTL_SMC_REG_BAR, // Base Address
678 CTL_SMC_REG_IAR0, // Individual Address 0
679 CTL_SMC_REG_IAR1, // Individual Address 1
680 CTL_SMC_REG_IAR2, // Individual Address 2
681 CTL_SMC_REG_GPR, // General Purpose
682 CTL_SMC_REG_CTLR, // Control
683 CTL_SMC_REG_MCR, // MMU Command
684 CTL_SMC_REG_PNR, // Packet Number
685 CTL_SMC_REG_FPR, // FIFO Ports
686 CTL_SMC_REG_PTR, // Pointer
687 CTL_SMC_REG_DR, // Data
688 CTL_SMC_REG_ISR, // Interrupt Status
689 CTL_SMC_REG_MTR1, // Multicast Table Entry 1
690 CTL_SMC_REG_MTR2, // Multicast Table Entry 2
691 CTL_SMC_REG_MTR3, // Multicast Table Entry 3
692 CTL_SMC_REG_MTR4, // Multicast Table Entry 4
693 CTL_SMC_REG_MIIR, // Management Interface
694 CTL_SMC_REG_REVR, // Revision
695 CTL_SMC_REG_ERCVR, // Early RCV
696 CTL_SMC_REG_EXTR, // External
697 CTL_SMC_PHY_CTRL, // PHY Control
698 CTL_SMC_PHY_STAT, // PHY Status
699 CTL_SMC_PHY_ID1, // PHY ID1
700 CTL_SMC_PHY_ID2, // PHY ID2
701 CTL_SMC_PHY_ADC, // PHY Advertise Capability
702 CTL_SMC_PHY_REMC, // PHY Advertise Capability
703 CTL_SMC_PHY_CFG1, // PHY Configuration 1
704 CTL_SMC_PHY_CFG2, // PHY Configuration 2
705 CTL_SMC_PHY_INT, // PHY Interrupt/Status Output
706 CTL_SMC_PHY_MASK, // PHY Interrupt/Status Mask
708 // ---------------------------------------------------
709 CTL_SMC_LAST_ENTRY // Add new entries above the line
711 #endif // CONFIG_SYSCTL
712 #endif /* _SMC_91111_H_ */