1 /* tc35815.c: A TOSHIBA TC35815CF PCI 10/100Mbps ethernet driver for linux.
3 * Copyright 2001 MontaVista Software Inc.
4 * Author: MontaVista Software, Inc.
7 * Based on skelton.c by Donald Becker.
8 * Copyright (C) 2000-2001 Toshiba Corporation
10 * Cleaned up various non portable stuff (save_and_cli etc) and made it
11 * build on x86 platforms -- Alan Cox <alan@redhat.com> 20020302
13 * This program is free software; you can redistribute it and/or modify it
14 * under the terms of the GNU General Public License as published by the
15 * Free Software Foundation; either version 2 of the License, or (at your
16 * option) any later version.
18 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
19 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
21 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
24 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
25 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 * You should have received a copy of the GNU General Public License along
30 * with this program; if not, write to the Free Software Foundation, Inc.,
31 * 675 Mass Ave, Cambridge, MA 02139, USA.
34 * Switch to spin_lock not lock_kernel for scalability.
37 static const char *version =
38 "tc35815.c:v0.00-ac 26/07/2000 by Toshiba Corporation\n";
40 #include <linux/module.h>
42 #include <linux/kernel.h>
43 #include <linux/sched.h>
44 #include <linux/types.h>
45 #include <linux/fcntl.h>
46 #include <linux/interrupt.h>
47 #include <linux/ptrace.h>
48 #include <linux/ioport.h>
50 #include <linux/slab.h>
51 #include <linux/string.h>
52 #include <asm/system.h>
53 #include <asm/bitops.h>
56 #include <linux/errno.h>
57 #include <linux/init.h>
59 #include <linux/netdevice.h>
60 #include <linux/etherdevice.h>
61 #include <linux/skbuff.h>
62 #include <linux/delay.h>
63 #include <linux/pci.h>
64 #include <linux/proc_fs.h>
65 #include <asm/byteorder.h>
69 * The name of the card. Is used for messages and in the requests for
70 * io regions, irqs and dma channels
72 static const char* cardname = "TC35815CF";
73 #define TC35815_PROC_ENTRY "net/tc35815"
75 #define TC35815_MODULE_NAME "TC35815CF"
76 #define TX_TIMEOUT (4*HZ)
78 /* First, a few definitions that the brave might change. */
80 /* use 0 for production, 1 for verification, >2 for debug */
82 #define TC35815_DEBUG 1
84 static unsigned int tc35815_debug = TC35815_DEBUG;
86 #define GATHER_TXINT /* On-Demand Tx Interrupt */
88 #define vtonocache(p) KSEG1ADDR(virt_to_phys(p))
94 volatile __u32 DMA_Ctl; /* 0x00 */
95 volatile __u32 TxFrmPtr;
96 volatile __u32 TxThrsh;
97 volatile __u32 TxPollCtr;
98 volatile __u32 BLFrmPtr;
99 volatile __u32 RxFragSize;
100 volatile __u32 Int_En;
101 volatile __u32 FDA_Bas;
102 volatile __u32 FDA_Lim; /* 0x20 */
103 volatile __u32 Int_Src;
104 volatile __u32 unused0[2];
105 volatile __u32 PauseCnt;
106 volatile __u32 RemPauCnt;
107 volatile __u32 TxCtlFrmStat;
108 volatile __u32 unused1;
109 volatile __u32 MAC_Ctl; /* 0x40 */
110 volatile __u32 CAM_Ctl;
111 volatile __u32 Tx_Ctl;
112 volatile __u32 Tx_Stat;
113 volatile __u32 Rx_Ctl;
114 volatile __u32 Rx_Stat;
115 volatile __u32 MD_Data;
116 volatile __u32 MD_CA;
117 volatile __u32 CAM_Adr; /* 0x60 */
118 volatile __u32 CAM_Data;
119 volatile __u32 CAM_Ena;
120 volatile __u32 PROM_Ctl;
121 volatile __u32 PROM_Data;
122 volatile __u32 Algn_Cnt;
123 volatile __u32 CRC_Cnt;
124 volatile __u32 Miss_Cnt;
130 /* DMA_Ctl bit asign ------------------------------------------------------- */
131 #define DMA_IntMask 0x00040000 /* 1:Interupt mask */
132 #define DMA_SWIntReq 0x00020000 /* 1:Software Interrupt request */
133 #define DMA_TxWakeUp 0x00010000 /* 1:Transmit Wake Up */
134 #define DMA_RxBigE 0x00008000 /* 1:Receive Big Endian */
135 #define DMA_TxBigE 0x00004000 /* 1:Transmit Big Endian */
136 #define DMA_TestMode 0x00002000 /* 1:Test Mode */
137 #define DMA_PowrMgmnt 0x00001000 /* 1:Power Management */
138 #define DMA_DmBurst_Mask 0x000001fc /* DMA Burst size */
140 /* RxFragSize bit asign ---------------------------------------------------- */
141 #define RxFrag_EnPack 0x00008000 /* 1:Enable Packing */
142 #define RxFrag_MinFragMask 0x00000ffc /* Minimum Fragment */
144 /* MAC_Ctl bit asign ------------------------------------------------------- */
145 #define MAC_Link10 0x00008000 /* 1:Link Status 10Mbits */
146 #define MAC_EnMissRoll 0x00002000 /* 1:Enable Missed Roll */
147 #define MAC_MissRoll 0x00000400 /* 1:Missed Roll */
148 #define MAC_Loop10 0x00000080 /* 1:Loop 10 Mbps */
149 #define MAC_Conn_Auto 0x00000000 /*00:Connection mode (Automatic) */
150 #define MAC_Conn_10M 0x00000020 /*01: (10Mbps endec)*/
151 #define MAC_Conn_Mll 0x00000040 /*10: (Mll clock) */
152 #define MAC_MacLoop 0x00000010 /* 1:MAC Loopback */
153 #define MAC_FullDup 0x00000008 /* 1:Full Duplex 0:Half Duplex */
154 #define MAC_Reset 0x00000004 /* 1:Software Reset */
155 #define MAC_HaltImm 0x00000002 /* 1:Halt Immediate */
156 #define MAC_HaltReq 0x00000001 /* 1:Halt request */
158 /* PROM_Ctl bit asign ------------------------------------------------------ */
159 #define PROM_Busy 0x00008000 /* 1:Busy (Start Operation) */
160 #define PROM_Read 0x00004000 /*10:Read operation */
161 #define PROM_Write 0x00002000 /*01:Write operation */
162 #define PROM_Erase 0x00006000 /*11:Erase operation */
163 /*00:Enable or Disable Writting, */
164 /* as specified in PROM_Addr. */
165 #define PROM_Addr_Ena 0x00000030 /*11xxxx:PROM Write enable */
168 /* CAM_Ctl bit asign ------------------------------------------------------- */
169 #define CAM_CompEn 0x00000010 /* 1:CAM Compare Enable */
170 #define CAM_NegCAM 0x00000008 /* 1:Reject packets CAM recognizes,*/
172 #define CAM_BroadAcc 0x00000004 /* 1:Broadcast assept */
173 #define CAM_GroupAcc 0x00000002 /* 1:Multicast assept */
174 #define CAM_StationAcc 0x00000001 /* 1:unicast accept */
176 /* CAM_Ena bit asign ------------------------------------------------------- */
177 #define CAM_ENTRY_MAX 21 /* CAM Data entry max count */
178 #define CAM_Ena_Mask ((1<<CAM_ENTRY_MAX)-1) /* CAM Enable bits (Max 21bits) */
179 #define CAM_Ena_Bit(index) (1<<(index))
180 #define CAM_ENTRY_DESTINATION 0
181 #define CAM_ENTRY_SOURCE 1
182 #define CAM_ENTRY_MACCTL 20
184 /* Tx_Ctl bit asign -------------------------------------------------------- */
185 #define Tx_En 0x00000001 /* 1:Transmit enable */
186 #define Tx_TxHalt 0x00000002 /* 1:Transmit Halt Request */
187 #define Tx_NoPad 0x00000004 /* 1:Suppress Padding */
188 #define Tx_NoCRC 0x00000008 /* 1:Suppress Padding */
189 #define Tx_FBack 0x00000010 /* 1:Fast Back-off */
190 #define Tx_EnUnder 0x00000100 /* 1:Enable Underrun */
191 #define Tx_EnExDefer 0x00000200 /* 1:Enable Excessive Deferral */
192 #define Tx_EnLCarr 0x00000400 /* 1:Enable Lost Carrier */
193 #define Tx_EnExColl 0x00000800 /* 1:Enable Excessive Collision */
194 #define Tx_EnLateColl 0x00001000 /* 1:Enable Late Collision */
195 #define Tx_EnTxPar 0x00002000 /* 1:Enable Transmit Parity */
196 #define Tx_EnComp 0x00004000 /* 1:Enable Completion */
198 /* Tx_Stat bit asign ------------------------------------------------------- */
199 #define Tx_TxColl_MASK 0x0000000F /* Tx Collision Count */
200 #define Tx_ExColl 0x00000010 /* Excessive Collision */
201 #define Tx_TXDefer 0x00000020 /* Transmit Defered */
202 #define Tx_Paused 0x00000040 /* Transmit Paused */
203 #define Tx_IntTx 0x00000080 /* Interrupt on Tx */
204 #define Tx_Under 0x00000100 /* Underrun */
205 #define Tx_Defer 0x00000200 /* Deferral */
206 #define Tx_NCarr 0x00000400 /* No Carrier */
207 #define Tx_10Stat 0x00000800 /* 10Mbps Status */
208 #define Tx_LateColl 0x00001000 /* Late Collision */
209 #define Tx_TxPar 0x00002000 /* Tx Parity Error */
210 #define Tx_Comp 0x00004000 /* Completion */
211 #define Tx_Halted 0x00008000 /* Tx Halted */
212 #define Tx_SQErr 0x00010000 /* Signal Quality Error(SQE) */
214 /* Rx_Ctl bit asign -------------------------------------------------------- */
215 #define Rx_EnGood 0x00004000 /* 1:Enable Good */
216 #define Rx_EnRxPar 0x00002000 /* 1:Enable Receive Parity */
217 #define Rx_EnLongErr 0x00000800 /* 1:Enable Long Error */
218 #define Rx_EnOver 0x00000400 /* 1:Enable OverFlow */
219 #define Rx_EnCRCErr 0x00000200 /* 1:Enable CRC Error */
220 #define Rx_EnAlign 0x00000100 /* 1:Enable Alignment */
221 #define Rx_IgnoreCRC 0x00000040 /* 1:Ignore CRC Value */
222 #define Rx_StripCRC 0x00000010 /* 1:Strip CRC Value */
223 #define Rx_ShortEn 0x00000008 /* 1:Short Enable */
224 #define Rx_LongEn 0x00000004 /* 1:Long Enable */
225 #define Rx_RxHalt 0x00000002 /* 1:Receive Halt Request */
226 #define Rx_RxEn 0x00000001 /* 1:Receive Intrrupt Enable */
228 /* Rx_Stat bit asign ------------------------------------------------------- */
229 #define Rx_Halted 0x00008000 /* Rx Halted */
230 #define Rx_Good 0x00004000 /* Rx Good */
231 #define Rx_RxPar 0x00002000 /* Rx Parity Error */
232 /* 0x00001000 not use */
233 #define Rx_LongErr 0x00000800 /* Rx Long Error */
234 #define Rx_Over 0x00000400 /* Rx Overflow */
235 #define Rx_CRCErr 0x00000200 /* Rx CRC Error */
236 #define Rx_Align 0x00000100 /* Rx Alignment Error */
237 #define Rx_10Stat 0x00000080 /* Rx 10Mbps Status */
238 #define Rx_IntRx 0x00000040 /* Rx Interrupt */
239 #define Rx_CtlRecd 0x00000020 /* Rx Control Receive */
241 #define Rx_Stat_Mask 0x0000EFC0 /* Rx All Status Mask */
243 /* Int_En bit asign -------------------------------------------------------- */
244 #define Int_NRAbtEn 0x00000800 /* 1:Non-recoverable Abort Enable */
245 #define Int_TxCtlCmpEn 0x00000400 /* 1:Transmit Control Complete Enable */
246 #define Int_DmParErrEn 0x00000200 /* 1:DMA Parity Error Enable */
247 #define Int_DParDEn 0x00000100 /* 1:Data Parity Error Enable */
248 #define Int_EarNotEn 0x00000080 /* 1:Early Notify Enable */
249 #define Int_DParErrEn 0x00000040 /* 1:Detected Parity Error Enable */
250 #define Int_SSysErrEn 0x00000020 /* 1:Signalled System Error Enable */
251 #define Int_RMasAbtEn 0x00000010 /* 1:Received Master Abort Enable */
252 #define Int_RTargAbtEn 0x00000008 /* 1:Received Target Abort Enable */
253 #define Int_STargAbtEn 0x00000004 /* 1:Signalled Target Abort Enable */
254 #define Int_BLExEn 0x00000002 /* 1:Buffer List Exhausted Enable */
255 #define Int_FDAExEn 0x00000001 /* 1:Free Descriptor Area */
256 /* Exhausted Enable */
258 /* Int_Src bit asign ------------------------------------------------------- */
259 #define Int_NRabt 0x00004000 /* 1:Non Recoverable error */
260 #define Int_DmParErrStat 0x00002000 /* 1:DMA Parity Error & Clear */
261 #define Int_BLEx 0x00001000 /* 1:Buffer List Empty & Clear */
262 #define Int_FDAEx 0x00000800 /* 1:FDA Empty & Clear */
263 #define Int_IntNRAbt 0x00000400 /* 1:Non Recoverable Abort */
264 #define Int_IntCmp 0x00000200 /* 1:MAC control packet complete */
265 #define Int_IntExBD 0x00000100 /* 1:Interrupt Extra BD & Clear */
266 #define Int_DmParErr 0x00000080 /* 1:DMA Parity Error & Clear */
267 #define Int_IntEarNot 0x00000040 /* 1:Receive Data write & Clear */
268 #define Int_SWInt 0x00000020 /* 1:Software request & Clear */
269 #define Int_IntBLEx 0x00000010 /* 1:Buffer List Empty & Clear */
270 #define Int_IntFDAEx 0x00000008 /* 1:FDA Empty & Clear */
271 #define Int_IntPCI 0x00000004 /* 1:PCI controller & Clear */
272 #define Int_IntMacRx 0x00000002 /* 1:Rx controller & Clear */
273 #define Int_IntMacTx 0x00000001 /* 1:Tx controller & Clear */
275 /* MD_CA bit asign --------------------------------------------------------- */
276 #define MD_CA_PreSup 0x00001000 /* 1:Preamble Supress */
277 #define MD_CA_Busy 0x00000800 /* 1:Busy (Start Operation) */
278 #define MD_CA_Wr 0x00000400 /* 1:Write 0:Read */
281 /* MII register offsets */
282 #define MII_CONTROL 0x0000
283 #define MII_STATUS 0x0001
284 #define MII_PHY_ID0 0x0002
285 #define MII_PHY_ID1 0x0003
286 #define MII_ANAR 0x0004
287 #define MII_ANLPAR 0x0005
288 #define MII_ANER 0x0006
289 /* MII Control register bit definitions. */
290 #define MIICNTL_FDX 0x0100
291 #define MIICNTL_RST_AUTO 0x0200
292 #define MIICNTL_ISOLATE 0x0400
293 #define MIICNTL_PWRDWN 0x0800
294 #define MIICNTL_AUTO 0x1000
295 #define MIICNTL_SPEED 0x2000
296 #define MIICNTL_LPBK 0x4000
297 #define MIICNTL_RESET 0x8000
298 /* MII Status register bit significance. */
299 #define MIISTAT_EXT 0x0001
300 #define MIISTAT_JAB 0x0002
301 #define MIISTAT_LINK 0x0004
302 #define MIISTAT_CAN_AUTO 0x0008
303 #define MIISTAT_FAULT 0x0010
304 #define MIISTAT_AUTO_DONE 0x0020
305 #define MIISTAT_CAN_T 0x0800
306 #define MIISTAT_CAN_T_FDX 0x1000
307 #define MIISTAT_CAN_TX 0x2000
308 #define MIISTAT_CAN_TX_FDX 0x4000
309 #define MIISTAT_CAN_T4 0x8000
310 /* MII Auto-Negotiation Expansion/RemoteEnd Register Bits */
311 #define MII_AN_TX_FDX 0x0100
312 #define MII_AN_TX_HDX 0x0080
313 #define MII_AN_10_FDX 0x0040
314 #define MII_AN_10_HDX 0x0020
321 /* Frame descripter */
323 volatile __u32 FDNext;
324 volatile __u32 FDSystem;
325 volatile __u32 FDStat;
326 volatile __u32 FDCtl;
329 /* Buffer descripter */
331 volatile __u32 BuffData;
332 volatile __u32 BDCtl;
337 /* Frame Descripter bit asign ---------------------------------------------- */
338 #define FD_FDLength_MASK 0x0000FFFF /* Length MASK */
339 #define FD_BDCnt_MASK 0x001F0000 /* BD count MASK in FD */
340 #define FD_FrmOpt_MASK 0x7C000000 /* Frame option MASK */
341 #define FD_FrmOpt_BigEndian 0x40000000 /* Tx/Rx */
342 #define FD_FrmOpt_IntTx 0x20000000 /* Tx only */
343 #define FD_FrmOpt_NoCRC 0x10000000 /* Tx only */
344 #define FD_FrmOpt_NoPadding 0x08000000 /* Tx only */
345 #define FD_FrmOpt_Packing 0x04000000 /* Rx only */
346 #define FD_CownsFD 0x80000000 /* FD Controller owner bit */
347 #define FD_Next_EOL 0x00000001 /* FD EOL indicator */
348 #define FD_BDCnt_SHIFT 16
350 /* Buffer Descripter bit asign --------------------------------------------- */
351 #define BD_BuffLength_MASK 0x0000FFFF /* Recieve Data Size */
352 #define BD_RxBDID_MASK 0x00FF0000 /* BD ID Number MASK */
353 #define BD_RxBDSeqN_MASK 0x7F000000 /* Rx BD Sequence Number */
354 #define BD_CownsBD 0x80000000 /* BD Controller owner bit */
355 #define BD_RxBDID_SHIFT 16
356 #define BD_RxBDSeqN_SHIFT 24
359 /* Some useful constants. */
360 #undef NO_CHECK_CARRIER /* Does not check No-Carrier with TP */
362 #ifdef NO_CHECK_CARRIER
363 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
364 Tx_EnExColl | Tx_EnLCarr | Tx_EnExDefer | Tx_EnUnder | \
365 Tx_En) /* maybe 0x7d01 */
367 #define TX_CTL_CMD (Tx_EnComp | Tx_EnTxPar | Tx_EnLateColl | \
368 Tx_EnExColl | Tx_EnExDefer | Tx_EnUnder | \
369 Tx_En) /* maybe 0x7f01 */
371 #define RX_CTL_CMD (Rx_EnGood | Rx_EnRxPar | Rx_EnLongErr | Rx_EnOver \
372 | Rx_EnCRCErr | Rx_EnAlign | Rx_RxEn) /* maybe 0x6f01 */
374 #define INT_EN_CMD (Int_NRAbtEn | \
375 Int_DParDEn | Int_DParErrEn | \
376 Int_SSysErrEn | Int_RMasAbtEn | Int_RTargAbtEn | \
378 Int_BLExEn | Int_FDAExEn) /* maybe 0xb7f*/
380 /* Tuning parameters */
381 #define DMA_BURST_SIZE 32
382 #define TX_THRESHOLD 1024
384 #define FD_PAGE_NUM 2
385 #define FD_PAGE_ORDER 1
386 /* 16 + RX_BUF_PAGES * 8 + RX_FD_NUM * 16 + TX_FD_NUM * 32 <= PAGE_SIZE*2 */
387 #define RX_BUF_PAGES 8 /* >= 2 */
388 #define RX_FD_NUM 250 /* >= 32 */
389 #define TX_FD_NUM 128
399 struct BDesc bd[0]; /* variable length */
404 struct BDesc bd[RX_BUF_PAGES];
408 #if defined(__mips__)
410 extern unsigned long tc_readl(volatile __u32 *addr);
411 extern void tc_writel(unsigned long data, volatile __u32 *addr);
413 #define tc_readl readl
414 #define tc_writel writel
417 dma_addr_t priv_dma_handle;
419 /* Information that need to be kept for each board. */
420 struct tc35815_local {
421 struct net_device *next_module;
424 struct net_device_stats stats;
433 #define TC35815_OPT_AUTO 0x00
434 #define TC35815_OPT_10M 0x01
435 #define TC35815_OPT_100M 0x02
436 #define TC35815_OPT_FULLDUP 0x04
437 int linkspeed; /* 10 or 100 */
441 * Transmitting: Batch Mode.
443 * Receiving: Packing Mode.
444 * 1 circular FD for Free Buffer List.
445 * RX_BUG_PAGES BD in Free Buffer FD.
446 * One Free Buffer BD has PAGE_SIZE data buffer.
448 struct pci_dev *pdev;
449 dma_addr_t fd_buf_dma_handle;
450 void * fd_buf; /* for TxFD, TxFD, FrFD */
451 struct TxFD *tfd_base;
454 struct RxFD *rfd_base;
455 struct RxFD *rfd_limit;
456 struct RxFD *rfd_cur;
457 struct FrFD *fbl_ptr;
458 unsigned char fbl_curid;
459 dma_addr_t data_buf_dma_handle[RX_BUF_PAGES];
460 void * data_buf[RX_BUF_PAGES]; /* packing */
463 /* Index to functions, as function prototypes. */
465 static int __init tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq);
467 static int tc35815_open(struct net_device *dev);
468 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev);
469 static void tc35815_tx_timeout(struct net_device *dev);
470 static void tc35815_interrupt(int irq, void *dev_id, struct pt_regs *regs);
471 static void tc35815_rx(struct net_device *dev);
472 static void tc35815_txdone(struct net_device *dev);
473 static int tc35815_close(struct net_device *dev);
474 static struct net_device_stats *tc35815_get_stats(struct net_device *dev);
475 static void tc35815_set_multicast_list(struct net_device *dev);
477 static void tc35815_chip_reset(struct net_device *dev);
478 static void tc35815_chip_init(struct net_device *dev);
479 static void tc35815_phy_chip_init(struct net_device *dev);
481 /* A list of all installed tc35815 devices. */
482 static struct net_device *root_tc35815_dev = NULL;
485 * PCI device identifiers for "new style" Linux PCI Device Drivers
487 static struct pci_device_id tc35815_pci_tbl[] __devinitdata = {
488 { PCI_VENDOR_ID_TOSHIBA_2, PCI_DEVICE_ID_TOSHIBA_TC35815CF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
492 MODULE_DEVICE_TABLE (pci, tc35815_pci_tbl);
495 tc35815_probe(struct pci_dev *pdev,
496 const struct pci_device_id *ent)
498 static int called = 0;
510 unsigned long pci_memaddr;
511 unsigned int pci_irq_line;
513 printk(KERN_INFO "tc35815_probe: found device %#08x.%#08x\n", ent->vendor, ent->device);
515 pci_memaddr = pci_resource_start (pdev, 1);
517 printk(KERN_INFO " pci_memaddr=%#08lx resource_flags=%#08lx\n", pci_memaddr, pci_resource_flags (pdev, 0));
520 printk(KERN_WARNING "no PCI MEM resources, aborting\n");
523 pci_irq_line = pdev->irq;
525 if (pci_irq_line == 0) {
526 printk(KERN_WARNING "no PCI irq, aborting\n");
530 ret = tc35815_probe1(pdev, pci_memaddr, pci_irq_line);
533 if ((err = pci_enable_device(pdev)) < 0) {
534 printk(KERN_ERR "tc35815_probe: failed to enable device -- err=%d\n", err);
537 pci_set_master(pdev);
545 static int __init tc35815_probe1(struct pci_dev *pdev, unsigned int base_addr, unsigned int irq)
547 static unsigned version_printed = 0;
549 struct tc35815_local *lp;
550 struct tc35815_regs *tr;
551 struct net_device *dev;
553 /* Allocate a new 'dev' if needed. */
554 dev = init_etherdev(NULL, 0);
558 if (tc35815_debug && version_printed++ == 0)
559 printk(KERN_DEBUG "%s", version);
561 printk(KERN_INFO "%s: %s found at %#x, irq %d\n",
562 dev->name, cardname, base_addr, irq);
564 /* Fill in the 'dev' fields. */
566 dev->base_addr = (unsigned long)ioremap(base_addr,
567 sizeof(struct tc35815_regs));
568 tr = (struct tc35815_regs*)dev->base_addr;
570 tc35815_chip_reset(dev);
572 /* Retrieve and print the ethernet address. */
573 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
575 for (i = 0; i < 6; i += 2) {
577 tc_writel(PROM_Busy | PROM_Read | (i / 2 + 2), &tr->PROM_Ctl);
578 while (tc_readl(&tr->PROM_Ctl) & PROM_Busy)
580 data = tc_readl(&tr->PROM_Data);
581 dev->dev_addr[i] = data & 0xff;
582 dev->dev_addr[i+1] = data >> 8;
584 for (i = 0; i < 6; i++)
585 printk(" %2.2x", dev->dev_addr[i]);
588 /* Initialize the device structure. */
589 if (dev->priv == NULL) {
590 dev->priv = kmalloc(sizeof(struct tc35815_local), GFP_KERNEL);
591 if (dev->priv == NULL)
598 memset(lp, 0, sizeof(struct tc35815_local));
600 lp->next_module = root_tc35815_dev;
601 root_tc35815_dev = dev;
603 if (dev->mem_start > 0) {
604 lp->option = dev->mem_start;
605 if ((lp->option & TC35815_OPT_10M) &&
606 (lp->option & TC35815_OPT_100M)) {
607 /* if both speed speficied, auto select. */
608 lp->option &= ~(TC35815_OPT_10M | TC35815_OPT_100M);
612 lp->option |= TC35815_OPT_10M;
614 /* do auto negotiation */
615 tc35815_phy_chip_init(dev);
616 printk(KERN_INFO "%s: linkspeed %dMbps, %s Duplex\n",
617 dev->name, lp->linkspeed, lp->fullduplex ? "Full" : "Half");
619 dev->open = tc35815_open;
620 dev->stop = tc35815_close;
621 dev->tx_timeout = tc35815_tx_timeout;
622 dev->watchdog_timeo = TX_TIMEOUT;
623 dev->hard_start_xmit = tc35815_send_packet;
624 dev->get_stats = tc35815_get_stats;
625 dev->set_multicast_list = tc35815_set_multicast_list;
627 #if 0 /* XXX called in init_etherdev */
628 /* Fill in the fields of the device structure with ethernet values. */
637 tc35815_init_queues(struct net_device *dev)
639 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
641 unsigned long fd_addr;
644 if (sizeof(struct FDesc) +
645 sizeof(struct BDesc) * RX_BUF_PAGES +
646 sizeof(struct FDesc) * RX_FD_NUM +
647 sizeof(struct TxFD) * TX_FD_NUM > PAGE_SIZE * FD_PAGE_NUM) {
648 printk(KERN_WARNING "%s: Invalid Queue Size.\n", dev->name);
652 if ((lp->fd_buf = (void *)__get_free_pages(GFP_KERNEL, FD_PAGE_ORDER)) == 0)
654 for (i = 0; i < RX_BUF_PAGES; i++) {
655 if ((lp->data_buf[i] = (void *)get_free_page(GFP_KERNEL)) == 0) {
657 free_page((unsigned long)lp->data_buf[i]);
660 free_page((unsigned long)lp->fd_buf);
665 dma_cache_wback_inv((unsigned long)lp->data_buf[i], PAGE_SIZE * FD_PAGE_NUM);
669 dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
672 clear_page(lp->fd_buf);
674 dma_cache_wback_inv((unsigned long)lp->fd_buf, PAGE_SIZE * FD_PAGE_NUM);
678 fd_addr = (unsigned long)vtonocache(lp->fd_buf);
680 fd_addr = (unsigned long)lp->fd_buf;
683 /* Free Descriptors (for Receive) */
684 lp->rfd_base = (struct RxFD *)fd_addr;
685 fd_addr += sizeof(struct RxFD) * RX_FD_NUM;
686 for (i = 0; i < RX_FD_NUM; i++) {
687 lp->rfd_base[i].fd.FDCtl = cpu_to_le32(FD_CownsFD);
689 lp->rfd_cur = lp->rfd_base;
690 lp->rfd_limit = (struct RxFD *)(fd_addr -
691 sizeof(struct FDesc) -
692 sizeof(struct BDesc) * 30);
694 /* Transmit Descriptors */
695 lp->tfd_base = (struct TxFD *)fd_addr;
696 fd_addr += sizeof(struct TxFD) * TX_FD_NUM;
697 for (i = 0; i < TX_FD_NUM; i++) {
698 lp->tfd_base[i].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[i+1]));
699 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
700 lp->tfd_base[i].fd.FDCtl = cpu_to_le32(0);
702 lp->tfd_base[TX_FD_NUM-1].fd.FDNext = cpu_to_le32(virt_to_bus(&lp->tfd_base[0]));
706 /* Buffer List (for Receive) */
707 lp->fbl_ptr = (struct FrFD *)fd_addr;
708 lp->fbl_ptr->fd.FDNext = cpu_to_le32(virt_to_bus(lp->fbl_ptr));
709 lp->fbl_ptr->fd.FDCtl = cpu_to_le32(RX_BUF_PAGES | FD_CownsFD);
710 for (i = 0; i < RX_BUF_PAGES; i++) {
711 lp->fbl_ptr->bd[i].BuffData = cpu_to_le32(virt_to_bus(lp->data_buf[i]));
712 /* BDID is index of FrFD.bd[] */
713 lp->fbl_ptr->bd[i].BDCtl =
714 cpu_to_le32(BD_CownsBD | (i << BD_RxBDID_SHIFT) | PAGE_SIZE);
722 tc35815_clear_queues(struct net_device *dev)
724 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
727 for (i = 0; i < TX_FD_NUM; i++) {
728 struct sk_buff *skb = (struct sk_buff *)
729 le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
731 dev_kfree_skb_any(skb);
732 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
735 tc35815_init_queues(dev);
739 tc35815_free_queues(struct net_device *dev)
741 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
745 for (i = 0; i < TX_FD_NUM; i++) {
746 struct sk_buff *skb = (struct sk_buff *)
747 le32_to_cpu(lp->tfd_base[i].fd.FDSystem);
749 dev_kfree_skb_any(skb);
750 lp->tfd_base[i].fd.FDSystem = cpu_to_le32(0);
756 lp->rfd_limit = NULL;
760 for (i = 0; i < RX_BUF_PAGES; i++) {
762 free_page((unsigned long)lp->data_buf[i]);
766 __free_pages(lp->fd_buf, FD_PAGE_ORDER);
771 dump_txfd(struct TxFD *fd)
773 printk("TxFD(%p): %08x %08x %08x %08x\n", fd,
774 le32_to_cpu(fd->fd.FDNext),
775 le32_to_cpu(fd->fd.FDSystem),
776 le32_to_cpu(fd->fd.FDStat),
777 le32_to_cpu(fd->fd.FDCtl));
780 le32_to_cpu(fd->bd.BuffData),
781 le32_to_cpu(fd->bd.BDCtl));
786 dump_rxfd(struct RxFD *fd)
788 int i, bd_count = (le32_to_cpu(fd->fd.FDCtl) & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
791 printk("RxFD(%p): %08x %08x %08x %08x\n", fd,
792 le32_to_cpu(fd->fd.FDNext),
793 le32_to_cpu(fd->fd.FDSystem),
794 le32_to_cpu(fd->fd.FDStat),
795 le32_to_cpu(fd->fd.FDCtl));
796 if (le32_to_cpu(fd->fd.FDCtl) & FD_CownsFD)
799 for (i = 0; i < bd_count; i++)
801 le32_to_cpu(fd->bd[i].BuffData),
802 le32_to_cpu(fd->bd[i].BDCtl));
808 dump_frfd(struct FrFD *fd)
811 printk("FrFD(%p): %08x %08x %08x %08x\n", fd,
812 le32_to_cpu(fd->fd.FDNext),
813 le32_to_cpu(fd->fd.FDSystem),
814 le32_to_cpu(fd->fd.FDStat),
815 le32_to_cpu(fd->fd.FDCtl));
817 for (i = 0; i < RX_BUF_PAGES; i++)
819 le32_to_cpu(fd->bd[i].BuffData),
820 le32_to_cpu(fd->bd[i].BDCtl));
825 panic_queues(struct net_device *dev)
827 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
830 printk("TxFD base %p, start %d, end %d\n",
831 lp->tfd_base, lp->tfd_start, lp->tfd_end);
832 printk("RxFD base %p limit %p cur %p\n",
833 lp->rfd_base, lp->rfd_limit, lp->rfd_cur);
834 printk("FrFD %p\n", lp->fbl_ptr);
835 for (i = 0; i < TX_FD_NUM; i++)
836 dump_txfd(&lp->tfd_base[i]);
837 for (i = 0; i < RX_FD_NUM; i++) {
838 int bd_count = dump_rxfd(&lp->rfd_base[i]);
839 i += (bd_count + 1) / 2; /* skip BDs */
841 dump_frfd(lp->fbl_ptr);
842 panic("%s: Illegal queue state.", dev->name);
846 static void print_buf(char *add, int length)
851 printk("print_buf(%08x)(%x)\n", (unsigned int) add,length);
855 for (i = 0; i < len; i++) {
856 printk(" %2.2X", (unsigned char) add[i]);
864 static void print_eth(char *add)
868 printk("print_eth(%08x)\n", (unsigned int) add);
869 for (i = 0; i < 6; i++)
870 printk(" %2.2X", (unsigned char) add[i + 6]);
872 for (i = 0; i < 6; i++)
873 printk(" %2.2X", (unsigned char) add[i]);
874 printk(" : %2.2X%2.2X\n", (unsigned char) add[12], (unsigned char) add[13]);
878 * Open/initialize the board. This is called (in the current kernel)
879 * sometime after booting when the 'ifconfig' program is run.
881 * This routine should set everything up anew at each open, even
882 * registers that "should" only need to be set once at boot, so that
883 * there is non-reboot way to recover if something goes wrong.
886 tc35815_open(struct net_device *dev)
888 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
890 * This is used if the interrupt line can turned off (shared).
891 * See 3c503.c for an example of selecting the IRQ at config-time.
895 request_irq(dev->irq, &tc35815_interrupt, SA_SHIRQ, cardname, dev)) {
899 tc35815_chip_reset(dev);
901 if (tc35815_init_queues(dev) != 0) {
902 free_irq(dev->irq, dev);
906 /* Reset the hardware here. Don't forget to set the station address. */
907 tc35815_chip_init(dev);
910 netif_start_queue(dev);
917 static void tc35815_tx_timeout(struct net_device *dev)
919 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
920 struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
925 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
926 dev->name, tc_readl(&tr->Tx_Stat));
927 /* Try to restart the adaptor. */
928 tc35815_chip_reset(dev);
929 tc35815_clear_queues(dev);
930 tc35815_chip_init(dev);
932 restore_flags(flags);
933 dev->trans_start = jiffies;
934 netif_wake_queue(dev);
937 static int tc35815_send_packet(struct sk_buff *skb, struct net_device *dev)
939 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
940 struct tc35815_regs *tr = (struct tc35815_regs *)dev->base_addr;
942 if (netif_queue_stopped(dev)) {
944 * If we get here, some higher level has decided we are broken.
945 * There should really be a "kick me" function call instead.
947 int tickssofar = jiffies - dev->trans_start;
950 printk(KERN_WARNING "%s: transmit timed out, status %#x\n",
951 dev->name, tc_readl(&tr->Tx_Stat));
952 /* Try to restart the adaptor. */
953 tc35815_chip_reset(dev);
954 tc35815_clear_queues(dev);
955 tc35815_chip_init(dev);
957 dev->trans_start = jiffies;
958 netif_wake_queue(dev);
962 * Block a timer-based transmit from overlapping. This could better be
963 * done with atomic_swap(1, lp->tbusy), but set_bit() works as well.
965 if (test_and_set_bit(0, (void*)&lp->tbusy) != 0) {
966 printk(KERN_WARNING "%s: Transmitter access conflict.\n", dev->name);
967 dev_kfree_skb_any(skb);
969 short length = ETH_ZLEN < skb->len ? skb->len : ETH_ZLEN;
970 unsigned char *buf = skb->data;
971 struct TxFD *txfd = &lp->tfd_base[lp->tfd_start];
973 lp->stats.tx_bytes += skb->len;
977 dma_cache_wback_inv((unsigned long)buf, length);
984 if (lp->tfd_start != lp->tfd_end)
988 txfd->bd.BuffData = cpu_to_le32(virt_to_bus(buf));
990 txfd->bd.BDCtl = cpu_to_le32(length);
991 txfd->fd.FDSystem = cpu_to_le32((__u32)skb);
992 txfd->fd.FDCtl = cpu_to_le32(FD_CownsFD | (1 << FD_BDCnt_SHIFT));
994 if (lp->tfd_start == lp->tfd_end) {
995 /* Start DMA Transmitter. */
996 txfd->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
998 txfd->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1000 if (tc35815_debug > 2) {
1001 printk("%s: starting TxFD.\n", dev->name);
1003 if (tc35815_debug > 3)
1006 tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
1008 txfd->fd.FDNext &= cpu_to_le32(~FD_Next_EOL);
1009 if (tc35815_debug > 2) {
1010 printk("%s: queueing TxFD.\n", dev->name);
1012 if (tc35815_debug > 3)
1016 lp->tfd_start = (lp->tfd_start + 1) % TX_FD_NUM;
1018 dev->trans_start = jiffies;
1020 if ((lp->tfd_start + 1) % TX_FD_NUM != lp->tfd_end) {
1021 /* we can send another packet */
1023 netif_start_queue(dev);
1025 netif_stop_queue(dev);
1026 if (tc35815_debug > 1)
1027 printk(KERN_WARNING "%s: TxFD Exhausted.\n", dev->name);
1029 restore_flags(flags);
1035 #define FATAL_ERROR_INT \
1036 (Int_IntPCI | Int_DmParErr | Int_IntNRAbt)
1037 static void tc35815_fatal_error_interrupt(struct net_device *dev, int status)
1040 printk(KERN_WARNING "%s: Fatal Error Intterrupt (%#x):",
1043 if (status & Int_IntPCI)
1045 if (status & Int_DmParErr)
1046 printk(" DmParErr");
1047 if (status & Int_IntNRAbt)
1048 printk(" IntNRAbt");
1051 panic("%s: Too many fatal errors.", dev->name);
1052 printk(KERN_WARNING "%s: Resetting %s...\n", dev->name, cardname);
1053 /* Try to restart the adaptor. */
1054 tc35815_chip_reset(dev);
1055 tc35815_clear_queues(dev);
1056 tc35815_chip_init(dev);
1060 * The typical workload of the driver:
1061 * Handle the network interface interrupts.
1063 static void tc35815_interrupt(int irq, void *dev_id, struct pt_regs * regs)
1065 struct net_device *dev = dev_id;
1066 struct tc35815_regs *tr;
1067 struct tc35815_local *lp;
1068 int status, boguscount = 0;
1071 printk(KERN_WARNING "%s: irq %d for unknown device.\n", cardname, irq);
1075 tr = (struct tc35815_regs*)dev->base_addr;
1076 lp = (struct tc35815_local *)dev->priv;
1079 status = tc_readl(&tr->Int_Src);
1082 tc_writel(status, &tr->Int_Src); /* write to clear */
1084 /* Fatal errors... */
1085 if (status & FATAL_ERROR_INT) {
1086 tc35815_fatal_error_interrupt(dev, status);
1089 /* recoverable errors */
1090 if (status & Int_IntFDAEx) {
1091 /* disable FDAEx int. (until we make rooms...) */
1092 tc_writel(tc_readl(&tr->Int_En) & ~Int_FDAExEn, &tr->Int_En);
1094 "%s: Free Descriptor Area Exhausted (%#x).\n",
1096 lp->stats.rx_dropped++;
1098 if (status & Int_IntBLEx) {
1099 /* disable BLEx int. (until we make rooms...) */
1100 tc_writel(tc_readl(&tr->Int_En) & ~Int_BLExEn, &tr->Int_En);
1102 "%s: Buffer List Exhausted (%#x).\n",
1104 lp->stats.rx_dropped++;
1106 if (status & Int_IntExBD) {
1108 "%s: Excessive Buffer Descriptiors (%#x).\n",
1110 lp->stats.rx_length_errors++;
1112 /* normal notification */
1113 if (status & Int_IntMacRx) {
1114 /* Got a packet(s). */
1115 lp->lstats.rx_ints++;
1118 if (status & Int_IntMacTx) {
1119 lp->lstats.tx_ints++;
1120 tc35815_txdone(dev);
1122 } while (++boguscount < 20) ;
1127 /* We have a good packet(s), get it/them out of the buffers. */
1129 tc35815_rx(struct net_device *dev)
1131 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1132 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1135 int buf_free_count = 0;
1136 int fd_free_count = 0;
1138 while (!((fdctl = le32_to_cpu(lp->rfd_cur->fd.FDCtl)) & FD_CownsFD)) {
1139 int status = le32_to_cpu(lp->rfd_cur->fd.FDStat);
1140 int pkt_len = fdctl & FD_FDLength_MASK;
1141 struct RxFD *next_rfd;
1142 int bd_count = (fdctl & FD_BDCnt_MASK) >> FD_BDCnt_SHIFT;
1144 if (tc35815_debug > 2)
1145 dump_rxfd(lp->rfd_cur);
1146 if (status & Rx_Good) {
1147 /* Malloc up new buffer. */
1148 struct sk_buff *skb;
1149 unsigned char *data;
1152 lp->stats.rx_bytes += pkt_len;
1154 skb = dev_alloc_skb(pkt_len + 2); /* +2: for reserve */
1156 printk(KERN_NOTICE "%s: Memory squeeze, dropping packet.\n",
1158 lp->stats.rx_dropped++;
1161 skb_reserve(skb, 2); /* 16 bit alignment */
1164 data = skb_put(skb, pkt_len);
1166 /* copy from receive buffer */
1169 while (offset < pkt_len && cur_bd < bd_count) {
1170 int len = le32_to_cpu(lp->rfd_cur->bd[cur_bd].BDCtl) &
1173 bus_to_virt(le32_to_cpu(lp->rfd_cur->bd[cur_bd].BuffData));
1175 dma_cache_inv((unsigned long)rxbuf, len);
1177 memcpy(data + offset, rxbuf, len);
1181 // print_buf(data,pkt_len);
1182 if (tc35815_debug > 3)
1184 skb->protocol = eth_type_trans(skb, dev);
1186 lp->stats.rx_packets++;
1188 lp->stats.rx_errors++;
1189 /* WORKAROUND: LongErr and CRCErr means Overflow. */
1190 if ((status & Rx_LongErr) && (status & Rx_CRCErr)) {
1191 status &= ~(Rx_LongErr|Rx_CRCErr);
1194 if (status & Rx_LongErr) lp->stats.rx_length_errors++;
1195 if (status & Rx_Over) lp->stats.rx_fifo_errors++;
1196 if (status & Rx_CRCErr) lp->stats.rx_crc_errors++;
1197 if (status & Rx_Align) lp->stats.rx_frame_errors++;
1201 /* put Free Buffer back to controller */
1202 int bdctl = le32_to_cpu(lp->rfd_cur->bd[bd_count - 1].BDCtl);
1204 (bdctl & BD_RxBDID_MASK) >> BD_RxBDID_SHIFT;
1205 if (id >= RX_BUF_PAGES) {
1206 printk("%s: invalid BDID.\n", dev->name);
1209 /* free old buffers */
1210 while (lp->fbl_curid != id) {
1211 bdctl = le32_to_cpu(lp->fbl_ptr->bd[lp->fbl_curid].BDCtl);
1212 if (bdctl & BD_CownsBD) {
1213 printk("%s: Freeing invalid BD.\n",
1217 /* pass BD to controler */
1218 /* Note: BDLength was modified by chip. */
1219 lp->fbl_ptr->bd[lp->fbl_curid].BDCtl =
1220 cpu_to_le32(BD_CownsBD |
1221 (lp->fbl_curid << BD_RxBDID_SHIFT) |
1224 (lp->fbl_curid + 1) % RX_BUF_PAGES;
1225 if (tc35815_debug > 2) {
1226 printk("%s: Entering new FBD %d\n",
1227 dev->name, lp->fbl_curid);
1228 dump_frfd(lp->fbl_ptr);
1234 /* put RxFD back to controller */
1235 next_rfd = bus_to_virt(le32_to_cpu(lp->rfd_cur->fd.FDNext));
1237 next_rfd = (struct RxFD *)vtonocache(next_rfd);
1239 if (next_rfd < lp->rfd_base || next_rfd > lp->rfd_limit) {
1240 printk("%s: RxFD FDNext invalid.\n", dev->name);
1243 for (i = 0; i < (bd_count + 1) / 2 + 1; i++) {
1244 /* pass FD to controler */
1245 lp->rfd_cur->fd.FDNext = cpu_to_le32(0xdeaddead); /* for debug */
1246 lp->rfd_cur->fd.FDCtl = cpu_to_le32(FD_CownsFD);
1251 lp->rfd_cur = next_rfd;
1254 /* re-enable BL/FDA Exhaust interupts. */
1255 if (fd_free_count) {
1256 tc_writel(tc_readl(&tr->Int_En) | Int_FDAExEn, &tr->Int_En);
1258 tc_writel(tc_readl(&tr->Int_En) | Int_BLExEn, &tr->Int_En);
1262 #ifdef NO_CHECK_CARRIER
1263 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1265 #define TX_STA_ERR (Tx_ExColl|Tx_Under|Tx_Defer|Tx_NCarr|Tx_LateColl|Tx_TxPar|Tx_SQErr)
1269 tc35815_check_tx_stat(struct net_device *dev, int status)
1271 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1272 const char *msg = NULL;
1274 /* count collisions */
1275 if (status & Tx_ExColl)
1276 lp->stats.collisions += 16;
1277 if (status & Tx_TxColl_MASK)
1278 lp->stats.collisions += status & Tx_TxColl_MASK;
1280 /* WORKAROUND: ignore LostCrS in full duplex operation */
1282 status &= ~Tx_NCarr;
1284 if (!(status & TX_STA_ERR)) {
1286 lp->stats.tx_packets++;
1290 lp->stats.tx_errors++;
1291 if (status & Tx_ExColl) {
1292 lp->stats.tx_aborted_errors++;
1293 msg = "Excessive Collision.";
1295 if (status & Tx_Under) {
1296 lp->stats.tx_fifo_errors++;
1297 msg = "Tx FIFO Underrun.";
1299 if (status & Tx_Defer) {
1300 lp->stats.tx_fifo_errors++;
1301 msg = "Excessive Deferral.";
1303 #ifndef NO_CHECK_CARRIER
1304 if (status & Tx_NCarr) {
1305 lp->stats.tx_carrier_errors++;
1306 msg = "Lost Carrier Sense.";
1309 if (status & Tx_LateColl) {
1310 lp->stats.tx_aborted_errors++;
1311 msg = "Late Collision.";
1313 if (status & Tx_TxPar) {
1314 lp->stats.tx_fifo_errors++;
1315 msg = "Transmit Parity Error.";
1317 if (status & Tx_SQErr) {
1318 lp->stats.tx_heartbeat_errors++;
1319 msg = "Signal Quality Error.";
1322 printk(KERN_WARNING "%s: %s (%#x)\n", dev->name, msg, status);
1326 tc35815_txdone(struct net_device *dev)
1328 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1329 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1334 txfd = &lp->tfd_base[lp->tfd_end];
1335 while (lp->tfd_start != lp->tfd_end &&
1336 !((fdctl = le32_to_cpu(txfd->fd.FDCtl)) & FD_CownsFD)) {
1337 int status = le32_to_cpu(txfd->fd.FDStat);
1338 struct sk_buff *skb;
1339 unsigned long fdnext = le32_to_cpu(txfd->fd.FDNext);
1341 if (tc35815_debug > 2) {
1342 printk("%s: complete TxFD.\n", dev->name);
1345 tc35815_check_tx_stat(dev, status);
1347 skb = (struct sk_buff *)le32_to_cpu(txfd->fd.FDSystem);
1349 dev_kfree_skb_any(skb);
1351 txfd->fd.FDSystem = cpu_to_le32(0);
1354 lp->tfd_end = (lp->tfd_end + 1) % TX_FD_NUM;
1355 txfd = &lp->tfd_base[lp->tfd_end];
1356 if ((fdnext & ~FD_Next_EOL) != virt_to_bus(txfd)) {
1357 printk("%s: TxFD FDNext invalid.\n", dev->name);
1360 if (fdnext & FD_Next_EOL) {
1361 /* DMA Transmitter has been stopping... */
1362 if (lp->tfd_end != lp->tfd_start) {
1363 int head = (lp->tfd_start + TX_FD_NUM - 1) % TX_FD_NUM;
1364 struct TxFD* txhead = &lp->tfd_base[head];
1365 int qlen = (lp->tfd_start + TX_FD_NUM
1366 - lp->tfd_end) % TX_FD_NUM;
1368 if (!(le32_to_cpu(txfd->fd.FDCtl) & FD_CownsFD)) {
1369 printk("%s: TxFD FDCtl invalid.\n", dev->name);
1372 /* log max queue length */
1373 if (lp->lstats.max_tx_qlen < qlen)
1374 lp->lstats.max_tx_qlen = qlen;
1377 /* start DMA Transmitter again */
1378 txhead->fd.FDNext |= cpu_to_le32(FD_Next_EOL);
1380 txhead->fd.FDCtl |= cpu_to_le32(FD_FrmOpt_IntTx);
1382 if (tc35815_debug > 2) {
1383 printk("%s: start TxFD on queue.\n",
1387 tc_writel(virt_to_bus(txfd), &tr->TxFrmPtr);
1393 if (num_done > 0 && lp->tbusy) {
1395 netif_start_queue(dev);
1399 /* The inverse routine to tc35815_open(). */
1401 tc35815_close(struct net_device *dev)
1403 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1406 netif_stop_queue(dev);
1408 /* Flush the Tx and disable Rx here. */
1410 tc35815_chip_reset(dev);
1411 free_irq(dev->irq, dev);
1413 tc35815_free_queues(dev);
1421 * Get the current statistics.
1422 * This may be called with the card open or closed.
1424 static struct net_device_stats *tc35815_get_stats(struct net_device *dev)
1426 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1427 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1428 unsigned long flags;
1430 if (netif_running(dev)) {
1433 /* Update the statistics from the device registers. */
1434 lp->stats.rx_missed_errors = tc_readl(&tr->Miss_Cnt);
1435 restore_flags(flags);
1441 static void tc35815_set_cam_entry(struct tc35815_regs *tr, int index, unsigned char *addr)
1443 int cam_index = index * 6;
1444 unsigned long cam_data;
1445 unsigned long saved_addr;
1446 saved_addr = tc_readl(&tr->CAM_Adr);
1448 if (tc35815_debug > 1) {
1450 printk(KERN_DEBUG "%s: CAM %d:", cardname, index);
1451 for (i = 0; i < 6; i++)
1452 printk(" %02x", addr[i]);
1456 /* read modify write */
1457 tc_writel(cam_index - 2, &tr->CAM_Adr);
1458 cam_data = tc_readl(&tr->CAM_Data) & 0xffff0000;
1459 cam_data |= addr[0] << 8 | addr[1];
1460 tc_writel(cam_data, &tr->CAM_Data);
1461 /* write whole word */
1462 tc_writel(cam_index + 2, &tr->CAM_Adr);
1463 cam_data = (addr[2] << 24) | (addr[3] << 16) | (addr[4] << 8) | addr[5];
1464 tc_writel(cam_data, &tr->CAM_Data);
1466 /* write whole word */
1467 tc_writel(cam_index, &tr->CAM_Adr);
1468 cam_data = (addr[0] << 24) | (addr[1] << 16) | (addr[2] << 8) | addr[3];
1469 tc_writel(cam_data, &tr->CAM_Data);
1470 /* read modify write */
1471 tc_writel(cam_index + 4, &tr->CAM_Adr);
1472 cam_data = tc_readl(&tr->CAM_Data) & 0x0000ffff;
1473 cam_data |= addr[4] << 24 | (addr[5] << 16);
1474 tc_writel(cam_data, &tr->CAM_Data);
1477 if (tc35815_debug > 2) {
1479 for (i = cam_index / 4; i < cam_index / 4 + 2; i++) {
1480 tc_writel(i * 4, &tr->CAM_Adr);
1481 printk("CAM 0x%x: %08x",
1482 i * 4, tc_readl(&tr->CAM_Data));
1485 tc_writel(saved_addr, &tr->CAM_Adr);
1490 * Set or clear the multicast filter for this adaptor.
1491 * num_addrs == -1 Promiscuous mode, receive all packets
1492 * num_addrs == 0 Normal mode, clear multicast list
1493 * num_addrs > 0 Multicast mode, receive normal and MC packets,
1494 * and do best-effort filtering.
1497 tc35815_set_multicast_list(struct net_device *dev)
1499 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1501 if (dev->flags&IFF_PROMISC)
1503 /* Enable promiscuous mode */
1504 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc | CAM_StationAcc, &tr->CAM_Ctl);
1506 else if((dev->flags&IFF_ALLMULTI) || dev->mc_count > CAM_ENTRY_MAX - 3)
1508 /* CAM 0, 1, 20 are reserved. */
1509 /* Disable promiscuous mode, use normal mode. */
1510 tc_writel(CAM_CompEn | CAM_BroadAcc | CAM_GroupAcc, &tr->CAM_Ctl);
1512 else if(dev->mc_count)
1514 struct dev_mc_list* cur_addr = dev->mc_list;
1516 int ena_bits = CAM_Ena_Bit(CAM_ENTRY_SOURCE);
1518 tc_writel(0, &tr->CAM_Ctl);
1519 /* Walk the address list, and load the filter */
1520 for (i = 0; i < dev->mc_count; i++, cur_addr = cur_addr->next) {
1523 /* entry 0,1 is reserved. */
1524 tc35815_set_cam_entry(tr, i + 2, cur_addr->dmi_addr);
1525 ena_bits |= CAM_Ena_Bit(i + 2);
1527 tc_writel(ena_bits, &tr->CAM_Ena);
1528 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1531 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1532 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1536 static unsigned long tc_phy_read(struct tc35815_regs *tr, int phy, int phy_reg)
1542 tc_writel(MD_CA_Busy | (phy << 5) | phy_reg, &tr->MD_CA);
1543 while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
1545 data = tc_readl(&tr->MD_Data);
1546 restore_flags(flags);
1550 static void tc_phy_write(unsigned long d, struct tc35815_regs *tr, int phy, int phy_reg)
1555 tc_writel(d, &tr->MD_Data);
1556 tc_writel(MD_CA_Busy | MD_CA_Wr | (phy << 5) | phy_reg, &tr->MD_CA);
1557 while (tc_readl(&tr->MD_CA) & MD_CA_Busy)
1559 restore_flags(flags);
1562 static void tc35815_phy_chip_init(struct net_device *dev)
1564 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1565 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1566 static int first = 1;
1570 unsigned short id0, id1;
1574 /* first data written to the PHY will be an ID number */
1575 tc_phy_write(0, tr, 0, MII_CONTROL); /* ID:0 */
1577 tc_phy_write(MIICNTL_RESET, tr, 0, MII_CONTROL);
1578 printk(KERN_INFO "%s: Resetting PHY...", dev->name);
1579 while (tc_phy_read(tr, 0, MII_CONTROL) & MIICNTL_RESET)
1582 tc_phy_write(MIICNTL_AUTO|MIICNTL_SPEED|MIICNTL_FDX, tr, 0,
1585 id0 = tc_phy_read(tr, 0, MII_PHY_ID0);
1586 id1 = tc_phy_read(tr, 0, MII_PHY_ID1);
1587 printk(KERN_DEBUG "%s: PHY ID %04x %04x\n", dev->name,
1589 if (lp->option & TC35815_OPT_10M) {
1591 lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
1592 } else if (lp->option & TC35815_OPT_100M) {
1593 lp->linkspeed = 100;
1594 lp->fullduplex = (lp->option & TC35815_OPT_FULLDUP) != 0;
1596 /* auto negotiation */
1597 unsigned long neg_result;
1598 tc_phy_write(MIICNTL_AUTO | MIICNTL_RST_AUTO, tr, 0, MII_CONTROL);
1599 printk(KERN_INFO "%s: Auto Negotiation...", dev->name);
1601 while (!(tc_phy_read(tr, 0, MII_STATUS) & MIISTAT_AUTO_DONE)) {
1602 if (count++ > 5000) {
1603 printk(" failed. Assume 10Mbps\n");
1608 if (count % 512 == 0)
1613 neg_result = tc_phy_read(tr, 0, MII_ANLPAR);
1614 if (neg_result & (MII_AN_TX_FDX | MII_AN_TX_HDX))
1615 lp->linkspeed = 100;
1618 if (neg_result & (MII_AN_TX_FDX | MII_AN_10_FDX))
1628 if (lp->linkspeed == 100)
1629 ctl |= MIICNTL_SPEED;
1632 tc_phy_write(ctl, tr, 0, MII_CONTROL);
1634 if (lp->fullduplex) {
1635 tc_writel(tc_readl(&tr->MAC_Ctl) | MAC_FullDup, &tr->MAC_Ctl);
1639 static void tc35815_chip_reset(struct net_device *dev)
1641 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1643 /* reset the controller */
1644 tc_writel(MAC_Reset, &tr->MAC_Ctl);
1645 while (tc_readl(&tr->MAC_Ctl) & MAC_Reset)
1648 tc_writel(0, &tr->MAC_Ctl);
1650 /* initialize registers to default value */
1651 tc_writel(0, &tr->DMA_Ctl);
1652 tc_writel(0, &tr->TxThrsh);
1653 tc_writel(0, &tr->TxPollCtr);
1654 tc_writel(0, &tr->RxFragSize);
1655 tc_writel(0, &tr->Int_En);
1656 tc_writel(0, &tr->FDA_Bas);
1657 tc_writel(0, &tr->FDA_Lim);
1658 tc_writel(0xffffffff, &tr->Int_Src); /* Write 1 to clear */
1659 tc_writel(0, &tr->CAM_Ctl);
1660 tc_writel(0, &tr->Tx_Ctl);
1661 tc_writel(0, &tr->Rx_Ctl);
1662 tc_writel(0, &tr->CAM_Ena);
1663 (void)tc_readl(&tr->Miss_Cnt); /* Read to clear */
1667 static void tc35815_chip_init(struct net_device *dev)
1669 struct tc35815_local *lp = (struct tc35815_local *)dev->priv;
1670 struct tc35815_regs *tr = (struct tc35815_regs*)dev->base_addr;
1672 unsigned long txctl = TX_CTL_CMD;
1674 tc35815_phy_chip_init(dev);
1676 /* load station address to CAM */
1677 tc35815_set_cam_entry(tr, CAM_ENTRY_SOURCE, dev->dev_addr);
1679 /* Enable CAM (broadcast and unicast) */
1680 tc_writel(CAM_Ena_Bit(CAM_ENTRY_SOURCE), &tr->CAM_Ena);
1681 tc_writel(CAM_CompEn | CAM_BroadAcc, &tr->CAM_Ctl);
1686 tc_writel(DMA_BURST_SIZE, &tr->DMA_Ctl);
1688 tc_writel(RxFrag_EnPack | ETH_ZLEN, &tr->RxFragSize); /* Packing */
1689 tc_writel(0, &tr->TxPollCtr); /* Batch mode */
1690 tc_writel(TX_THRESHOLD, &tr->TxThrsh);
1691 tc_writel(INT_EN_CMD, &tr->Int_En);
1694 tc_writel(virt_to_bus(lp->rfd_base), &tr->FDA_Bas);
1695 tc_writel((unsigned long)lp->rfd_limit - (unsigned long)lp->rfd_base,
1698 * Activation method:
1699 * First, enable eht MAC Transmitter and the DMA Receive circuits.
1700 * Then enable the DMA Transmitter and the MAC Receive circuits.
1702 tc_writel(virt_to_bus(lp->fbl_ptr), &tr->BLFrmPtr); /* start DMA receiver */
1703 tc_writel(RX_CTL_CMD, &tr->Rx_Ctl); /* start MAC receiver */
1704 /* start MAC transmitter */
1705 /* WORKAROUND: ignore LostCrS in full duplex operation */
1707 txctl = TX_CTL_CMD & ~Tx_EnLCarr;
1709 txctl &= ~Tx_EnComp; /* disable global tx completion int. */
1711 tc_writel(txctl, &tr->Tx_Ctl);
1712 #if 0 /* No need to polling */
1713 tc_writel(virt_to_bus(lp->tfd_base), &tr->TxFrmPtr); /* start DMA transmitter */
1715 restore_flags(flags);
1721 tc35815_killall(void)
1723 struct net_device *dev;
1725 for (dev = root_tc35815_dev; dev; dev = ((struct tc35815_local *)dev->priv)->next_module) {
1726 if (dev->flags&IFF_UP){
1732 static struct pci_driver tc35815_driver = {
1733 name: TC35815_MODULE_NAME,
1734 probe: tc35815_probe,
1736 id_table: tc35815_pci_tbl,
1739 static int __init tc35815_init_module(void)
1743 if ((err = pci_module_init(&tc35815_driver)) < 0 )
1749 static void __exit tc35815_cleanup_module(void)
1751 struct net_device *next_dev;
1753 /* No need to check MOD_IN_USE, as sys_delete_module() checks. */
1754 while (root_tc35815_dev) {
1755 struct net_device *dev = root_tc35815_dev;
1756 next_dev = ((struct tc35815_local *)dev->priv)->next_module;
1758 iounmap((void *)(dev->base_addr));
1759 unregister_netdev(dev);
1761 root_tc35815_dev = next_dev;
1764 module_init(tc35815_init_module);
1765 module_exit(tc35815_cleanup_module);