2 * $Id: proc.c,v 1.1.1.1 2005/04/11 02:50:33 jack Exp $
4 * Procfs interface for the PCI bus.
6 * Copyright (c) 1997--1999 Martin Mares <mj@ucw.cz>
9 #include <linux/types.h>
10 #include <linux/kernel.h>
11 #include <linux/pci.h>
12 #include <linux/proc_fs.h>
13 #include <linux/init.h>
14 #include <linux/seq_file.h>
16 #include <asm/uaccess.h>
17 #include <asm/byteorder.h>
19 #define PCI_CFG_SPACE_SIZE 256
22 proc_bus_pci_lseek(struct file *file, loff_t off, int whence)
31 new = file->f_pos + off;
34 new = PCI_CFG_SPACE_SIZE + off;
39 if (new < 0 || new > PCI_CFG_SPACE_SIZE)
41 return (file->f_pos = new);
45 proc_bus_pci_read(struct file *file, char *buf, size_t nbytes, loff_t *ppos)
47 const struct inode *ino = file->f_dentry->d_inode;
48 const struct proc_dir_entry *dp = ino->u.generic_ip;
49 struct pci_dev *dev = dp->data;
50 unsigned int pos = *ppos;
51 unsigned int cnt, size;
54 * Normal users can read only the standardized portion of the
55 * configuration space as several chips lock up when trying to read
56 * undefined locations (think of Intel PIIX4 as a typical example).
59 if (capable(CAP_SYS_ADMIN))
60 size = PCI_CFG_SPACE_SIZE;
61 else if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
70 if (pos + nbytes > size)
74 if (!access_ok(VERIFY_WRITE, buf, cnt))
77 if ((pos & 1) && cnt) {
79 pci_read_config_byte(dev, pos, &val);
86 if ((pos & 3) && cnt > 2) {
88 pci_read_config_word(dev, pos, &val);
89 __put_user(cpu_to_le16(val), (unsigned short *) buf);
97 pci_read_config_dword(dev, pos, &val);
98 __put_user(cpu_to_le32(val), (unsigned int *) buf);
106 pci_read_config_word(dev, pos, &val);
107 __put_user(cpu_to_le16(val), (unsigned short *) buf);
115 pci_read_config_byte(dev, pos, &val);
116 __put_user(val, buf);
127 proc_bus_pci_write(struct file *file, const char *buf, size_t nbytes, loff_t *ppos)
129 const struct inode *ino = file->f_dentry->d_inode;
130 const struct proc_dir_entry *dp = ino->u.generic_ip;
131 struct pci_dev *dev = dp->data;
135 if (pos >= PCI_CFG_SPACE_SIZE)
137 if (nbytes >= PCI_CFG_SPACE_SIZE)
138 nbytes = PCI_CFG_SPACE_SIZE;
139 if (pos + nbytes > PCI_CFG_SPACE_SIZE)
140 nbytes = PCI_CFG_SPACE_SIZE - pos;
143 if (!access_ok(VERIFY_READ, buf, cnt))
146 if ((pos & 1) && cnt) {
148 __get_user(val, buf);
149 pci_write_config_byte(dev, pos, val);
155 if ((pos & 3) && cnt > 2) {
157 __get_user(val, (unsigned short *) buf);
158 pci_write_config_word(dev, pos, le16_to_cpu(val));
166 __get_user(val, (unsigned int *) buf);
167 pci_write_config_dword(dev, pos, le32_to_cpu(val));
175 __get_user(val, (unsigned short *) buf);
176 pci_write_config_word(dev, pos, le16_to_cpu(val));
184 __get_user(val, buf);
185 pci_write_config_byte(dev, pos, val);
195 struct pci_filp_private {
196 enum pci_mmap_state mmap_state;
200 static int proc_bus_pci_ioctl(struct inode *inode, struct file *file, unsigned int cmd, unsigned long arg)
202 const struct proc_dir_entry *dp = inode->u.generic_ip;
203 struct pci_dev *dev = dp->data;
205 struct pci_filp_private *fpriv = file->private_data;
206 #endif /* HAVE_PCI_MMAP */
210 case PCIIOC_CONTROLLER:
211 ret = pci_controller_num(dev);
215 case PCIIOC_MMAP_IS_IO:
216 fpriv->mmap_state = pci_mmap_io;
219 case PCIIOC_MMAP_IS_MEM:
220 fpriv->mmap_state = pci_mmap_mem;
223 case PCIIOC_WRITE_COMBINE:
225 fpriv->write_combine = 1;
227 fpriv->write_combine = 0;
230 #endif /* HAVE_PCI_MMAP */
241 static int proc_bus_pci_mmap(struct file *file, struct vm_area_struct *vma)
243 struct inode *inode = file->f_dentry->d_inode;
244 const struct proc_dir_entry *dp = inode->u.generic_ip;
245 struct pci_dev *dev = dp->data;
246 struct pci_filp_private *fpriv = file->private_data;
249 if (!capable(CAP_SYS_RAWIO))
252 ret = pci_mmap_page_range(dev, vma,
254 fpriv->write_combine);
261 static int proc_bus_pci_open(struct inode *inode, struct file *file)
263 struct pci_filp_private *fpriv = kmalloc(sizeof(*fpriv), GFP_KERNEL);
268 fpriv->mmap_state = pci_mmap_io;
269 fpriv->write_combine = 0;
271 file->private_data = fpriv;
276 static int proc_bus_pci_release(struct inode *inode, struct file *file)
278 kfree(file->private_data);
279 file->private_data = NULL;
283 #endif /* HAVE_PCI_MMAP */
285 static struct file_operations proc_bus_pci_operations = {
286 llseek: proc_bus_pci_lseek,
287 read: proc_bus_pci_read,
288 write: proc_bus_pci_write,
289 ioctl: proc_bus_pci_ioctl,
291 open: proc_bus_pci_open,
292 release: proc_bus_pci_release,
293 mmap: proc_bus_pci_mmap,
294 #ifdef HAVE_ARCH_PCI_GET_UNMAPPED_AREA
295 get_unmapped_area: get_pci_unmapped_area,
296 #endif /* HAVE_ARCH_PCI_GET_UNMAPPED_AREA */
297 #endif /* HAVE_PCI_MMAP */
300 #if BITS_PER_LONG == 32
301 #define LONG_FORMAT "\t%08lx"
303 #define LONG_FORMAT "\t%16lx"
307 static void *pci_seq_start(struct seq_file *m, loff_t *pos)
309 struct list_head *p = &pci_devices;
312 /* XXX: surely we need some locking for traversing the list? */
315 if (p == &pci_devices)
320 static void *pci_seq_next(struct seq_file *m, void *v, loff_t *pos)
322 struct list_head *p = v;
324 return p->next != &pci_devices ? p->next : NULL;
326 static void pci_seq_stop(struct seq_file *m, void *v)
328 /* release whatever locks we need */
331 static int show_device(struct seq_file *m, void *v)
333 struct list_head *p = v;
334 const struct pci_dev *dev;
335 const struct pci_driver *drv;
338 if (p == &pci_devices)
342 drv = pci_dev_driver(dev);
343 seq_printf(m, "%02x%02x\t%04x%04x\t%x",
349 /* Here should be 7 and not PCI_NUM_RESOURCES as we need to preserve compatibility */
351 seq_printf(m, LONG_FORMAT,
352 dev->resource[i].start |
353 (dev->resource[i].flags & PCI_REGION_FLAG_MASK));
355 seq_printf(m, LONG_FORMAT,
356 dev->resource[i].start < dev->resource[i].end ?
357 dev->resource[i].end - dev->resource[i].start + 1 : 0);
360 seq_printf(m, "%s", drv->name);
365 static struct seq_operations proc_bus_pci_devices_op = {
366 start: pci_seq_start,
372 struct proc_dir_entry *proc_bus_pci_dir;
374 int pci_proc_attach_device(struct pci_dev *dev)
376 struct pci_bus *bus = dev->bus;
377 struct proc_dir_entry *de, *e;
380 if (!(de = bus->procdir)) {
381 sprintf(name, "%02x", bus->number);
382 de = bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
386 sprintf(name, "%02x.%x", PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
387 e = dev->procent = create_proc_entry(name, S_IFREG | S_IRUGO | S_IWUSR, de);
390 e->proc_fops = &proc_bus_pci_operations;
392 e->size = PCI_CFG_SPACE_SIZE;
396 int pci_proc_detach_device(struct pci_dev *dev)
398 struct proc_dir_entry *e;
400 if ((e = dev->procent)) {
401 if (atomic_read(&e->count))
403 remove_proc_entry(e->name, dev->bus->procdir);
409 int pci_proc_attach_bus(struct pci_bus* bus)
411 struct proc_dir_entry *de = bus->procdir;
415 sprintf(name, "%02x", bus->number);
416 de = bus->procdir = proc_mkdir(name, proc_bus_pci_dir);
423 int pci_proc_detach_bus(struct pci_bus* bus)
425 struct proc_dir_entry *de = bus->procdir;
427 remove_proc_entry(de->name, proc_bus_pci_dir);
433 * Backward compatible /proc/pci interface.
437 * Convert some of the configuration space registers of the device at
438 * address (bus,devfn) into a string (possibly several lines each).
439 * The configuration string is stored starting at buf[len]. If the
440 * string would exceed the size of the buffer (SIZE), 0 is returned.
442 static int show_dev_config(struct seq_file *m, void *v)
444 struct list_head *p = v;
446 struct pci_driver *drv;
448 unsigned char latency, min_gnt, max_lat, *class;
451 if (p == &pci_devices) {
452 seq_puts(m, "PCI devices found:\n");
457 drv = pci_dev_driver(dev);
459 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class_rev);
460 pci_read_config_byte (dev, PCI_LATENCY_TIMER, &latency);
461 pci_read_config_byte (dev, PCI_MIN_GNT, &min_gnt);
462 pci_read_config_byte (dev, PCI_MAX_LAT, &max_lat);
463 seq_printf(m, " Bus %2d, device %3d, function %2d:\n",
464 dev->bus->number, PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn));
465 class = pci_class_name(class_rev >> 16);
467 seq_printf(m, " %s", class);
469 seq_printf(m, " Class %04x", class_rev >> 16);
470 seq_printf(m, ": %s (rev %d).\n", dev->name, class_rev & 0xff);
472 //if (dev->irq) //+Bing modified 01122005
473 seq_printf(m, " IRQ %d.\n", dev->irq);
475 if (latency || min_gnt || max_lat) {
476 seq_printf(m, " Master Capable. ");
478 seq_printf(m, "Latency=%d. ", latency);
480 seq_puts(m, "No bursts. ");
482 seq_printf(m, "Min Gnt=%d.", min_gnt);
484 seq_printf(m, "Max Lat=%d.", max_lat);
488 for (reg = 0; reg < 6; reg++) {
489 struct resource *res = dev->resource + reg;
490 unsigned long base, end, flags;
498 if (flags & PCI_BASE_ADDRESS_SPACE_IO) {
499 seq_printf(m, " I/O at 0x%lx [0x%lx].\n",
502 const char *pref, *type = "unknown";
504 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
508 switch (flags & PCI_BASE_ADDRESS_MEM_TYPE_MASK) {
509 case PCI_BASE_ADDRESS_MEM_TYPE_32:
510 type = "32 bit"; break;
511 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
512 type = "20 bit"; break;
513 case PCI_BASE_ADDRESS_MEM_TYPE_64:
514 type = "64 bit"; break;
516 seq_printf(m, " %srefetchable %s memory at "
517 "0x%lx [0x%lx].\n", pref, type,
525 static struct seq_operations proc_pci_op = {
526 start: pci_seq_start,
529 show: show_dev_config
532 static int proc_bus_pci_dev_open(struct inode *inode, struct file *file)
534 return seq_open(file, &proc_bus_pci_devices_op);
536 static struct file_operations proc_bus_pci_dev_operations = {
537 open: proc_bus_pci_dev_open,
540 release: seq_release,
542 static int proc_pci_open(struct inode *inode, struct file *file)
544 return seq_open(file, &proc_pci_op);
546 static struct file_operations proc_pci_operations = {
550 release: seq_release,
553 static int __init pci_proc_init(void)
556 struct proc_dir_entry *entry;
558 proc_bus_pci_dir = proc_mkdir("pci", proc_bus);
559 entry = create_proc_entry("devices", 0, proc_bus_pci_dir);
561 entry->proc_fops = &proc_bus_pci_dev_operations;
562 pci_for_each_dev(dev) {
563 pci_proc_attach_device(dev);
565 entry = create_proc_entry("pci", 0, NULL);
567 entry->proc_fops = &proc_pci_operations;
572 __initcall(pci_proc_init);