2 * Regular lowlevel cardbus driver ("yenta")
4 * (C) Copyright 1999, 2000 Linus Torvalds
7 * Aug 2002: Manfred Spraul <manfred@colorfullife.com>
8 * Dynamically adjust the size of the bridge resource
11 #include <linux/init.h>
12 #include <linux/pci.h>
13 #include <linux/sched.h>
14 #include <linux/interrupt.h>
15 #include <linux/delay.h>
16 #include <linux/module.h>
18 #include <pcmcia/version.h>
19 #include <pcmcia/cs_types.h>
20 #include <pcmcia/ss.h>
21 #include <pcmcia/cs.h>
29 #define DEBUG(x,args...) printk(__FUNCTION__ ": " x,##args)
31 #define DEBUG(x,args...)
35 #define to_cycles(ns) ((ns)/120)
36 #define to_ns(cycles) ((cycles)*120)
39 * Generate easy-to-use ways of reading a cardbus sockets
40 * regular memory space ("cb_xxx"), configuration space
41 * ("config_xxx") and compatibility space ("exca_xxxx")
43 static inline u32 cb_readl(pci_socket_t *socket, unsigned reg)
45 u32 val = readl(socket->base + reg);
46 DEBUG("%p %04x %08x\n", socket, reg, val);
50 static inline void cb_writel(pci_socket_t *socket, unsigned reg, u32 val)
52 DEBUG("%p %04x %08x\n", socket, reg, val);
53 writel(val, socket->base + reg);
56 static inline u8 config_readb(pci_socket_t *socket, unsigned offset)
59 pci_read_config_byte(socket->dev, offset, &val);
60 DEBUG("%p %04x %02x\n", socket, offset, val);
64 static inline u16 config_readw(pci_socket_t *socket, unsigned offset)
67 pci_read_config_word(socket->dev, offset, &val);
68 DEBUG("%p %04x %04x\n", socket, offset, val);
72 static inline u32 config_readl(pci_socket_t *socket, unsigned offset)
75 pci_read_config_dword(socket->dev, offset, &val);
76 DEBUG("%p %04x %08x\n", socket, offset, val);
80 static inline void config_writeb(pci_socket_t *socket, unsigned offset, u8 val)
82 DEBUG("%p %04x %02x\n", socket, offset, val);
83 pci_write_config_byte(socket->dev, offset, val);
86 static inline void config_writew(pci_socket_t *socket, unsigned offset, u16 val)
88 DEBUG("%p %04x %04x\n", socket, offset, val);
89 pci_write_config_word(socket->dev, offset, val);
92 static inline void config_writel(pci_socket_t *socket, unsigned offset, u32 val)
94 DEBUG("%p %04x %08x\n", socket, offset, val);
95 pci_write_config_dword(socket->dev, offset, val);
98 static inline u8 exca_readb(pci_socket_t *socket, unsigned reg)
100 u8 val = readb(socket->base + 0x800 + reg);
101 DEBUG("%p %04x %02x\n", socket, reg, val);
105 static inline u8 exca_readw(pci_socket_t *socket, unsigned reg)
108 val = readb(socket->base + 0x800 + reg);
109 val |= readb(socket->base + 0x800 + reg + 1) << 8;
110 DEBUG("%p %04x %04x\n", socket, reg, val);
114 static inline void exca_writeb(pci_socket_t *socket, unsigned reg, u8 val)
116 DEBUG("%p %04x %02x\n", socket, reg, val);
117 writeb(val, socket->base + 0x800 + reg);
120 static void exca_writew(pci_socket_t *socket, unsigned reg, u16 val)
122 DEBUG("%p %04x %04x\n", socket, reg, val);
123 writeb(val, socket->base + 0x800 + reg);
124 writeb(val >> 8, socket->base + 0x800 + reg + 1);
128 * Ugh, mixed-mode cardbus and 16-bit pccard state: things depend
129 * on what kind of card is inserted..
131 static int yenta_get_status(pci_socket_t *socket, unsigned int *value)
134 u32 state = cb_readl(socket, CB_SOCKET_STATE);
136 val = (state & CB_3VCARD) ? SS_3VCARD : 0;
137 val |= (state & CB_XVCARD) ? SS_XVCARD : 0;
138 val |= (state & (CB_CDETECT1 | CB_CDETECT2 | CB_5VCARD | CB_3VCARD
139 | CB_XVCARD | CB_YVCARD)) ? 0 : SS_PENDING;
141 if (state & CB_CBCARD) {
143 val |= (state & CB_CARDSTS) ? SS_STSCHG : 0;
144 val |= (state & (CB_CDETECT1 | CB_CDETECT2)) ? 0 : SS_DETECT;
145 val |= (state & CB_PWRCYCLE) ? SS_POWERON | SS_READY : 0;
147 u8 status = exca_readb(socket, I365_STATUS);
148 val |= ((status & I365_CS_DETECT) == I365_CS_DETECT) ? SS_DETECT : 0;
149 if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
150 val |= (status & I365_CS_STSCHG) ? 0 : SS_STSCHG;
152 val |= (status & I365_CS_BVD1) ? 0 : SS_BATDEAD;
153 val |= (status & I365_CS_BVD2) ? 0 : SS_BATWARN;
155 val |= (status & I365_CS_WRPROT) ? SS_WRPROT : 0;
156 val |= (status & I365_CS_READY) ? SS_READY : 0;
157 val |= (status & I365_CS_POWERON) ? SS_POWERON : 0;
164 static int yenta_Vcc_power(u32 control)
166 switch (control & CB_SC_VCC_MASK) {
167 case CB_SC_VCC_5V: return 50;
168 case CB_SC_VCC_3V: return 33;
173 static int yenta_Vpp_power(u32 control)
175 switch (control & CB_SC_VPP_MASK) {
176 case CB_SC_VPP_12V: return 120;
177 case CB_SC_VPP_5V: return 50;
178 case CB_SC_VPP_3V: return 33;
183 static int yenta_get_socket(pci_socket_t *socket, socket_state_t *state)
188 control = cb_readl(socket, CB_SOCKET_CONTROL);
190 state->Vcc = yenta_Vcc_power(control);
191 state->Vpp = yenta_Vpp_power(control);
192 state->io_irq = socket->io_irq;
194 if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
195 u16 bridge = config_readw(socket, CB_BRIDGE_CONTROL);
196 if (bridge & CB_BRIDGE_CRST)
197 state->flags |= SS_RESET;
201 /* 16-bit card state.. */
202 reg = exca_readb(socket, I365_POWER);
203 state->flags = (reg & I365_PWR_AUTO) ? SS_PWR_AUTO : 0;
204 state->flags |= (reg & I365_PWR_OUT) ? SS_OUTPUT_ENA : 0;
206 reg = exca_readb(socket, I365_INTCTL);
207 state->flags |= (reg & I365_PC_RESET) ? 0 : SS_RESET;
208 state->flags |= (reg & I365_PC_IOCARD) ? SS_IOCARD : 0;
210 reg = exca_readb(socket, I365_CSCINT);
211 state->csc_mask = (reg & I365_CSC_DETECT) ? SS_DETECT : 0;
212 if (state->flags & SS_IOCARD) {
213 state->csc_mask |= (reg & I365_CSC_STSCHG) ? SS_STSCHG : 0;
215 state->csc_mask |= (reg & I365_CSC_BVD1) ? SS_BATDEAD : 0;
216 state->csc_mask |= (reg & I365_CSC_BVD2) ? SS_BATWARN : 0;
217 state->csc_mask |= (reg & I365_CSC_READY) ? SS_READY : 0;
223 static void yenta_set_power(pci_socket_t *socket, socket_state_t *state)
225 u32 reg = 0; /* CB_SC_STPCLK? */
226 switch (state->Vcc) {
227 case 33: reg = CB_SC_VCC_3V; break;
228 case 50: reg = CB_SC_VCC_5V; break;
229 default: reg = 0; break;
231 switch (state->Vpp) {
232 case 33: reg |= CB_SC_VPP_3V; break;
233 case 50: reg |= CB_SC_VPP_5V; break;
234 case 120: reg |= CB_SC_VPP_12V; break;
236 if (reg != cb_readl(socket, CB_SOCKET_CONTROL))
237 cb_writel(socket, CB_SOCKET_CONTROL, reg);
240 static int yenta_set_socket(pci_socket_t *socket, socket_state_t *state)
244 if (state->flags & SS_DEBOUNCED) {
245 /* The insertion debounce period has ended. Clear any pending insertion events */
246 socket->events &= ~SS_DETECT;
247 state->flags &= ~SS_DEBOUNCED; /* SS_DEBOUNCED is oneshot */
249 yenta_set_power(socket, state);
250 socket->io_irq = state->io_irq;
251 bridge = config_readw(socket, CB_BRIDGE_CONTROL) & ~(CB_BRIDGE_CRST | CB_BRIDGE_INTR);
252 if (cb_readl(socket, CB_SOCKET_STATE) & CB_CBCARD) {
254 bridge |= (state->flags & SS_RESET) ? CB_BRIDGE_CRST : 0;
256 /* ISA interrupt control? */
257 intr = exca_readb(socket, I365_INTCTL);
258 intr = (intr & ~0xf);
259 if (!socket->cb_irq) {
260 intr |= state->io_irq;
261 bridge |= CB_BRIDGE_INTR;
263 exca_writeb(socket, I365_INTCTL, intr);
267 reg = exca_readb(socket, I365_INTCTL) & (I365_RING_ENA | I365_INTR_ENA);
268 reg |= (state->flags & SS_RESET) ? 0 : I365_PC_RESET;
269 reg |= (state->flags & SS_IOCARD) ? I365_PC_IOCARD : 0;
270 if (state->io_irq != socket->cb_irq) {
271 reg |= state->io_irq;
272 bridge |= CB_BRIDGE_INTR;
274 exca_writeb(socket, I365_INTCTL, reg);
276 reg = exca_readb(socket, I365_POWER) & (I365_VCC_MASK|I365_VPP1_MASK);
277 reg |= I365_PWR_NORESET;
278 if (state->flags & SS_PWR_AUTO) reg |= I365_PWR_AUTO;
279 if (state->flags & SS_OUTPUT_ENA) reg |= I365_PWR_OUT;
280 if (exca_readb(socket, I365_POWER) != reg)
281 exca_writeb(socket, I365_POWER, reg);
283 /* CSC interrupt: no ISA irq for CSC */
284 reg = I365_CSC_DETECT;
285 if (state->flags & SS_IOCARD) {
286 if (state->csc_mask & SS_STSCHG) reg |= I365_CSC_STSCHG;
288 if (state->csc_mask & SS_BATDEAD) reg |= I365_CSC_BVD1;
289 if (state->csc_mask & SS_BATWARN) reg |= I365_CSC_BVD2;
290 if (state->csc_mask & SS_READY) reg |= I365_CSC_READY;
292 exca_writeb(socket, I365_CSCINT, reg);
293 exca_readb(socket, I365_CSC);
295 if(socket->zoom_video)
296 socket->zoom_video(socket, state->flags & SS_ZVCARD);
298 config_writew(socket, CB_BRIDGE_CONTROL, bridge);
299 /* Socket event mask: get card insert/remove events.. */
300 cb_writel(socket, CB_SOCKET_EVENT, -1);
301 cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
305 static int yenta_get_io_map(pci_socket_t *socket, struct pccard_io_map *io)
308 unsigned char ioctl, addr;
314 io->start = exca_readw(socket, I365_IO(map)+I365_W_START);
315 io->stop = exca_readw(socket, I365_IO(map)+I365_W_STOP);
317 ioctl = exca_readb(socket, I365_IOCTL);
318 addr = exca_readb(socket, I365_ADDRWIN);
319 io->speed = to_ns(ioctl & I365_IOCTL_WAIT(map)) ? 1 : 0;
320 io->flags = (addr & I365_ENA_IO(map)) ? MAP_ACTIVE : 0;
321 io->flags |= (ioctl & I365_IOCTL_0WS(map)) ? MAP_0WS : 0;
322 io->flags |= (ioctl & I365_IOCTL_16BIT(map)) ? MAP_16BIT : 0;
323 io->flags |= (ioctl & I365_IOCTL_IOCS16(map)) ? MAP_AUTOSZ : 0;
328 static int yenta_set_io_map(pci_socket_t *socket, struct pccard_io_map *io)
331 unsigned char ioctl, addr, enable;
338 enable = I365_ENA_IO(map);
339 addr = exca_readb(socket, I365_ADDRWIN);
341 /* Disable the window before changing it.. */
344 exca_writeb(socket, I365_ADDRWIN, addr);
347 exca_writew(socket, I365_IO(map)+I365_W_START, io->start);
348 exca_writew(socket, I365_IO(map)+I365_W_STOP, io->stop);
350 ioctl = exca_readb(socket, I365_IOCTL) & ~I365_IOCTL_MASK(map);
351 if (io->flags & MAP_0WS) ioctl |= I365_IOCTL_0WS(map);
352 if (io->flags & MAP_16BIT) ioctl |= I365_IOCTL_16BIT(map);
353 if (io->flags & MAP_AUTOSZ) ioctl |= I365_IOCTL_IOCS16(map);
354 exca_writeb(socket, I365_IOCTL, ioctl);
356 if (io->flags & MAP_ACTIVE)
357 exca_writeb(socket, I365_ADDRWIN, addr | enable);
361 static int yenta_get_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem)
365 unsigned int start, stop, page, offset;
371 addr = exca_readb(socket, I365_ADDRWIN);
372 mem->flags = (addr & I365_ENA_MEM(map)) ? MAP_ACTIVE : 0;
374 start = exca_readw(socket, I365_MEM(map) + I365_W_START);
375 mem->flags |= (start & I365_MEM_16BIT) ? MAP_16BIT : 0;
376 mem->flags |= (start & I365_MEM_0WS) ? MAP_0WS : 0;
377 start = (start & 0x0fff) << 12;
379 stop = exca_readw(socket, I365_MEM(map) + I365_W_STOP);
380 mem->speed = to_ns(stop >> 14);
381 stop = ((stop & 0x0fff) << 12) + 0x0fff;
383 offset = exca_readw(socket, I365_MEM(map) + I365_W_OFF);
384 mem->flags |= (offset & I365_MEM_WRPROT) ? MAP_WRPROT : 0;
385 mem->flags |= (offset & I365_MEM_REG) ? MAP_ATTRIB : 0;
386 offset = ((offset & 0x3fff) << 12) + start;
387 mem->card_start = offset & 0x3ffffff;
389 page = exca_readb(socket, CB_MEM_PAGE(map)) << 24;
390 mem->sys_start = start + page;
391 mem->sys_stop = start + page;
396 static int yenta_set_mem_map(pci_socket_t *socket, struct pccard_mem_map *mem)
399 unsigned char addr, enable;
400 unsigned int start, stop, card_start;
404 start = mem->sys_start;
405 stop = mem->sys_stop;
406 card_start = mem->card_start;
408 if (map > 4 || start > stop || ((start ^ stop) >> 24) ||
409 (card_start >> 26) || mem->speed > 1000)
412 enable = I365_ENA_MEM(map);
413 addr = exca_readb(socket, I365_ADDRWIN);
416 exca_writeb(socket, I365_ADDRWIN, addr);
419 exca_writeb(socket, CB_MEM_PAGE(map), start >> 24);
421 word = (start >> 12) & 0x0fff;
422 if (mem->flags & MAP_16BIT)
423 word |= I365_MEM_16BIT;
424 if (mem->flags & MAP_0WS)
425 word |= I365_MEM_0WS;
426 exca_writew(socket, I365_MEM(map) + I365_W_START, word);
428 word = (stop >> 12) & 0x0fff;
429 switch (to_cycles(mem->speed)) {
431 case 1: word |= I365_MEM_WS0; break;
432 case 2: word |= I365_MEM_WS1; break;
433 default: word |= I365_MEM_WS1 | I365_MEM_WS0; break;
435 exca_writew(socket, I365_MEM(map) + I365_W_STOP, word);
437 word = ((card_start - start) >> 12) & 0x3fff;
438 if (mem->flags & MAP_WRPROT)
439 word |= I365_MEM_WRPROT;
440 if (mem->flags & MAP_ATTRIB)
441 word |= I365_MEM_REG;
442 exca_writew(socket, I365_MEM(map) + I365_W_OFF, word);
444 if (mem->flags & MAP_ACTIVE)
445 exca_writeb(socket, I365_ADDRWIN, addr | enable);
449 static void yenta_proc_setup(pci_socket_t *socket, struct proc_dir_entry *base)
454 static unsigned int yenta_events(pci_socket_t *socket)
460 /* Clear interrupt status for the event */
461 cb_event = cb_readl(socket, CB_SOCKET_EVENT);
462 cb_writel(socket, CB_SOCKET_EVENT, cb_event);
464 csc = exca_readb(socket, I365_CSC);
466 events = (cb_event & (CB_CD1EVENT | CB_CD2EVENT)) ? SS_DETECT : 0 ;
467 events |= (csc & I365_CSC_DETECT) ? SS_DETECT : 0;
468 if (exca_readb(socket, I365_INTCTL) & I365_PC_IOCARD) {
469 events |= (csc & I365_CSC_STSCHG) ? SS_STSCHG : 0;
471 events |= (csc & I365_CSC_BVD1) ? SS_BATDEAD : 0;
472 events |= (csc & I365_CSC_BVD2) ? SS_BATWARN : 0;
473 events |= (csc & I365_CSC_READY) ? SS_READY : 0;
479 static void yenta_bh(void *data)
481 pci_socket_t *socket = data;
484 spin_lock_irq(&socket->event_lock);
485 events = socket->events;
487 spin_unlock_irq(&socket->event_lock);
489 socket->handler(socket->info, events);
492 static void yenta_interrupt(int irq, void *dev_id, struct pt_regs *regs)
495 pci_socket_t *socket = (pci_socket_t *) dev_id;
497 events = yenta_events(socket);
499 spin_lock(&socket->event_lock);
500 socket->events |= events;
501 spin_unlock(&socket->event_lock);
502 schedule_task(&socket->tq_task);
506 static void yenta_interrupt_wrapper(unsigned long data)
508 pci_socket_t *socket = (pci_socket_t *) data;
510 yenta_interrupt(0, (void *)socket, NULL);
511 socket->poll_timer.expires = jiffies + HZ;
512 add_timer(&socket->poll_timer);
516 * Only probe "regular" interrupts, don't
517 * touch dangerous spots like the mouse irq,
518 * because there are mice that apparently
519 * get really confused if they get fondled
522 * Default to 11, 10, 9, 7, 6, 5, 4, 3.
524 static u32 isa_interrupts = 0x0ef8;
526 static unsigned int yenta_probe_irq(pci_socket_t *socket, u32 isa_irq_mask)
533 /* Set up ISA irq routing to probe the ISA irqs.. */
534 bridge_ctrl = config_readw(socket, CB_BRIDGE_CONTROL);
535 if (!(bridge_ctrl & CB_BRIDGE_INTR)) {
536 bridge_ctrl |= CB_BRIDGE_INTR;
537 config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl);
541 * Probe for usable interrupts using the force
542 * register to generate bogus card status events.
544 cb_writel(socket, CB_SOCKET_EVENT, -1);
545 cb_writel(socket, CB_SOCKET_MASK, CB_CSTSMASK);
546 exca_writeb(socket, I365_CSCINT, 0);
547 val = probe_irq_on() & isa_irq_mask;
548 for (i = 1; i < 16; i++) {
549 if (!((val >> i) & 1))
551 exca_writeb(socket, I365_CSCINT, I365_CSC_STSCHG | (i << 4));
552 cb_writel(socket, CB_SOCKET_FORCE, CB_FCARDSTS);
554 cb_writel(socket, CB_SOCKET_EVENT, -1);
556 cb_writel(socket, CB_SOCKET_MASK, 0);
557 exca_writeb(socket, I365_CSCINT, 0);
559 mask = probe_irq_mask(val) & 0xffff;
561 bridge_ctrl &= ~CB_BRIDGE_INTR;
562 config_writew(socket, CB_BRIDGE_CONTROL, bridge_ctrl);
568 * Set static data that doesn't need re-initializing..
570 static void yenta_get_socket_capabilities(pci_socket_t *socket, u32 isa_irq_mask)
572 socket->cap.features |= SS_CAP_PAGE_REGS | SS_CAP_PCCARD | SS_CAP_CARDBUS;
573 socket->cap.map_size = 0x1000;
574 socket->cap.pci_irq = socket->cb_irq;
575 socket->cap.irq_mask = yenta_probe_irq(socket, isa_irq_mask);
576 socket->cap.cb_dev = socket->dev;
577 socket->cap.bus = NULL;
579 printk("Yenta IRQ list %04x, PCI irq%d\n", socket->cap.irq_mask, socket->cb_irq);
582 extern void cardbus_register(pci_socket_t *socket);
585 * 'Bottom half' for the yenta_open routine. Allocate the interrupt line
586 * and register the socket with the upper layers.
588 static void yenta_open_bh(void * data)
590 pci_socket_t * socket = (pci_socket_t *) data;
592 /* It's OK to overwrite this now */
593 socket->tq_task.routine = yenta_bh;
595 if (!socket->cb_irq || request_irq(socket->cb_irq, yenta_interrupt, SA_SHIRQ, socket->dev->name, socket)) {
596 /* No IRQ or request_irq failed. Poll */
597 socket->cb_irq = 0; /* But zero is a valid IRQ number. */
598 socket->poll_timer.function = yenta_interrupt_wrapper;
599 socket->poll_timer.data = (unsigned long)socket;
600 socket->poll_timer.expires = jiffies + HZ;
601 add_timer(&socket->poll_timer);
604 /* Figure out what the dang thing can do for the PCMCIA layer... */
605 yenta_get_socket_capabilities(socket, isa_interrupts);
606 printk("Socket status: %08x\n", cb_readl(socket, CB_SOCKET_STATE));
608 /* Register it with the pcmcia layer.. */
609 cardbus_register(socket);
614 static void yenta_clear_maps(pci_socket_t *socket)
617 pccard_io_map io = { 0, 0, 0, 0, 1 };
618 pccard_mem_map mem = { 0, 0, 0, 0, 0, 0 };
620 mem.sys_stop = 0x0fff;
621 yenta_set_socket(socket, &dead_socket);
622 for (i = 0; i < 2; i++) {
624 yenta_set_io_map(socket, &io);
626 for (i = 0; i < 5; i++) {
628 yenta_set_mem_map(socket, &mem);
633 * Initialize the standard cardbus registers
635 static void yenta_config_init(pci_socket_t *socket)
638 struct pci_dev *dev = socket->dev;
640 pci_set_power_state(socket->dev, 0);
642 config_writel(socket, CB_LEGACY_MODE_BASE, 0);
643 config_writel(socket, PCI_BASE_ADDRESS_0, dev->resource[0].start);
644 config_writew(socket, PCI_COMMAND,
650 /* MAGIC NUMBERS! Fixme */
651 config_writeb(socket, PCI_CACHE_LINE_SIZE, L1_CACHE_BYTES / 4);
652 config_writeb(socket, PCI_LATENCY_TIMER, 168);
653 config_writel(socket, PCI_PRIMARY_BUS,
654 (176 << 24) | /* sec. latency timer */
655 (dev->subordinate->subordinate << 16) | /* subordinate bus */
656 (dev->subordinate->secondary << 8) | /* secondary bus */
657 dev->subordinate->primary); /* primary bus */
660 * Set up the bridging state:
661 * - enable write posting.
662 * - memory window 0 prefetchable, window 1 non-prefetchable
663 * - PCI interrupts enabled if a PCI interrupt exists..
665 bridge = config_readw(socket, CB_BRIDGE_CONTROL);
666 bridge &= ~(CB_BRIDGE_CRST | CB_BRIDGE_PREFETCH1 | CB_BRIDGE_INTR | CB_BRIDGE_ISAEN | CB_BRIDGE_VGAEN);
667 bridge |= CB_BRIDGE_PREFETCH0 | CB_BRIDGE_POSTEN;
669 bridge |= CB_BRIDGE_INTR;
670 config_writew(socket, CB_BRIDGE_CONTROL, bridge);
672 exca_writeb(socket, I365_GBLCTL, 0x00);
673 exca_writeb(socket, I365_GENCTL, 0x00);
675 /* Redo card voltage interrogation */
676 cb_writel(socket, CB_SOCKET_FORCE, CB_CVSTEST);
679 /* Called at resume and initialization events */
680 static int yenta_init(pci_socket_t *socket)
682 yenta_config_init(socket);
683 yenta_clear_maps(socket);
685 /* Re-enable interrupts */
686 cb_writel(socket, CB_SOCKET_MASK, CB_CDMASK);
690 static int yenta_suspend(pci_socket_t *socket)
692 yenta_set_socket(socket, &dead_socket);
694 /* Disable interrupts */
695 cb_writel(socket, CB_SOCKET_MASK, 0x0);
698 * This does not work currently. The controller
699 * loses too much information during D3 to come up
700 * cleanly. We should probably fix yenta_init()
701 * to update all the critical registers, notably
702 * the IO and MEM bridging region data.. That is
703 * something that pci_set_power_state() should
704 * probably know about bridges anyway.
706 pci_set_power_state(socket->dev, 3);
713 * Use an adaptive allocation for the memory resource,
714 * sometimes the size behind pci bridges is limited:
715 * 1/8 of the size of the io window of the parent.
716 * max 4 MB, min 16 kB.
718 #define BRIDGE_SIZE_MAX 4*1024*1024
719 #define BRIDGE_SIZE_MIN 16*1024
721 static void yenta_allocate_res(pci_socket_t *socket, int nr, unsigned type)
724 struct resource *root, *res;
726 u32 align, size, min, max;
730 /* The granularity of the memory limit is 4kB, on IO it's 4 bytes */
732 if (type & IORESOURCE_IO)
735 offset = 0x1c + 8*nr;
736 bus = socket->dev->subordinate;
737 res = socket->dev->resource + PCI_BRIDGE_RESOURCES + nr;
738 res->name = bus->name;
742 root = pci_find_parent_resource(socket->dev, res);
747 start = config_readl(socket, offset) & mask;
748 end = config_readl(socket, offset+4) | ~mask;
749 if (start && end > start) {
752 if (request_resource(root, res) == 0)
754 printk(KERN_INFO "yenta %s: Preassigned resource %d busy, reconfiguring...\n",
755 socket->dev->slot_name, nr);
756 res->start = res->end = 0;
759 if (type & IORESOURCE_IO) {
765 unsigned long avail = root->end - root->start;
767 align = size = BRIDGE_SIZE_MAX;
768 if (size > avail/8) {
770 /* round size down to next power of 2 */
772 while ((size /= 2) != 0)
776 if (size < BRIDGE_SIZE_MIN)
777 size = BRIDGE_SIZE_MIN;
779 min = PCIBIOS_MIN_MEM; max = ~0U;
782 if (allocate_resource(root, res, size, min, max, align, NULL, NULL) < 0) {
783 printk(KERN_INFO "yenta %s: no resource of type %x available, trying to continue...\n",
784 socket->dev->slot_name, type);
785 res->start = res->end = 0;
789 config_writel(socket, offset, res->start);
790 config_writel(socket, offset+4, res->end);
794 * Allocate the bridge mappings for the device..
796 static void yenta_allocate_resources(pci_socket_t *socket)
798 yenta_allocate_res(socket, 0, IORESOURCE_MEM|IORESOURCE_PREFETCH);
799 yenta_allocate_res(socket, 1, IORESOURCE_MEM);
800 yenta_allocate_res(socket, 2, IORESOURCE_IO);
801 yenta_allocate_res(socket, 3, IORESOURCE_IO); /* PCI isn't clever enough to use this one yet */
805 * Free the bridge mappings for the device..
807 static void yenta_free_resources(pci_socket_t *socket)
811 struct resource *res;
812 res = socket->dev->resource + PCI_BRIDGE_RESOURCES + i;
813 if (res->start != 0 && res->end != 0)
814 release_resource(res);
815 res->start = res->end = 0;
819 * Close it down - release our resources and go home..
821 static void yenta_close(pci_socket_t *sock)
823 /* Disable all events so we don't die in an IRQ storm */
824 cb_writel(sock, CB_SOCKET_MASK, 0x0);
825 exca_writeb(sock, I365_CSCINT, 0);
828 free_irq(sock->cb_irq, sock);
830 del_timer_sync(&sock->poll_timer);
834 yenta_free_resources(sock);
841 * Different cardbus controllers have slightly different
842 * initialization sequences etc details. List them here..
844 #define PD(x,y) PCI_VENDOR_ID_##x, PCI_DEVICE_ID_##x##_##y
845 static struct cardbus_override_struct {
846 unsigned short vendor;
847 unsigned short device;
848 struct pci_socket_ops *op;
849 } cardbus_override[] = {
850 { PD(TI,1130), &ti113x_ops },
851 { PD(TI,1031), &ti_ops },
852 { PD(TI,1131), &ti113x_ops },
853 { PD(TI,1250), &ti1250_ops },
854 { PD(TI,1220), &ti_ops },
855 { PD(TI,1221), &ti_ops },
856 { PD(TI,1210), &ti_ops },
857 { PD(TI,1450), &ti_ops },
858 { PD(TI,1225), &ti_ops },
859 { PD(TI,1251A), &ti_ops },
860 { PD(TI,1211), &ti_ops },
861 { PD(TI,1251B), &ti_ops },
862 { PD(TI,1410), &ti_ops },
863 { PD(TI,1420), &ti_ops },
864 { PD(TI,4410), &ti_ops },
865 { PD(TI,4451), &ti_ops },
867 { PD(RICOH,RL5C465), &ricoh_ops },
868 { PD(RICOH,RL5C466), &ricoh_ops },
869 { PD(RICOH,RL5C475), &ricoh_ops },
870 { PD(RICOH,RL5C476), &ricoh_ops },
871 { PD(RICOH,RL5C478), &ricoh_ops }
874 #define NR_OVERRIDES (sizeof(cardbus_override)/sizeof(struct cardbus_override_struct))
877 * Initialize a cardbus controller. Make sure we have a usable
878 * interrupt, and that we can map the cardbus area. Fill in the
879 * socket information structure..
881 static int yenta_open(pci_socket_t *socket)
884 struct pci_dev *dev = socket->dev;
887 * Do some basic sanity checking..
889 if (pci_enable_device(dev))
891 if (!pci_resource_start(dev, 0)) {
892 printk("No cardbus resource!\n");
897 * Ok, start setup.. Map the cardbus registers,
898 * and request the IRQ.
900 socket->base = ioremap(pci_resource_start(dev, 0), 0x1000);
904 yenta_config_init(socket);
906 /* Disable all events */
907 cb_writel(socket, CB_SOCKET_MASK, 0x0);
909 /* Set up the bridge regions.. */
910 yenta_allocate_resources(socket);
912 socket->cb_irq = dev->irq;
914 /* Do we have special options for the device? */
915 for (i = 0; i < NR_OVERRIDES; i++) {
916 struct cardbus_override_struct *d = cardbus_override+i;
917 if (dev->vendor == d->vendor && dev->device == d->device) {
920 int retval = d->op->open(socket);
927 /* Get the PCMCIA kernel thread to complete the
928 initialisation later. We can't do this here,
929 because, er, because Linus says so :)
931 socket->tq_task.routine = yenta_open_bh;
932 socket->tq_task.data = socket;
935 schedule_task(&socket->tq_task);
941 * Standard plain cardbus - no frills, no extensions
943 struct pci_socket_ops yenta_operations = {
957 EXPORT_SYMBOL(yenta_operations);
958 MODULE_LICENSE("GPL");