drivers/scsi/atp870u.c

   1 /* $Id: atp870u.c,v 1.4 2005/12/12 06:25:19 axl Exp $
   2  *  linux/kernel/atp86x.c
   3  *
   4  *  Copyright (C) 2003-04       ACARD
   5  *  Modified by Jason Wu from aec6285.c to support ATP865 chip
   6  *
   7  *  0.10        2003/12/19
   8  *              1. Modify atp86x_detect()
   9  *
  10  *  0.11        2003/12/19
  11  *              1. Change file name from AEC6885.X to atp86x.c and .h
  12  *              2. Change routine name from aec6285 to atp86x
  13  *  0.12        2003/12/19
  14  *              1. Modify atp86x_detect()
  15  *                 (1) 865: init chip registers.
  16  *  0.13        2003/12/22
  17  *              1. Modify atp86x_detect()
  18  *                 (1) is865: scan device
  19  *  0.14        2003/12/22
  20  *              1. Modify is865()
  21  *                 (1) display the correct debug message of idenfity device command
  22  *  0.15        2003/12/22
  23  *              1. Modify is865()
  24  *                 (1) display more correct debug message of idenfity device command
  25  *                 (2) display "UDMA xxx" after inquiry string..
  26  *              2. Modify atp86x_release()
  27  *                 (1) If 865, release region is different to 867.
  28  *  0.16        2003/12/22
  29  *              1. disable "DETECT_DEBUG" and "IS865_DEBUG"
  30  *              2. Modify atp86x_queuecommand()
  31  *                 (1) S860Io():
  32  *  0.17        2003/12/23
  33  *              1. S860IO(): display more debug messages
  34  *              2. BuildSrb& RAID05: don't change ..
  35  *              3. Noiocmd: don't change ..
  36  *              4. SendSCSI: second argument: baseioaddress[0]= channel 0, baseioaddress[1] = channel 1
  37  *  0.18        2003/12/23
  38  *              1. atp86x_intr_handle
  39  *  0.20        2003/12/23
  40  *              1. Change version string.
  41  *              2. atp86x_abort: change nothing..
  42  *  0.30        2003/12/23
  43  *              1. atp86x_reset:
  44  *  0.40        2003/12/23
  45  *              1. S3init: change name to ATP867init
  46  *              2. ATP865init: init the ATP865 chip.
  47  *              3. ATP865init: should send 3x6 software reset first.
  48  *  0.50        2003/12/26
  49  *              1. Define ATP865 chip number= 0x0008,0x0009 and ATP867=0x000A
  50  *              2. ATP865: If chip version <= A3, should run UDMA100 only.
  51  *              3. Print out not supported commands...
  52  *                 (1) IO commands: 0x28,0x2a,0x08,0x0a,0x2b,0x0b,0x35,0x2f,0x1b
  53  *                 (2) No IO commands: 0x1a, 0x12, 0x25, 0x03
  54  *                 (3) Always status good: 0x00, 0x15, 0x55, 0x1e, 0x04
  55  *                 (4) Always status check condition:  All others.
  56  *                     Sense key : 05/20/00 not supported commands?
  57  *
  58  *  0.60        2003/12/27
  59  *              1. Inquiry EVPD support:
  60  *                 (1) Other pages: return 05/24/00
  61  *              2. ISR: Error handling: Sense key table implementation.
  62  *                 (1) CRC Error: print out the debug message for release mode
  63  *                 (2) Media Error: read/write/verify commands
  64  *                 (3) Abort command:
  65  *                 (4) Invalid address: read/write/seek/verify commands
  66  *              3. Bad sector: sense key with bad sector LBA info
  67  *              4. Command 0x2E support!
  68  *              5. Sense key should be enough for each HDD.( [8] for each card [16] for each buffer)
  69  *
  70  *  0.70        2004/1/14
  71  *              1. IXP425: Big Endian problem
  72  *                 (1) Inquiry: First 8 bytes should be filled in byte-unit. -> DONE
  73  *                 (2) Read Capacity: block length should be filled in byte-unit. ->DONE
  74  *                 (3) Read Capacity: Capacity Wrong! (identify command should get capacity in byte-unit)->DONE
  75  *              2. IXP425: Big Endian problem
  76  *                 (1) RAID05: use byte-unit to fill PRD table. -> DONE
  77  *                 (2) Send SCSI: IDE command and PCI control should be seperated.
  78  *                     -> Sendnorm: UCHAR for blkno, UCHAR pcicmd, UCHAR cmd. -> DONE
  79  *                 (3) BuildSrb: Transfer counter should be set in byte-unit. -> DONE
  80  *
  81  *  0.71        2004/1/14
  82  *              1. IXP425: Test if allocate memory use GFP_ATOMIC parameter.
  83  *              2. IXP42X_DEBUG_MSG = ON
  84  *
  85  *  0.72        2004/1/14
  86  *              1. IXP425: Test if allocate memory use GFP_ATOMIC|GFP_DMA parameter.
  87  *              2. IXP42X_DEBUG_MSG = OFF
  88  *
  89  *  0.73        2004/1/14
  90  *              1. IXP425: Send SCSI: IDE command and PCI control should be seperated.
  91  *                     -> Sendbigd: USHORT for blkno, UCHAR pcicmd, UCHAR cmd. ->DONE
  92  *              2. IXP425: Is865 Bug: Inquiry command: first 8 bytes not modified.
  93  *              3. IXP425: is867 Bug:
  94  *                 Read Capacity: Capacity Wrong! (identify command should get capacity in byte-unit)->DONE
  95  *  0.74        2004/1/14
  96  *              1. Function get_disk_err_LBA: Bug! Bad sector LBA error for 48-bit LBA mode.
  97  *                 HOB problem -> DONE
  98  *
  99  *  0.75        2004/1/15
 100  *              1.IXP425: Try to allocate memory by pci_alloc_consistent() and pci_free_consistent
 101  *
 102  *  0.76        2004/1/15
 103  *              1.ATP867: PowerOn: I2C delay too long?
 104  *                        Remove I2C_ENABLE
 105  *  0.77        2004/1/15
 106  *              1. IXP425: Big-Endian: Mode sense problem: #define MODESENSE_DEBUG -> DONE
 107  *
 108  *  0.78        2004/1/15
 109  *              1. IXP42X_DEBUG -> IXP42X_SUPPORT
 110  *              2. Queue count: enlarge to max 128 queues per card.
 111  *
 112  * Pending issues
 113  *              1. Inquiry EVPD page 80 : serial number support.
 114  *              2. Invalid address check: for Read/Write/seek/verify commands.
 115  *              3. Reassign block command support.
 116  *              4. Abort: function not implement
 117  *              5. Reset: function should be well tested
 118  *              6. Sendbigd: Should clear HOB first.
 119  *              7. Save Flags? Cli? Restore Flags? -> Protect sections that prevent the queue function fails.
 120  *              8. ATP867: PowerOn: WD HDD -> UDMA 133?? Bugs?
 121  *                         ata66? is66? iswd? If the first driver=133, the next drive will become 133?
 122  *              9. Mode select (6) not supported.
 123  */
 124
 125 #define DEBUG_UDMA    // Always set to indicate the UDMA mode for HDDs
 126 #define IXP42X_SUPPORT  // IXP Big-Endian problem fixed
 127 //#define MODESENSE_DEBUG
 128 //#define I2C_ENABLE
 129 //#define IXP42X_DEBUG_MSG
 130 //#define DETECT_DEBUG
 131 //#define IS865_DEBUG
 132 //#define QUEUECOMMAND_DEBUG
 133 //#define INTR_DEBUG
 134 //#define RESET_DEBUG
 135 //#define DEBUG_SENSEKEY
 136
 137 #include <linux/module.h>
 138
 139 #include <linux/kernel.h>
 140 #include <linux/types.h>
 141 #include <linux/string.h>
 142 #include <linux/ioport.h>
 143 #include <linux/delay.h>
 144 #include <linux/sched.h>
 145 #include <linux/proc_fs.h>
 146 #include <linux/spinlock.h>
 147 #include <asm/system.h>
 148 #include <asm/io.h>
 149 #include <linux/pci.h>
 150 #include <linux/blk.h>
 151 #include "scsi.h"
 152 #include "hosts.h"
 153
 154
 155 #include "atp870u.h"
 156
 157 #include<linux/stat.h>
 158
 159 #define UCHAR    unsigned char
 160 #define USHORT   unsigned short
 161 #define ULONG    unsigned long
 162 #define PUCHAR    unsigned char *
 163 #define PUSHORT   unsigned short *
 164 #define PULONG    unsigned long *
 165
 166
 167 #define Inpb(x,y)      inb((x + y))
 168 #define Outpb(x,y,z)   outb(z, (x + y))
 169 #define Inpw(x,y)     inw((x + y))
 170 #define Outpw(x,y,z)  outw(z, (x + y))
 171 #define Inpl(x,y)      inl((x + y))
 172 #define Outpl(x,y,z)   outl(z, (x + y))
 173
 174 static unsigned char admaxu = 3;
 175 static unsigned int irqnumu[4] = {0, 0, 0, 0};
 176
 177 struct hw_lu_ext {
 178 #ifdef IXP42X_SUPPORT
 179     dma_addr_t prdaddr;
 180 #else
 181     ULONG   prdaddr;
 182 #endif
 183
 184     PUCHAR  prd;
 185     ULONG   wslba;
 186     USHORT  wsblkno;
 187 };
 188
 189 struct hw_device_ext {
 190     struct hw_lu_ext lsrb[4][qcnt1];
 191     struct hw_lu_ext *Cplsrb[4];
 192     struct hw_lu_ext *plsrb[4][qcnt1];
 193     struct pci_dev *pdev;
 194
 195     ULONG   BaseIoAddress[4];
 196     ULONG   BaseIoAddresm[4];
 197     ULONG   irq,in_int;
 198     Scsi_Cmnd * CSrb[4];
 199     Scsi_Cmnd * QSrb[4][qcnt1];
 200     ULONG   cap[8];
 201     ULONG   que_hd[4],que_end[4],bigdrv[8];
 202     USHORT  active_id;
 203     UCHAR   devtype[8];
 204     UCHAR   dskerr[8];
 205     UCHAR   hd_status[8];
 206     UCHAR   page0[16];
 207     UCHAR   page1[24];
 208     UCHAR   page1c[24];
 209     UCHAR   sensd[8][16];
 210     ULONG   dskerr_LBA[8];
 211 //    UCHAR   sensda[14];
 212 //    UCHAR   sensdok[14];
 213 //    UCHAR   inqdat[8][38];
 214         UCHAR   inqdat[8][56];  //axl+
 215 // add for smart read  =================//
 216         Scsi_Cmnd               SmartSrb;
 217         ULONG                                   SmartReadID;
 218         struct timer_list               AdapterTimer;
 219         UCHAR                                   FG_TimerStop;
 220         UCHAR                                   FG_SmartRead;
 221 //======================================//
 222         UCHAR   dev_id,chipver,ata66;
 223     UCHAR   host_id,c_mask;
 224
 225 //axl+
 226     ULONG   SamwiseBaseIoAddress;
 227     UCHAR   SamwiseHDSelect;
 228 //axl end
 229 };
 230 // add for smart read  =================//
 231 USHORT  smart_buf[256];
 232 void    smart_timer(ULONG para);
 233 //======================================//
 234
 235 static struct Scsi_Host *a867host[4] = {NULL, NULL, NULL, NULL};
 236 static struct hw_device_ext dev_ext[4];
 237
 238 int S860Io(struct hw_device_ext * devext, Scsi_Cmnd * Srb);
 239 int BuildSrb(struct hw_device_ext * devext, struct hw_lu_ext * srbp, Scsi_Cmnd * Srb);
 240 int Raid05(struct hw_device_ext * devext, struct hw_lu_ext * srbp, Scsi_Cmnd * Srb);
 241 int SendScsi(struct hw_device_ext * devext, Scsi_Cmnd * Srb, ULONG Ch);
 242 #ifdef IXP42X_SUPPORT
 243 void Sendnorm(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, UCHAR wkblkno, UCHAR pcicmd, UCHAR cmd);
 244 void Sendbigd(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, USHORT wkblkno, UCHAR pcicmd, UCHAR cmd);
 245 #else
 246 void Sendnorm(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, USHORT wkblkno, USHORT cmd);
 247 void Sendbigd(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, USHORT wkblkno, USHORT cmd);
 248 #endif
 249 void Noiocmd(struct hw_device_ext * devext, Scsi_Cmnd * Srb);
 250 #ifdef I2C_ENABLE
 251 int i2cwrite(ULONG baseIoAddress, UCHAR Rindex, UCHAR Rval);
 252 int i2cread(ULONG baseIoAddress, UCHAR Rindex, PUCHAR Rval);
 253 #endif
 254 void ATP867init(struct hw_device_ext * devext);
 255 void ATP865init(struct hw_device_ext * devext);
 256 int fill_sensekey_buf(struct hw_device_ext * devext, UCHAR tid);
 257
 258
 259 int get_disk_err_LBA(struct hw_device_ext * devext, UCHAR tid)
 260 {
 261         ULONG  baseIoAddress= devext->BaseIoAddress[tid>>1];
 262         ULONG  baseIoAddress2= devext->BaseIoAddress[(tid>>1)+2];
 263         UCHAR  tmp;
 264
 265         if (devext->bigdrv[tid] == 0)
 266         {
 267                 // if 28-bit LBA
 268                 // 1x3 =
 269                 // 1x4 =
 270                 // 1x5 =
 271                 // 1x6 =
 272                 tmp = Inpb(baseIoAddress,0x3);
 273                 devext->dskerr_LBA[tid] = tmp;
 274 #ifdef DEBUG_SENSEKEY
 275                 printk("28-bit LBA 1X3 = %2X",tmp);
 276 #endif
 277                 tmp = Inpb(baseIoAddress,0x4);
 278                 devext->dskerr_LBA[tid] |= (tmp<<8);
 279 #ifdef DEBUG_SENSEKEY
 280                 printk("1X4 = %2X",tmp);
 281 #endif
 282                 tmp = Inpb(baseIoAddress,0x5);
 283                 devext->dskerr_LBA[tid] |= (tmp<<16);
 284 #ifdef DEBUG_SENSEKEY
 285                 printk("1X5 = %2X",tmp);
 286 #endif
 287                 tmp = Inpb(baseIoAddress,0x6);
 288                 devext->dskerr_LBA[tid] |= ((tmp<<24) & 0x0F);
 289 #ifdef DEBUG_SENSEKEY
 290                 printk("1X6 = %2X \n",tmp);
 291 #endif
 292         }
 293         else
 294         {
 295                 // HOB=0: 1X3=LBA(7:0)   1X4= LBA(15:8) 1X5=LBA(23:16)
 296                 // HOB=1: 1X3=LBA(31:24) 1X4=LBA(39:32) 1X5=LBA(47:40)
 297                 outb(0x00, baseIoAddress2+2);
 298 #ifdef DEBUG_SENSEKEY
 299                 printk("48-bit Error LBA HOB = 0\n",tmp);
 300 #endif
 301                 tmp = Inpb(baseIoAddress,0x3);
 302                 devext->dskerr_LBA[tid] = tmp;
 303 #ifdef DEBUG_SENSEKEY
 304                 printk("1X3 = %2X",tmp);
 305 #endif
 306                 tmp = Inpb(baseIoAddress,0x4);
 307                 devext->dskerr_LBA[tid] |= (tmp<<8);
 308 #ifdef DEBUG_SENSEKEY
 309                 printk("1X4 = %2X",tmp);
 310 #endif
 311                 tmp = Inpb(baseIoAddress,0x5);
 312                 devext->dskerr_LBA[tid] |= (tmp<<16);
 313 #ifdef DEBUG_SENSEKEY
 314                 printk("1X5 = %2X\n",tmp);
 315 #endif
 316                 outb(0x80, baseIoAddress2+2);
 317 #ifdef DEBUG_SENSEKEY
 318                 printk("48-bit Error LBA HOB = 1\n",tmp);
 319 #endif
 320                 tmp = Inpb(baseIoAddress,0x3);
 321                 devext->dskerr_LBA[tid] |= (tmp<<24);
 322 #ifdef DEBUG_SENSEKEY
 323                 printk("2nd 1X3 = %2X",tmp);
 324 #endif
 325                 tmp = Inpb(baseIoAddress,0x4);
 326 #ifdef DEBUG_SENSEKEY
 327                 printk("2nd 1X4 = %2X",tmp);
 328 #endif
 329                 tmp = Inpb(baseIoAddress,0x5);
 330 #ifdef DEBUG_SENSEKEY
 331                 printk("2nd 1X5 = %2X\n",tmp);
 332 #endif
 333                 outb(0x00, baseIoAddress2+2);
 334                 tmp = Inpb(baseIoAddress,0x6);
 335         }
 336 #ifdef DEBUG_SENSEKEY
 337         printk("1X6 = %2X LBA=%8lX\n",tmp,devext->dskerr_LBA[tid]);
 338 #endif
 339         return 0;
 340 }
 341
 342 static void atp86x_intr_handle(int irq, void *dev_id, struct pt_regs *regs)
 343 {
 344      struct hw_device_ext *devext = dev_id;
 345      ULONG  flags;
 346      ULONG  baseIoAddress;
 347      ULONG  baseIoAddresm;
 348 //     ULONG  lba;
 349      Scsi_Cmnd * CSrb;
 350      ULONG  Ch, x;
 351      UCHAR  TargetId,intn;
 352      UCHAR  i,h,k;
 353 #ifdef I2C_ENABLE
 354      UCHAR  l;
 355 #endif
 356         unsigned short  Value16;
 357         unsigned char*  pData;
 358
 359         pData = &smart_buf[0];
 360
 361      for (h = 0; h < 4; h++) {
 362              if (irq == irqnumu[h]) {
 363                      goto irq_numok;
 364              }
 365      }
 366      return;
 367 irq_numok:
 368      devext->in_int++;
 369     if (devext->dev_id == ATP867_DEVID1)
 370     {
 371         baseIoAddress = devext->BaseIoAddress[0];
 372 #ifdef I2C_ENABLE
 373         if ((Inpb(baseIoAddress,0x2a) & devext->c_mask) != 0)
 374         {
 375                 i=Inpb(baseIoAddress,0x2a) & devext->c_mask;
 376                 for (k=0; k < 4; k++)
 377                 {
 378                         if ((i & 0x10) != 0)
 379                         {
 380                                 baseIoAddress = devext->BaseIoAddress[k];
 381                                 i2cread(baseIoAddress,0x41,&l);
 382                                 i2cread(baseIoAddress,0x42,&l);
 383                                 i2cread(baseIoAddress,0x40,&l);
 384                                 i2cread(baseIoAddress,0x41,&l);
 385                                 i2cread(baseIoAddress,0x42,&l);
 386                                 Outpb(baseIoAddress,0x43,0x20);
 387                         }
 388                         i >>= 1;
 389                 }
 390                 baseIoAddress = devext->BaseIoAddress[0];
 391         }
 392 #endif
 393         intn=Inpb(baseIoAddress,0x2a) & 0x0f;
 394 //check_irq:
 395         for (Ch=0 ;Ch < 4; Ch++)
 396         {
 397                 i=1;
 398                 i <<= Ch;
 399                 if ((intn & i) != 0)
 400                 {
 401                         baseIoAddress = devext->BaseIoAddress[Ch];
 402                         baseIoAddresm = devext->BaseIoAddresm[Ch];
 403                         intn &= ~i;
 404                         if (devext->CSrb[Ch] != 0)
 405                         {
 406                                 CSrb=devext->CSrb[Ch];
 407                                 goto do_irq3;
 408                         }
 409                         else
 410                         {
 411                                 Inpb(baseIoAddress,7);
 412                                 Outpb(baseIoAddresm,2,0x06);
 413                         }
 414                 }
 415         }
 416     }
 417     else
 418     {
 419         for (Ch=0 ;Ch < 2; Ch++)
 420         {
 421         // ATP865
 422                 baseIoAddress = devext->BaseIoAddresm[Ch];
 423                 intn=Inpb(baseIoAddress,2) & 0x06;
 424 #ifdef INTR_DEBUG
 425                 printk("865INTR:Ch = %2lX intn = %2X \n",Ch,intn);
 426 #endif
 427 //check_irq:
 428                 if ((intn & 0x04) != 0)
 429                 {
 430                         baseIoAddress = devext->BaseIoAddress[Ch];
 431                         baseIoAddresm = devext->BaseIoAddresm[Ch];
 432
 433                         if (devext->CSrb[Ch] != 0)
 434                         {
 435                                 CSrb=devext->CSrb[Ch];
 436                                 goto do_irq3;
 437                         }
 438                         else
 439                         {
 440                                 Inpb(baseIoAddress,7);
 441                                 Outpb(baseIoAddresm,2,0x06);
 442                         }
 443                 }
 444         }
 445     }
 446     devext->in_int--;
 447     return;
 448
 449 do_irq3:
 450 #ifdef INTR_DEBUG
 451    printk("86XINTR:do_irq3: target = %2X \n",CSrb->target);
 452 #endif
 453    TargetId=CSrb->target;
 454    Outpb(baseIoAddresm,0,0);
 455    i=Inpb(baseIoAddress,7);
 456    Outpb(baseIoAddresm,2,0x06);
 457    i &= 0xf9;
 458 // add for smart read  =================//
 459    if (CSrb->cmnd[0] == 0xB0)
 460    {
 461 //printk("Smart Read Interrupt,status:%02X",i);
 462         if ((i == 0x58) || (i == 0x48))
 463         {
 464                 for (x = 0 ; x < 256 ; x++)
 465                 {
 466                         Value16 = Inpw(baseIoAddress,0);
 467                         *(pData+(x<<1))         = (unsigned char)Value16;
 468                         *(pData+(x<<1)+1)       = (unsigned char)(Value16>>8);
 469                 }
 470                 CSrb->result = 0x00;
 471         }
 472         else
 473         {
 474                 devext->hd_status[TargetId]=0x51;
 475                 CSrb->result=0x02;
 476                 devext->dskerr[TargetId]=0xB0; // 0B/00/00 aborted command
 477         }
 478         i = Inpb(baseIoAddress,7);
 479 //printk(",status:%02X\n",i);
 480         devext->FG_SmartRead = 0;
 481         goto interrupt_keep_going;
 482    }
 483 //======================================//
 484    if ((i != 0x50) && (i != 0x40))
 485    {
 486       k=Inpb(baseIoAddress,1);
 487 //#ifdef DEBUG_SENSEKEY
 488       printk("\nATP86X: Ch %2lX ID %2X Error: status=%2X error reg=%2X\n",Ch,TargetId,i,k);
 489 //#endif
 490       if (k& 0x80)
 491       {
 492 #ifdef DEBUG_SENSEKEY
 493                 printk("ATP86X: CRC Error:");
 494 #endif
 495                 devext->dskerr[TargetId]=0x48;  // 04/08/03 CRC Error
 496       }
 497       else if (k&0x54)
 498       {
 499 #ifdef DEBUG_SENSEKEY
 500                 printk("ATP86X: Media Error:");
 501 #endif
 502         if (CSrb->cmnd[0]==0x0A || CSrb->cmnd[0]==0x2A || CSrb->cmnd[0]==0x2E)
 503         {
 504                 devext->dskerr[TargetId]=0x3C;  // 03/0C/00 Write Error
 505 // Get Error LBA here and fill into dskerr_LBA[TargetId]  48-bit or 28-bit
 506                 get_disk_err_LBA(devext,TargetId);
 507         }
 508         else if (CSrb->cmnd[0]==0x08 || CSrb->cmnd[0]==0x28 || CSrb->cmnd[0]==0x2F ||
 509                  CSrb->cmnd[0]==0x0B || CSrb->cmnd[0]==0x2B )
 510         {
 511                 devext->dskerr[TargetId]=0x31;  // 03/11/00 Read Error
 512 // Get Error LBA here and fill into dskerr_LBA[TargetId]  48-bit or 28-bit
 513                 get_disk_err_LBA(devext,TargetId);
 514         }
 515         else devext->dskerr[TargetId]=0xB0; // 0B/00/00 aborted command
 516       }
 517       else
 518       {
 519 //              devext->dskerr[TargetId]=0x51;
 520                 devext->dskerr[TargetId]=0xB0; // 0B/00/00 aborted command
 521       }
 522 #ifdef DEBUG_SENSEKEY
 523       printk("CDB=");
 524       for (i=0;i<CSrb->cmd_len;i++ )
 525         printk("%2X ",CSrb->cmnd[i]);
 526       printk("\n");
 527 #endif
 528       devext->hd_status[TargetId]=0x51;
 529       CSrb->result=0x02;
 530    }
 531    else
 532    {
 533       CSrb->result = 0x00;
 534    }
 535 // add for smart read  =================//
 536 interrupt_keep_going:
 537 //======================================//
 538
 539    spin_lock_irqsave(&io_request_lock, flags);
 540    (*CSrb->scsi_done) (CSrb);
 541    devext->CSrb[Ch]=0;
 542    if (devext->que_hd[Ch] != devext->que_end[Ch])
 543    {
 544       if ((devext->que_hd[Ch] += 1) > qcnt1 - 1)
 545       {
 546          devext->que_hd[Ch]=0;
 547       }
 548       devext->CSrb[Ch]=devext->QSrb[Ch][devext->que_hd[Ch]];
 549       devext->Cplsrb[Ch]=devext->plsrb[Ch][devext->que_hd[Ch]];
 550       SendScsi(devext,devext->CSrb[Ch],Ch);
 551    }
 552    spin_unlock_irqrestore(&io_request_lock, flags);
 553    devext->in_int--;
 554    return;
 555 }
 556
 557 int atp86x_queuecommand(Scsi_Cmnd * req_p, void (*done) (Scsi_Cmnd *))
 558 {
 559         UCHAR h;
 560         ULONG flags,Ch;
 561         struct hw_device_ext *devext;
 562
 563         for (h = 0; h <= admaxu; h++) {
 564                 if (req_p->host == a867host[h]) {
 565                         goto host_ok;
 566                 }
 567         }
 568         return 0;
 569 host_ok:
 570         if (!done) {
 571                 printk(KERN_WARNING "atp86x_queuecommand: done can't be NULL\n");
 572                 req_p->result = 0;
 573                 done(req_p);
 574                 return 0;
 575         }
 576         if (req_p->channel != 0) {
 577                 req_p->result = 0x00040000;
 578                 done(req_p);
 579                 return 0;
 580         }
 581         save_flags(flags);
 582         cli();
 583         devext = &dev_ext[h];
 584         req_p->scsi_done = done;
 585
 586         if (!S860Io(devext,req_p))
 587         {
 588            restore_flags(flags);
 589            return 0;
 590         }
 591         if (devext->in_int == 0)
 592         {
 593            Ch = (ULONG)(req_p->target >> 1);
 594            if ((devext->CSrb[Ch] == 0) &&
 595                (devext->que_hd[Ch] != devext->que_end[Ch]))
 596            {
 597               if ( devext->que_hd[Ch] == qcnt1 - 1 )
 598               {
 599                  devext->que_hd[Ch]=0;
 600               }
 601               else
 602               {
 603                  devext->que_hd[Ch]++;
 604               }
 605               devext->CSrb[Ch]=devext->QSrb[Ch][devext->que_hd[Ch]];
 606               devext->Cplsrb[Ch]=devext->plsrb[Ch][devext->que_hd[Ch]];
 607               SendScsi(devext,devext->CSrb[Ch],Ch);
 608            }
 609         }
 610         restore_flags(flags);
 611         return 0;
 612 }
 613
 614 int S860Io(struct hw_device_ext * devext, Scsi_Cmnd * Srb)
 615 {
 616     struct hw_lu_ext *srbp;
 617     UCHAR i,j,t;
 618 #ifdef QUEUECOMMAND_DEBUG
 619         printk("S860IO: Srb->lun= %2X devext->dev_id= %2X\n",Srb->lun,devext->dev_id);
 620 #endif
 621     if ( Srb->lun > 0 )
 622     {
 623        Srb->result = 0x00040000;
 624        Srb->scsi_done(Srb);
 625        return FALSE;
 626     }
 627     t = Srb->target;
 628     if (devext->dev_id == ATP867_DEVID1)
 629     {
 630         if ((t > 7) || (devext->cap[t] == 0))
 631         {
 632                 Srb->result = 0x00040000;
 633                 Srb->scsi_done(Srb);
 634                 return FALSE;
 635         }
 636     }
 637     else
 638     {
 639 #ifdef QUEUECOMMAND_DEBUG
 640         printk("S860IO: t= %2X devext->cap[t]= %8lX\n",t,devext->cap[t]);
 641 #endif
 642         if ((t > 4) || (devext->cap[t] == 0))
 643         {
 644                 Srb->result = 0x00040000;
 645                 Srb->scsi_done(Srb);
 646                 return FALSE;
 647         }
 648     }
 649 #ifdef QUEUECOMMAND_DEBUG
 650         printk("S860IO: Srb->cmnd[0] = %2X hd_status[t]= %2X\n",Srb->cmnd[0],devext->hd_status[t]);
 651 #endif
 652     j=Srb->cmnd[0];
 653     if ((j == 0x28) || (j == 0x2a) || (j == 0x2e)|| (j == 0x08) ||
 654         (j == 0x0a) || (j == 0x2b) || (j == 0x0b) ||
 655         (j == 0x35) || (j == 0x2f) || (j == 0x1b))
 656     {
 657        if (devext->hd_status[t] == 0x7f)
 658        {
 659           Srb->result = 0x02;
 660           Srb->scsi_done(Srb);
 661           return FALSE;
 662        }
 663
 664        i = t >> 1;
 665        if ((devext->que_end[i] += 1) > qcnt1 - 1)
 666        {
 667           devext->que_end[i]=0;
 668        }
 669        devext->QSrb[i][devext->que_end[i]]=Srb;
 670        srbp=devext->plsrb[i][devext->que_end[i]];
 671        BuildSrb(devext, srbp ,Srb);
 672        return TRUE;
 673     }
 674     else
 675     {
 676        Noiocmd(devext,Srb);
 677        Srb->scsi_done(Srb);
 678     }
 679     return FALSE;
 680 }
 681
 682 int BuildSrb(struct hw_device_ext * devext, struct hw_lu_ext * srbp, Scsi_Cmnd * Srb)
 683 {
 684
 685    if (Srb->cmd_len == 0x06)
 686    {
 687       ((PUCHAR)&srbp->wslba)[0]=Srb->cmnd[3];
 688       ((PUCHAR)&srbp->wslba)[1]=Srb->cmnd[2];
 689       ((PUCHAR)&srbp->wslba)[2]=Srb->cmnd[1];
 690       ((PUCHAR)&srbp->wslba)[3]=Srb->cmnd[0];
 691       srbp->wslba &= 0x000fffff;
 692       srbp->wsblkno=Srb->cmnd[4];
 693       srbp->wsblkno &=0x00ff;
 694    }
 695    else
 696    {
 697       ((PUCHAR)&srbp->wslba)[0]=Srb->cmnd[5];
 698       ((PUCHAR)&srbp->wslba)[1]=Srb->cmnd[4];
 699       ((PUCHAR)&srbp->wslba)[2]=Srb->cmnd[3];
 700       ((PUCHAR)&srbp->wslba)[3]=Srb->cmnd[2];
 701 #ifdef IXP42X_SUPPORT
 702       srbp->wsblkno = Srb->cmnd[8];
 703       if (Srb->cmnd[7]!=0) srbp->wsblkno |= (USHORT)(Srb->cmnd[7]<<8);
 704 #else
 705       ((PUCHAR)&srbp->wsblkno)[0]=Srb->cmnd[8];
 706       ((PUCHAR)&srbp->wsblkno)[1]=Srb->cmnd[7];
 707 #endif
 708    }
 709 #ifdef IXP42X_DEBUG_MSG
 710       printk("BuildSrb: c[0]=%2X c[1]=%2X c[2]=%2X c[3]=%2X c[4]=%2X c[5]=%2x lba=%8lx\n",Srb->cmnd[0],Srb->cmnd[1],
 711                       Srb->cmnd[2],Srb->cmnd[3],Srb->cmnd[4],Srb->cmnd[5],srbp->wslba);
 712       printk("BuildSrb: c[6]=%2X c[7]=%2X c[8]=%2X blkno=%4X\n",Srb->cmnd[6],Srb->cmnd[7],Srb->cmnd[8],srbp->wsblkno);
 713 #endif
 714    return (Raid05(devext,srbp,Srb));
 715 }
 716
 717 int Raid05(struct hw_device_ext * devext, struct hw_lu_ext * srbp, Scsi_Cmnd * Srb)
 718 {
 719    ULONG  baddr;
 720    ULONG  maplen;
 721    ULONG  leng,l1;
 722 #ifdef IXP42X_DEBUG_MSG
 723    ULONG  l2;
 724 #endif
 725    struct scatterlist *sgpnt;
 726    UCHAR  i;
 727
 728    sgpnt = (struct scatterlist *) Srb->request_buffer;
 729    if (Srb->use_sg)
 730    {
 731            leng = 0;
 732            for (i = 0; i < Srb->use_sg; i++)
 733            {
 734                    if (sgpnt[i].length == 0 || Srb->use_sg > ATP86X_SCATTER)
 735                    {
 736                            panic("Foooooooood fight!");
 737                    }
 738                    leng += sgpnt[i].length;
 739            }
 740    } else {
 741            leng = Srb->request_bufflen;
 742    }
 743    if ((leng != 0x00) && (Srb->cmnd[0] != 0x2f))
 744    {
 745       l1=0;
 746       i=0;
 747       while ( leng > 0 )
 748       {
 749          if (Srb->use_sg)
 750          {
 751             baddr = virt_to_bus(sgpnt[i].address);
 752             maplen = sgpnt[i++].length;
 753          } else {
 754             baddr = virt_to_bus(Srb->request_buffer);
 755             maplen = Srb->request_bufflen;
 756          }
 757          if ( maplen > leng )
 758          {
 759             maplen=leng;
 760          }
 761 #ifdef IXP42X_SUPPORT
 762          srbp->prd[l1]=(UCHAR)baddr;
 763          srbp->prd[l1+1]=(UCHAR)(baddr>>8);
 764          srbp->prd[l1+2]=(UCHAR)(baddr>>16);
 765          srbp->prd[l1+3]=(UCHAR)(baddr>>24);
 766          l1+=4;
 767 #else
 768          ((PULONG)srbp->prd)[l1++]=baddr;
 769 #endif
 770 next_64k:
 771 #ifdef IXP42X_DEBUG_MSG
 772         printk("RAID05: Srb->use_sg = %4X l1=%2lX maplen=%8lX baddr=%8lX\n",Srb->use_sg,l1,maplen,baddr);
 773 #endif
 774          if ( maplen > 0x10000 )
 775          {
 776 #ifdef IXP42X_SUPPORT
 777             srbp->prd[l1]=0;
 778             srbp->prd[l1+1]=0;
 779             srbp->prd[l1+2]=0;
 780             srbp->prd[l1+3]=0;
 781             l1+=4;
 782 #else
 783             ((PULONG)srbp->prd)[l1++]=0;
 784 #endif
 785             maplen -= 0x10000;
 786             leng -= 0x10000;
 787             baddr += 0x10000;
 788 #ifdef IXP42X_SUPPORT
 789             srbp->prd[l1]=(UCHAR)baddr;
 790             srbp->prd[l1+1]=(UCHAR)(baddr>>8);
 791             srbp->prd[l1+2]=(UCHAR)(baddr>>16);
 792             srbp->prd[l1+3]=(UCHAR)(baddr>>24);
 793             l1+=4;
 794 #else
 795             ((PULONG)srbp->prd)[l1++]=baddr;
 796 #endif
 797             goto next_64k;
 798          }
 799          leng -= maplen;
 800 #ifdef IXP42X_SUPPORT
 801          srbp->prd[l1]=(UCHAR)maplen;
 802          srbp->prd[l1+1]=(UCHAR)(maplen>>8);
 803          srbp->prd[l1+2]=0;
 804          srbp->prd[l1+3]=0;
 805          l1+=4;
 806 #else
 807          ((PULONG)srbp->prd)[l1++]=maplen;
 808 #endif
 809       }
 810 #ifdef IXP42X_SUPPORT
 811       l1--;
 812       srbp->prd[l1]=0x80;
 813 #else
 814       l1=((l1 << 2) - 2) >> 1;
 815       ((PUSHORT)srbp->prd)[l1]=0x8000;
 816 #endif
 817    }
 818 #ifdef IXP42X_DEBUG_MSG
 819    for (l1=0;l1<=Srb->use_sg;l1++)
 820    {
 821       printk("l1= %2lX ",l1);
 822       for (l2=l1*8;l2<(l1*8+8);l2++)
 823       {
 824         printk("[%2lX]= %2X ",l2,(UCHAR) (srbp->prd[l2]));
 825       }
 826       printk("\n");
 827    }
 828 #endif
 829    return TRUE ;
 830 }
 831
 832 int SendScsi(struct hw_device_ext * devext, Scsi_Cmnd * Srb, ULONG Ch)
 833 {
 834    ULONG baseIoAddress = devext->BaseIoAddress[Ch];
 835    ULONG baseIoAddresm = devext->BaseIoAddresm[Ch];
 836    struct hw_lu_ext * srbp;
 837    ULONG  t;
 838 #ifndef IXP42X_SUPPORT
 839    USHORT k;
 840 #endif
 841    UCHAR  devno;
 842
 843 #ifdef QUEUECOMMAND_DEBUG
 844    printk("SendSCSI: Ch=%2lX Tarrget=%2X CDB[0]= %2X  \n",Ch,Srb->target,Srb->cmnd[0]);
 845 #endif
 846    srbp=devext->Cplsrb[Ch];
 847
 848    Outpb(baseIoAddresm,2,0x06);
 849
 850    t = (ULONG)Srb->target;
 851    if ((t & 1) == 0)
 852    {
 853       devno=0xe0;
 854    }
 855    else
 856    {
 857       devno=0xf0;
 858    }
 859    Outpb(baseIoAddress,6,devno);
 860 // add for smart read  =================//
 861    if (Srb->cmnd[0] == 0xB0)
 862    {
 863         Outpb(baseIoAddress,1,0xD0);
 864         Outpb(baseIoAddress,4,0x4F);
 865         Outpb(baseIoAddress,5,0xC2);
 866         Outpb(baseIoAddress,7,0xB0);
 867         return TRUE;
 868    }
 869 //=====================================//
 870    if ((Srb->cmnd[0] == 0x28) || (Srb->cmnd[0] == 0x2a) || (Srb->cmnd[0] == 0x2e) ||
 871        (Srb->cmnd[0] == 0x08) || (Srb->cmnd[0] == 0x0a))
 872    {
 873       Outpl(baseIoAddresm,4,srbp->prdaddr);
 874 #ifdef IXP42X_SUPPORT
 875       if (devext->bigdrv[t] == 0)
 876       {
 877          if ((Srb->cmnd[0] == 0x2a) || (Srb->cmnd[0] == 0x0a) || (Srb->cmnd[0] == 0x2e))
 878          {
 879             Sendnorm(baseIoAddress,baseIoAddresm,srbp->wslba,(UCHAR)srbp->wsblkno,0x01,0xca);
 880          }
 881          else
 882          {
 883             Sendnorm(baseIoAddress,baseIoAddresm,srbp->wslba,(UCHAR)srbp->wsblkno,0x09,0xc8);
 884          }
 885       }
 886       else
 887       {
 888          if ((Srb->cmnd[0] == 0x2a) || (Srb->cmnd[0] == 0x0a)|| (Srb->cmnd[0] == 0x2e))
 889          {
 890             Sendbigd(baseIoAddress,baseIoAddresm,srbp->wslba,srbp->wsblkno,0x01,0x35);
 891          }
 892          else
 893          {
 894             Sendbigd(baseIoAddress,baseIoAddresm,srbp->wslba,srbp->wsblkno,0x09,0x25);
 895          }
 896       }
 897 #else
 898       if (devext->bigdrv[t] == 0)
 899       {
 900          if ((Srb->cmnd[0] == 0x2a) || (Srb->cmnd[0] == 0x0a) || (Srb->cmnd[0] == 0x2e))
 901          {
 902             k=0x01ca;
 903          }
 904          else
 905          {
 906             k=0x09c8;
 907          }
 908          Sendnorm(baseIoAddress,baseIoAddresm,srbp->wslba,srbp->wsblkno,k);
 909       }
 910       else
 911       {
 912          if ((Srb->cmnd[0] == 0x2a) || (Srb->cmnd[0] == 0x0a)|| (Srb->cmnd[0] == 0x2e))
 913          {
 914             k=0x0135;
 915          }
 916          else
 917          {
 918             k=0x0925;
 919          }
 920          Sendbigd(baseIoAddress,baseIoAddresm,srbp->wslba,srbp->wsblkno,k);
 921       }
 922 #endif
 923
 924       return TRUE;
 925    }
 926
 927    if (Srb->cmnd[0] == 0x35)
 928    {
 929       if (devext->bigdrv[t] == 0)
 930       {
 931          Outpb(baseIoAddress,7,0xe7);
 932       }
 933       else
 934       {
 935          Outpb(baseIoAddress,7,0xea);
 936       }
 937       return TRUE ;
 938    }
 939
 940    if (Srb->cmnd[0] == 0x1b)
 941    {
 942       if (Srb->cmnd[4] == 0x00)
 943       {
 944 #ifdef IXP42X_SUPPORT
 945          Sendnorm(baseIoAddress,baseIoAddresm,0,0,0x00,0xe0);
 946 #else
 947          Sendnorm(baseIoAddress,baseIoAddresm,0,0,0x00e0);
 948 #endif
 949       }
 950       else
 951       {
 952 #ifdef IXP42X_SUPPORT
 953          Sendnorm(baseIoAddress,baseIoAddresm,0,0x40,0x00,0x40);
 954 #else
 955          Sendnorm(baseIoAddress,baseIoAddresm,0,0x40,0x40);
 956 #endif
 957       }
 958       return TRUE ;
 959    }
 960
 961    if ((Srb->cmnd[0] == 0x0b) || (Srb->cmnd[0] == 0x2b))
 962    {
 963       if (devext->bigdrv[t] == 0)
 964       {
 965 #ifdef IXP42X_SUPPORT
 966          Sendnorm(baseIoAddress,baseIoAddresm,srbp->wslba,1,0x00,0x70);
 967 #else
 968          Sendnorm(baseIoAddress,baseIoAddresm,srbp->wslba,1,0x70);
 969 #endif
 970       }
 971       else
 972       {
 973 #ifdef IXP42X_SUPPORT
 974          Sendbigd(baseIoAddress,baseIoAddresm,srbp->wslba,1,0X00,0x42);
 975 #else
 976          Sendbigd(baseIoAddress,baseIoAddresm,srbp->wslba,1,0x42);
 977 #endif
 978       }
 979       return TRUE ;
 980    }
 981
 982    if (Srb->cmnd[0] == 0x2f)
 983    {
 984       if (devext->bigdrv[t] == 0)
 985       {
 986 #ifdef IXP42X_SUPPORT
 987          Sendnorm(baseIoAddress,baseIoAddresm,srbp->wslba,(UCHAR) srbp->wsblkno,0x00,0x40);
 988 #else
 989          Sendnorm(baseIoAddress,baseIoAddresm,srbp->wslba,srbp->wsblkno,0x40);
 990 #endif
 991       }
 992       else
 993       {
 994 #ifdef IXP42X_SUPPORT
 995          Sendbigd(baseIoAddress,baseIoAddresm,srbp->wslba,srbp->wsblkno,0x00,0x42);
 996 #else
 997          Sendbigd(baseIoAddress,baseIoAddresm,srbp->wslba,srbp->wsblkno,0x42);
 998 #endif
 999       }
1000    }
1001    return TRUE ;
1002 }
1003
1004 #ifdef IXP42X_SUPPORT
1005 void Sendnorm(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, UCHAR wkblkno, UCHAR pcicmd, UCHAR cmd)
1006 {
1007       UCHAR  i;
1008
1009       outb(wkblkno, baseIoAddress + 2);
1010 #ifdef IXP42X_DEBUG_MSG
1011       printk("Sendnorm: 1X2 wkblkno=%2X \n",wkblkno);
1012 #endif
1013       outb(((PUCHAR)&wklba)[0], baseIoAddress+3);
1014 #ifdef IXP42X_DEBUG_MSG
1015       printk("Sendnorm: 1X3 = %2X \n",((PUCHAR)&wklba)[0]);
1016 #endif
1017       outb(((PUCHAR)&wklba)[1], baseIoAddress+4);
1018 #ifdef IXP42X_DEBUG_MSG
1019       printk("Sendnorm: 1X4 = %2X \n",((PUCHAR)&wklba)[1]);
1020 #endif
1021       outb(((PUCHAR)&wklba)[2], baseIoAddress+5);
1022 #ifdef IXP42X_DEBUG_MSG
1023       printk("Sendnorm: 1X5 = %2X \n",((PUCHAR)&wklba)[2]);
1024 #endif
1025       i=((PUCHAR)&wklba)[3] & 0x0f;
1026
1027       outb((UCHAR)((inb(baseIoAddress+6) & 0xf0) | i), baseIoAddress+6);
1028 #ifdef IXP42X_DEBUG_MSG
1029       printk("Sendnorm: 1X6 = %2X \n",inb(baseIoAddress+6));
1030 #endif
1031       outb(cmd, baseIoAddress+7);
1032 #ifdef IXP42X_DEBUG_MSG
1033       printk("Sendnorm: 1X7 = %2X \n",cmd);
1034 #endif
1035       outb(pcicmd, baseIoAddresm);
1036 #ifdef IXP42X_DEBUG_MSG
1037       printk("Sendnorm: PCI cmd = %2X \n",pcicmd);
1038 #endif
1039       return;
1040 }
1041
1042 void Sendbigd(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, USHORT wkblkno, UCHAR pcicmd, UCHAR cmd)
1043 {
1044 //      outb(((PUCHAR)&wkblkno)[1], baseIoAddress+2);
1045       outb((UCHAR)(wkblkno>>8),baseIoAddress+2);
1046 #ifdef IXP42X_DEBUG_MSG
1047       printk("Sendbigd: 1X2 =%2X  wkblkno=%2X\n",(UCHAR)(wkblkno>>8),wkblkno);
1048 #endif
1049 //      outb(((PUCHAR)&wkblkno)[0], baseIoAddress+2);
1050       outb((UCHAR)(wkblkno),baseIoAddress+2);
1051 #ifdef IXP42X_DEBUG_MSG
1052       printk("Sendbigd: 1X2 =%2X  wkblkno=%2X\n",(UCHAR)(wkblkno),wkblkno);
1053 #endif
1054       outb(((PUCHAR)&wklba)[3], baseIoAddress+3);
1055 #ifdef IXP42X_DEBUG_MSG
1056       printk("Sendbigd: 1X3 =%2X \n",((PUCHAR)&wklba)[3]);
1057 #endif
1058       outb(0, baseIoAddress+4);
1059 #ifdef IXP42X_DEBUG_MSG
1060       printk("Sendbigd: 1X4 =0 \n");
1061 #endif
1062       outb(0, baseIoAddress+5);
1063 #ifdef IXP42X_DEBUG_MSG
1064       printk("Sendbigd: 1X5 =0 \n");
1065 #endif
1066       outb(((PUCHAR)&wklba)[0], baseIoAddress+3);
1067 #ifdef IXP42X_DEBUG_MSG
1068       printk("Sendbigd: 1X3 =%2X \n",((PUCHAR)&wklba)[0]);
1069 #endif
1070       outb(((PUCHAR)&wklba)[1], baseIoAddress+4);
1071 #ifdef IXP42X_DEBUG_MSG
1072       printk("Sendbigd: 1X4 =%2X \n",((PUCHAR)&wklba)[1]);
1073 #endif
1074       outb(((PUCHAR)&wklba)[2], baseIoAddress+5);
1075 #ifdef IXP42X_DEBUG_MSG
1076       printk("Sendbigd: 1X5 =%2X \n",((PUCHAR)&wklba)[2]);
1077 #endif
1078       outb(cmd, baseIoAddress+7);
1079 #ifdef IXP42X_DEBUG_MSG
1080       printk("Sendbigd: 1X7 =%2X \n",cmd);
1081 #endif
1082       outb(pcicmd, baseIoAddresm);
1083 #ifdef IXP42X_DEBUG_MSG
1084       printk("Sendbigd: pcicmd =%2X \n",pcicmd);
1085 #endif
1086       return;
1087 }
1088
1089 #else
1090
1091 void Sendnorm(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, USHORT wkblkno, USHORT cmd)
1092 {
1093       UCHAR  i;
1094
1095       outb((UCHAR)wkblkno, baseIoAddress + 2);
1096       outb(((PUCHAR)&wklba)[0], baseIoAddress+3);
1097       outb(((PUCHAR)&wklba)[1], baseIoAddress+4);
1098       outb(((PUCHAR)&wklba)[2], baseIoAddress+5);
1099       i=((PUCHAR)&wklba)[3] & 0x0f;
1100       outb((UCHAR)((inb(baseIoAddress+6) & 0xf0) | i), baseIoAddress+6);
1101       outb(((PUCHAR)&cmd)[0], baseIoAddress+7);
1102       outb(((PUCHAR)&cmd)[1], baseIoAddresm);
1103       return;
1104 }
1105 void Sendbigd(ULONG baseIoAddress, ULONG baseIoAddresm, ULONG wklba, USHORT wkblkno, USHORT cmd)
1106 {
1107       outb(((PUCHAR)&wkblkno)[1], baseIoAddress+2);
1108       outb(((PUCHAR)&wkblkno)[0], baseIoAddress+2);
1109       outb(((PUCHAR)&wklba)[3], baseIoAddress+3);
1110       outb(0, baseIoAddress+4);
1111       outb(0, baseIoAddress+5);
1112       outb(((PUCHAR)&wklba)[0], baseIoAddress+3);
1113       outb(((PUCHAR)&wklba)[1], baseIoAddress+4);
1114       outb(((PUCHAR)&wklba)[2], baseIoAddress+5);
1115       outb(((PUCHAR)&cmd)[0], baseIoAddress+7);
1116       outb(((PUCHAR)&cmd)[1], baseIoAddresm);
1117       return;
1118 }
1119
1120 #endif
1121
1122
1123
1124 static void internal_done(Scsi_Cmnd * SCpnt)
1125 {
1126         SCpnt->SCp.Status++;
1127 }
1128
1129 int atp86x_command(Scsi_Cmnd * SCpnt)
1130 {
1131
1132         atp86x_queuecommand(SCpnt, internal_done);
1133
1134         SCpnt->SCp.Status = 0;
1135         while (!SCpnt->SCp.Status)
1136                 barrier();
1137         return SCpnt->result;
1138 }
1139
1140 int fill_sensekey_buf(struct hw_device_ext * devext, UCHAR tid)
1141 {
1142         int i;
1143         static UCHAR sensd[16]=   {0xF0,0,0x03,0,0,0,0,0x8,0,0,0,0,0x11,0x00,0,0};
1144         static UCHAR sensdw[16]=  {0xF0,0,0x03,0,0,0,0,0x8,0,0,0,0,0x0C,0x00,0,0};
1145         static UCHAR sensda[16]=  {0x70,0,0x05,0,0,0,0,0x8,0,0,0,0,0x20,0x00,0,0};
1146         static UCHAR sensdif[16]= {0x70,0,0x05,0,0,0,0,0x8,0,0,0,0,0x24,0x00,0,0};
1147         static UCHAR sensdip[16]= {0x70,0,0x05,0,0,0,0,0x8,0,0,0,0,0x26,0x00,0,0};
1148         static UCHAR sensdor[16]= {0xF0,0,0x05,0,0,0,0,0x8,0,0,0,0,0x1A,0x00,0,0};
1149         static UCHAR sensdcrc[16]={0x70,0,0x04,0,0,0,0,0x8,0,0,0,0,0x08,0x03,0,0};
1150         static UCHAR sensdabt[16]={0x70,0,0x0B,0,0,0,0,0x8,0,0,0,0,0x00,0x00,0,0};
1151         static UCHAR sensdok[16]= {0x70,0,0x00,0,0,0,0,0x8,0,0,0,0,0x00,0x00,0,0};
1152
1153         switch (devext->dskerr[tid])
1154         {
1155                 case 0x50:
1156                                for(i=0;i<16;i++)
1157                                {
1158                                     devext->sensd[tid][i]=sensda[i];
1159                                }
1160                                break;
1161                 case 0x54:
1162                                for(i=0;i<16;i++)
1163                                {
1164                                     devext->sensd[tid][i]=sensdif[i];
1165                                }
1166                                break;
1167                 case 0x56:
1168                                for(i=0;i<16;i++)
1169                                {
1170                                     devext->sensd[tid][i]=sensdip[i];
1171                                }
1172                                break;
1173                 case 0x5A:
1174                                for(i=0;i<16;i++)
1175                                {
1176                                     devext->sensd[tid][i]=sensdor[i];
1177                                }
1178                                goto fill_err_LBA;
1179                 case 0x31:
1180                                for(i=0;i<16;i++)
1181                                {
1182                                     devext->sensd[tid][i]=sensd[i];
1183                                }
1184 fill_err_LBA:
1185                                devext->sensd[tid][3]=(UCHAR)((devext->dskerr_LBA[tid]>>24));
1186                                devext->sensd[tid][4]=(UCHAR)((devext->dskerr_LBA[tid]>>16));
1187                                devext->sensd[tid][5]=(UCHAR)((devext->dskerr_LBA[tid]>>8));
1188                                devext->sensd[tid][6]=(UCHAR)(devext->dskerr_LBA[tid]);
1189                                break;
1190                 case 0x3C:
1191                                for(i=0;i<16;i++)
1192                                {
1193                                     devext->sensd[tid][i]=sensdw[i];
1194                                }
1195                                goto fill_err_LBA;
1196                 case 0x48:
1197                                for(i=0;i<16;i++)
1198                                {
1199                                     devext->sensd[tid][i]=sensdcrc[i];
1200                                }
1201                                break;
1202                 case 0x00:
1203                                for(i=0;i<16;i++)
1204                                {
1205                                     devext->sensd[tid][i]=sensdok[i];
1206                                }
1207                                break;
1208                 case 0xB0:
1209                 default:
1210                                for(i=0;i<16;i++)
1211                                {
1212                                     devext->sensd[tid][i]=sensdabt[i];
1213                                }
1214                                break;
1215         }
1216 #ifdef DEBUG_SENSEKEY
1217                                printk("TID %2X SenseKey=",tid);
1218                                for(i=0;i<16;i++)
1219                                {
1220                                     printk("%2X ",devext->sensd[tid][i]);
1221                                }
1222                                printk("\n");
1223 #endif
1224         return 0;
1225 }
1226
1227 //axl+
1228 unsigned char EnableSMART(struct hw_device_ext * devext)
1229 {
1230         unsigned char   Value8;
1231
1232         Outpb(devext->SamwiseBaseIoAddress, 6, devext->SamwiseHDSelect);
1233         mdelay(10);
1234
1235         Value8 = Inpb(devext->SamwiseBaseIoAddress, 7);
1236         if((Value8 & 0x88) != 0x00)
1237         {
1238            return 1;
1239         }
1240
1241         /* ATA Identify device command */
1242         Outpb(devext->SamwiseBaseIoAddress, 1, 0xd8);
1243         Outpb(devext->SamwiseBaseIoAddress, 4, 0x4f);
1244         Outpb(devext->SamwiseBaseIoAddress, 5, 0xc2);
1245         Outpb(devext->SamwiseBaseIoAddress, 7, 0xb0);
1246         mdelay(400);
1247
1248         while(1)
1249         {
1250         Value8 = Inpb(devext->SamwiseBaseIoAddress, 7);
1251         if((Value8 & 0x80) == 0 )
1252         {
1253                 break;
1254         }
1255         }
1256
1257         if ((Value8 & 0x01) == 0x01 )
1258         {
1259                 return 2;
1260         }
1261
1262         if ((Value8 & 0xf8) == 0x58 )
1263         {
1264                 return 3;
1265         }
1266
1267         return 0;
1268 }//end EnableSMART()
1269 //axl-
1270
1271 void Noiocmd(struct hw_device_ext * devext, Scsi_Cmnd * Srb)
1272 {
1273     UCHAR i,j,t;
1274     UCHAR c[8];
1275     PUCHAR saddr;
1276     ULONG l;
1277     struct scatterlist *sgpnt;
1278 //#ifdef MODESENSE_DEBUG
1279 //          printk("Noiocmd: CDB=%2X %2X %2X %2X %2X %2X %2X %2X %2X %2X\n",Srb->cmnd[0],Srb->cmnd[1],
1280 //                      Srb->cmnd[2],Srb->cmnd[3],Srb->cmnd[4],Srb->cmnd[5],Srb->cmnd[6],Srb->cmnd[7],
1281 //                      Srb->cmnd[8],Srb->cmnd[9]);
1282 //#endif
1283             sgpnt = (struct scatterlist *) Srb->request_buffer;
1284             if (Srb->use_sg)
1285             {
1286                saddr = sgpnt[0].address;
1287             } else {
1288                saddr=Srb->request_buffer;
1289             }
1290             t = Srb->target;
1291             j=Srb->cmnd[0];
1292             if (j == 0x1a)
1293             {
1294 #ifdef MODESENSE_DEBUG
1295                 printk("Noiocmd: Mode Sense(6): Page=%2X, length=%2X cap=%8lX\n",Srb->cmnd[2],Srb->cmnd[4],
1296                         devext->cap[t]);
1297 #endif
1298                l=devext->cap[t];
1299 #ifdef IXP42X_SUPPORT
1300                devext->page0[4]=(UCHAR)(l>>24);
1301                devext->page0[5]=(UCHAR)(l>>16);
1302                devext->page0[6]=(UCHAR)(l>>8);
1303                devext->page0[7]=(UCHAR)(l);
1304                devext->page1[4]=(UCHAR)(l>>24);
1305                devext->page1[5]=(UCHAR)(l>>16);
1306                devext->page1[6]=(UCHAR)(l>>8);
1307                devext->page1[7]=(UCHAR)(l);
1308                devext->page1c[4]=(UCHAR)(l>>24);
1309                devext->page1c[5]=(UCHAR)(l>>16);
1310                devext->page1c[6]=(UCHAR)(l>>8);
1311                devext->page1c[7]=(UCHAR)(l);
1312 #else
1313                i=((PUCHAR)&l)[0];
1314                ((PUCHAR)&l)[0]=((PUCHAR)&l)[3];
1315                ((PUCHAR)&l)[3]=i;
1316                i=((PUCHAR)&l)[1];
1317                ((PUCHAR)&l)[1]=((PUCHAR)&l)[2];
1318                ((PUCHAR)&l)[2]=i;
1319                ((PULONG)&devext->page0[4])[0]=l;
1320                ((PULONG)&devext->page1[4])[0]=l;
1321                ((PULONG)&devext->page1c[4])[0]=l;
1322 #endif
1323                Srb->result=0;
1324 #ifdef MODESENSE_DEBUG
1325                printk("Noiocm: Mode Sense(6): Page data[4]=%2X %2X %2X %2X\n",devext->page0[4],
1326                       devext->page0[5],devext->page0[6],devext->page0[7]);
1327 #endif
1328                j=Srb->cmnd[4];
1329                if ((Srb->cmnd[2] & 0x3f) == 0)
1330                {
1331                   if ( j > 0x10 )
1332                   {
1333                      j=0x10;
1334                   }
1335                   memcpy(saddr,&devext->page0[0],j);
1336                }
1337                else
1338                {
1339                   if ((Srb->cmnd[2] & 0x3f) == 1)
1340                   {
1341                      if ( j > 0x18 )
1342                      {
1343                         j=0x18;
1344                      }
1345                      memcpy(saddr,&devext->page1[0],j);
1346                   }
1347                   else
1348                   {
1349                      if ((Srb->cmnd[2] & 0x3f) == 0x1c)
1350                      {
1351                         if ( j > 0x18 )
1352                         {
1353                            j=0x18;
1354                         }
1355                         memcpy(saddr,&devext->page1c[0],j);
1356                      }
1357                      else
1358                      {
1359                         if ((Srb->cmnd[2] & 0x3f) == 0x3f)
1360                         {
1361                            i=j;
1362                            if ( i > 0x18 )
1363                            {
1364                               i=0x18;
1365                            }
1366                            memcpy(saddr,&devext->page1[0],i);
1367                            c[0]=0x33;
1368                            memcpy(saddr,&c[0],1);
1369                            (ULONG)saddr += i;
1370                            j -= i;
1371                            i=j;
1372                            if ( i > 0x0c )
1373                            {
1374                               i=0x0c;
1375                            }
1376                            memcpy(saddr,&devext->page1c[12],i);
1377                            (ULONG)saddr += i;
1378                            j -= i;
1379                            i=j;
1380                            if ( i > 0x10 )
1381                            {
1382                               i=0x10;
1383                            }
1384                            memcpy(saddr,&devext->page0[0],i);
1385                         }
1386                         else
1387                         {
1388                            goto do_autosens;
1389                         }
1390                      }
1391                   }
1392                }
1393                goto EXECUTE_SCSI1;
1394             }
1395             if ( j == 0x12 )
1396             {
1397 //axl +
1398                 switch(Srb->cmnd[3])
1399                 {
1400                         case 0:
1401                                if (Srb->cmnd[1] & 0x01)
1402                                {
1403                                         devext->dskerr[t]=0x54;
1404                                         goto print_autosens; // EVPD not supported
1405                                }
1406                                j=Srb->cmnd[4];
1407                                                if ( j > 0x38 )
1408                                {
1409                                                                 j=0x38;
1410                                }
1411                                memcpy(saddr,&devext->inqdat[t][0],j);
1412                                Srb->result=0;
1413                                break;
1414
1415                         case 1:
1416                                 memcpy(saddr, smart_buf, sizeof(smart_buf));
1417                                 Srb->result=0;
1418                                break;
1419                         }
1420                 goto EXECUTE_SCSI1;
1421             }
1422             if ( j == 0x01 )
1423             {
1424 {
1425                 unsigned char cStatus;
1426                 Srb->result = EnableSMART(devext);
1427 //              printk("EnableSMART cStatus %x\n",Srb->result);
1428                 if(Srb->result == 0)
1429                 {
1430                         devext->inqdat[t][38] = 1;
1431                 }
1432 }
1433 //axl end
1434                goto EXECUTE_SCSI1;
1435             }
1436             if ( j == 0x25 )
1437             {
1438 #ifdef IXP42X_SUPPORT
1439                c[0]= (UCHAR) (devext->cap[t]>>24);
1440                c[1]= (UCHAR) (devext->cap[t]>>16);
1441                c[2]= (UCHAR) (devext->cap[t]>>8);
1442                c[3]= (UCHAR) (devext->cap[t]);
1443                c[4]= 0x00;
1444                c[5]= 0x00;
1445                c[6]= 0x02; // block length = 512 bytes
1446                c[7]= 0x00;
1447 #else
1448                c[0]=((PUCHAR)(&devext->cap[t]))[3];
1449                c[1]=((PUCHAR)(&devext->cap[t]))[2];
1450                c[2]=((PUCHAR)(&devext->cap[t]))[1];
1451                c[3]=((PUCHAR)(&devext->cap[t]))[0];
1452                ((PULONG)&c[4])[0]=0x00020000;
1453 #endif
1454                memcpy(saddr,&c[0],8);
1455                Srb->result=0;
1456                goto EXECUTE_SCSI1;
1457             }
1458             if ( j == 0x03 )
1459             {
1460 #ifdef DEBUG_SENSEKEY
1461                printk("ATP86X: Request sense command comes!\n");
1462 #endif
1463                j=Srb->cmnd[4];
1464                if ( j > 0x10 )
1465                {
1466                   j=0x10;
1467                }
1468                fill_sensekey_buf(devext,t);
1469                memcpy(saddr,&devext->sensd[t][0],j);
1470                devext->dskerr[t]=0;
1471                Srb->result=0;
1472                goto EXECUTE_SCSI1;
1473             }
1474             Srb->result=0;
1475             if ((j != 0x00) && (j != 0x15) && (j != 0x55) &&
1476                 (j != 0x1e) && (j != 0x04))
1477             {
1478 //printk("Noiocmd: NOT 'TUR' 'Mode Select(6)' 'Mode Select(10)' 'PAMR' 'FORMAT UNIT'\n");
1479 do_autosens:
1480                devext->dskerr[t]=0x50;
1481 print_autosens:
1482                Srb->result=0x02;
1483 #ifdef DEBUG_SENSEKEY
1484                printk("ATP86X: Not supported CDB = ");
1485                for (j=0;j<Srb->cmd_len;j++ )
1486                 printk("%2X ",Srb->cmnd[j]);
1487                printk("\n");
1488 #endif
1489             }
1490 EXECUTE_SCSI1:
1491             return ;
1492 }
1493
1494 void is867(struct hw_device_ext * devext)
1495 {
1496     ULONG baseIoAddress = devext->BaseIoAddress[0];
1497     ULONG  r;
1498     UCHAR  i,j,k,l,ata66,is66,iswd;
1499     UCHAR  cbuf[4];
1500     USHORT m,mbuf[256];
1501
1502     /* Port 4A: IDE0 8 bit IO ports speed  */
1503     Outpb(baseIoAddress,0x4a,0x43);
1504     Outpb(baseIoAddress,0x5a,0x43);
1505     Outpb(baseIoAddress,0x6a,0x43);
1506     Outpb(baseIoAddress,0x7a,0x43);
1507
1508     ata66=0x00;
1509     devext->ata66=ata66;
1510     /* Port 48: IDE0 master DATA PIO/NDMA speed : 0aaarrrr
1511        Port 49: IDE0 slave  DATA PIO/NDMA speed : 0aaarrrr
1512        Port 4B: IDE0 UDMA mode (default 00H)
1513                 bit7=0.
1514                 bit6-4 :slave-IDE UDMA MODE#
1515                 000 : disable UDMA
1516                 001 : UDMA mode 0
1517                 010 : UDMA mode 1
1518                 011 : UDMA mode 2
1519                 100 : UDMA mode 3
1520                 101 : UDMA mode 4
1521                 110 : UDMA mode 5
1522                 111 : UDMA mode 6
1523                 bit3=0.
1524                 bit2-0 :master-IDE UDMA MODE#
1525                 000 : disable UDMA
1526                 001 : UDMA mode 0
1527                 010 : UDMA mode 1
1528                 011 : UDMA mode 2
1529                 100 : UDMA mode 3
1530                 101 : UDMA mode 4
1531                 110 : UDMA mode 5
1532                 111 : UDMA mode 6
1533     */
1534     Outpb(baseIoAddress,0x48,0x31);
1535     Outpb(baseIoAddress,0x49,0x31);
1536     Outpb(baseIoAddress,0x4b,0x00);
1537     Outpb(baseIoAddress,0x58,0x31);
1538     Outpb(baseIoAddress,0x59,0x31);
1539     Outpb(baseIoAddress,0x5b,0x00);
1540     Outpb(baseIoAddress,0x68,0x31);
1541     Outpb(baseIoAddress,0x69,0x31);
1542     Outpb(baseIoAddress,0x6b,0x00);
1543     Outpb(baseIoAddress,0x78,0x31);
1544     Outpb(baseIoAddress,0x79,0x31);
1545     Outpb(baseIoAddress,0x7b,0x00);
1546     /*  cbuf[0]: UDMA mode value for port 0x4B  IDE0
1547         cbuf[1]: UDMA mode value for port 0x5B  IDE1
1548         cbuf[2]: UDMA mode value for port 0x6B  IDE2
1549         cbuf[3]: UDMA mode value for port 0x7B  IDE3
1550     */
1551     cbuf[0] = 0x00;
1552     cbuf[1] = 0x00;
1553     cbuf[2] = 0x00;
1554     cbuf[3] = 0x00;
1555
1556     /* Scan device for master/slave of 4 channels */
1557     for ( i = 0 ; i < 8 ; i++ )
1558     {
1559         /* j = out to 1X6 value , i=xx0: Master 0xA0 or i=xx1: Slave 0xB0 */
1560         baseIoAddress=devext->BaseIoAddress[i >> 1];
1561         j=0xa0;
1562         if ((i & 0x01) != 0)
1563         {
1564            j=0xb0;
1565         }
1566         Outpb(baseIoAddress,6,j);
1567         mdelay(10);
1568         /* k = in from 1X7 value */
1569         k=Inpb(baseIoAddress,7);
1570         if ((k & 0x88) != 0x00)
1571         {
1572            devext->hd_status[i]=0x7f;
1573            continue;
1574         }
1575         /* ATA Identify device command */
1576         Outpb(baseIoAddress,7,0xec);
1577         mdelay(400);
1578 wait_drq:
1579        l=Inpb(baseIoAddress,7);
1580        if ((l & 0x80) != 0 )
1581        {
1582           goto wait_drq;
1583        }
1584        if ((l & 0x01) == 0x01 )
1585        {
1586           devext->hd_status[i]=0x7f;
1587           continue;
1588        }
1589        if ((l & 0xf8) != 0x58 )
1590        {
1591           devext->hd_status[i]=0x7f;
1592           continue;
1593        }
1594        for (m=0; m < 0x100; m++)
1595        {
1596           mbuf[m]=Inpw(baseIoAddress,0);
1597        }
1598        /* Clear IRQ? */
1599         mdelay(1);
1600         k=Inpb(baseIoAddress,7);
1601        /* active_id = device exists */
1602        k=1;
1603        k=k<<i;
1604        devext->active_id |= k;
1605
1606        /* device type =0, capacity = word 60:61 (28-bit LBA) or word 100:101 (48-bit LBA) */
1607        devext->devtype[i]=0;
1608 #ifdef IXP42X_SUPPORT
1609        devext->cap[i] =  mbuf[61]<<16;
1610        devext->cap[i] |= mbuf[60];
1611 #else
1612        devext->cap[i]=((PULONG)&mbuf[60])[0];
1613 #endif
1614        if (devext->cap[i] == 0x0fffffff)
1615        {
1616           if ((mbuf[100] != 0) || (mbuf[101] != 0) ||
1617               (mbuf[102] != 0) || (mbuf[103] != 0))
1618           {
1619              devext->bigdrv[i]=1;
1620 #ifdef IXP42X_SUPPORT
1621              devext->cap[i] =  mbuf[101]<<16;
1622              devext->cap[i] |= mbuf[100];
1623 #else
1624              devext->cap[i]=((PULONG)&mbuf[100])[0];
1625 #endif
1626              r=((PULONG)&mbuf[102])[0];
1627              if (r != 0)
1628              {
1629                 devext->cap[i]=0xffffffff;
1630              }
1631           }
1632        }
1633        /* capacity -2??  why ??*/
1634        devext->cap[i] -= 2;
1635        /* fill inquiry data from byte 8 to byte 8+ 14*2 */
1636        k=4;
1637        for ( l=27; l < 41; l++ )
1638        {
1639            ((PUSHORT)&devext->inqdat[i][0])[k++]=(USHORT)((((PUCHAR)&mbuf[l])[0] << 8) | ((PUCHAR)&mbuf[l])[1]);
1640        }
1641        /* fill inquiry data from byte 0 to byte 7 */
1642 #ifdef  IXP42X_SUPPORT
1643        devext->inqdat[i][0]= 0x00;
1644        devext->inqdat[i][1]= 0x00;
1645        devext->inqdat[i][2]= 0x02;
1646        devext->inqdat[i][3]= 0x02;
1647        devext->inqdat[i][4]= 0x7D;
1648        devext->inqdat[i][5]= 0x00;
1649        devext->inqdat[i][6]= 0x00;
1650        devext->inqdat[i][7]= 0x32;
1651 #else
1652        ((PULONG)(&devext->inqdat[i][0]))[0]=0x02020000;
1653        ((PULONG)(&devext->inqdat[i][0]))[1]=0x3200007d;
1654 #endif
1655        devext->inqdat[i][36]=0;
1656        printk(KERN_INFO "         ID: %2d  %s     ", i, &devext->inqdat[i][8]);
1657 #ifndef DEBUG_UDMA
1658        printk("\n");
1659 #endif
1660        is66=0;
1661        iswd=0;
1662
1663 /* fill PIO/DMA/UDMA speed table and set feature to drive here */
1664
1665        /* 1X1 = 0x3  */
1666        Outpb(baseIoAddress,1,0x03);
1667        /* Identify device word 88:
1668                 F 15 Reserved
1669                 V 14 1 = Ultra DMA mode 6 is selected
1670                 0 = Ultra DMA mode 6 is not selected
1671                 V 13 1 = Ultra DMA mode 5 is selected
1672                 0 = Ultra DMA mode 5 is not selected
1673                 V 12 1 = Ultra DMA mode 4 is selected
1674                 0 = Ultra DMA mode 4 is not selected
1675                 V 11 1 = Ultra DMA mode 3 is selected
1676                 0 = Ultra DMA mode 3 is not selected
1677                 V 10 1 = Ultra DMA mode 2 is selected
1678                 0 = Ultra DMA mode 2 is not selected
1679                 V 9 1 = Ultra DMA mode 1 is selected
1680                 0 = Ultra DMA mode 1 is not selected
1681                 V 8 1 = Ultra DMA mode 0 is selected
1682                 0 = Ultra DMA mode 0 is not selected
1683                 F 7 Reserved
1684                 F 6 1 = Ultra DMA mode 6 and below are supported
1685                 F 5 1 = Ultra DMA mode 5 and below are supported
1686                 F 4 1 = Ultra DMA mode 4 and below are supported
1687                 F 3 1 = Ultra DMA mode 3 and below are supported
1688                 F 2 1 = Ultra DMA mode 2 and below are supported
1689                 F 1 1 = Ultra DMA mode 1 and below are supported
1690                 F 0 1 = Ultra DMA mode 0 is supported
1691        */
1692        if ((mbuf[88] & 0x0018) == 0)
1693        {
1694           if ((iswd == 0) && ((mbuf[88] & 0x007f) != 0))
1695           {
1696              /* UDMA mode 2 */
1697              Outpb(baseIoAddress,2,0x42);
1698 #ifdef DEBUG_UDMA
1699              printk("UDMA2 (33)\n");
1700 #endif
1701           }
1702           else
1703           {
1704 force_normdma:
1705              /* Multiword DMA mode 0-2 */
1706              k=(UCHAR)(mbuf[63] & 0x0007);
1707              k >>= 1;
1708              if (k > 2)
1709                 k=2;
1710 #ifdef DEBUG_UDMA
1711              printk("Mw-DMA %2X\n",k);
1712 #endif
1713              k |= 0x20;
1714              Outpb(baseIoAddress,2,k);
1715              iswd=1;
1716
1717           }
1718        }
1719        else
1720        {
1721           if ( iswd != 0 )
1722           {
1723              goto force_normdma;
1724           }
1725
1726           if (((i < 2) && ((ata66 & 0x01) == 0)) ||
1727               ((i > 1) && ((ata66 & 0x02) == 0)))
1728           {
1729              if ((mbuf[88] & 0x0020) == 0)
1730              {
1731                 /* UDMA mode 4 */
1732                 Outpb(baseIoAddress,2,0x44);
1733                 is66=1;
1734 #ifdef DEBUG_UDMA
1735                 printk("UDMA4 (66)\n");
1736 #endif
1737              }
1738              else
1739              {
1740                 /* UDMA mode 5 */
1741                 if ((mbuf[88] & 0x0040) == 0)
1742                 {
1743                    is66=2;
1744                    Outpb(baseIoAddress,2,0x45);
1745 #ifdef DEBUG_UDMA
1746                    printk("UDMA5 (100)\n");
1747 #endif
1748                 }
1749                 else
1750                 {
1751                 /* UDMA mode 6 */
1752                    is66=3;
1753                    Outpb(baseIoAddress,2,0x46);
1754 #ifdef DEBUG_UDMA
1755                    printk("UDMA6 (133)\n");
1756 #endif
1757                 }
1758              }
1759           }
1760           else
1761           {
1762              /* UDMA mode 2 */
1763              Outpb(baseIoAddress,2,0x42);
1764 #ifdef DEBUG_UDMA
1765              printk("UDMA2 (33)\n");
1766 #endif
1767           }
1768        }
1769        /* set feature  UDMA or NDMA mode */
1770        Outpb(baseIoAddress,7,0xef);
1771        mdelay(1000);
1772        k=Inpb(baseIoAddress,7);
1773        while ((k & 0x80) != 0)
1774        {
1775          k=Inpb(baseIoAddress,7);
1776        }
1777        if ((k & 0xf9) == 0x50)
1778        {
1779           if ( is66 == 0)
1780           {
1781             if ( iswd == 0 )
1782             {
1783                if ( i == 0 )
1784                {
1785                   cbuf[0] |= 0x03;
1786                }
1787                if ( i == 1 )
1788                {
1789                   cbuf[0] |= 0x30;
1790                }
1791                if ( i == 2 )
1792                {
1793                   cbuf[1] |= 0x03;
1794                }
1795                if ( i == 3 )
1796                {
1797                   cbuf[1] |= 0x30;
1798                }
1799                if ( i == 4 )
1800                {
1801                   cbuf[2] |= 0x03;
1802                }
1803                if ( i == 5 )
1804                {
1805                   cbuf[2] |= 0x30;
1806                }
1807                if ( i == 6 )
1808                {
1809                   cbuf[3] |= 0x03;
1810                }
1811                if ( i == 7 )
1812                {
1813                   cbuf[3] |= 0x30;
1814                }
1815             }
1816           }
1817           else
1818           {
1819              if ( i == 0 )
1820              {
1821                 if ( is66 == 1 )
1822                 {
1823                    cbuf[0] |= 0x05;
1824                 }
1825                 else
1826                 {
1827                    if ( is66 == 2 )
1828                       cbuf[0] |= 0x06;
1829                    else
1830                       cbuf[0] |= 0x07;
1831                 }
1832              }
1833              if ( i == 1 )
1834              {
1835                 if ( is66 == 1 )
1836                 {
1837                    cbuf[0] |= 0x50;
1838                 }
1839                 else
1840                 {
1841                    if ( is66 == 2 )
1842                       cbuf[0] |= 0x60;
1843                    else
1844                       cbuf[0] |= 0x70;
1845                 }
1846              }
1847              if ( i == 2 )
1848              {
1849                 if ( is66 == 1 )
1850                 {
1851                    cbuf[1] |= 0x05;
1852                 }
1853                 else
1854                 {
1855                    if ( is66 == 2 )
1856                       cbuf[1] |= 0x06;
1857                    else
1858                       cbuf[1] |= 0x07;
1859                 }
1860              }
1861              if ( i == 3 )
1862              {
1863                 if ( is66 == 1 )
1864                 {
1865                    cbuf[1] |= 0x50;
1866                 }
1867                 else
1868                 {
1869                    if ( is66 == 2 )
1870                       cbuf[1] |= 0x60;
1871                    else
1872                       cbuf[1] |= 0x70;
1873                 }
1874              }
1875              if ( i == 4 )
1876              {
1877                 if ( is66 == 1 )
1878                 {
1879                    cbuf[2] |= 0x05;
1880                 }
1881                 else
1882                 {
1883                    if ( is66 == 2 )
1884                       cbuf[2] |= 0x06;
1885                    else
1886                       cbuf[2] |= 0x07;
1887                 }
1888              }
1889              if ( i == 5 )
1890              {
1891                 if ( is66 == 1 )
1892                 {
1893                    cbuf[2] |= 0x50;
1894                 }
1895                 else
1896                 {
1897                    if ( is66 == 2 )
1898                       cbuf[2] |= 0x60;
1899                    else
1900                       cbuf[2] |= 0x70;
1901                 }
1902              }
1903              if ( i == 6 )
1904              {
1905                 if ( is66 == 1 )
1906                 {
1907                    cbuf[3] |= 0x05;
1908                 }
1909                 else
1910                 {
1911                    if ( is66 == 2 )
1912                       cbuf[3] |= 0x06;
1913                    else
1914                       cbuf[3] |= 0x07;
1915                 }
1916              }
1917              if ( i == 7 )
1918              {
1919                 if ( is66 == 1 )
1920                 {
1921                    cbuf[3] |= 0x50;
1922                 }
1923                 else
1924                 {
1925                    if ( is66 == 2 )
1926                       cbuf[3] |= 0x60;
1927                    else
1928                       cbuf[3] |= 0x70;
1929                 }
1930              }
1931           }
1932        }
1933     }
1934     baseIoAddress=devext->BaseIoAddress[0];
1935     Outpb(baseIoAddress,0x4b,cbuf[0]);
1936     Outpb(baseIoAddress,0x5b,cbuf[1]);
1937     Outpb(baseIoAddress,0x6b,cbuf[2]);
1938     Outpb(baseIoAddress,0x7b,cbuf[3]);
1939     return;
1940 }
1941
1942 void is865(struct hw_device_ext * devext,struct pci_dev *pdev)
1943 {
1944     ULONG baseIoAddress = devext->BaseIoAddress[0];
1945     ULONG  r;
1946     UCHAR  i,j,k,l,ata66,is66,iswd;
1947     UCHAR  cbuf[4];
1948     USHORT m,mbuf[256];
1949
1950     ata66=0x00;
1951     devext->ata66=ata66;
1952     /* config +40+00: IDE0 master DATA PIO/NDMA speed : 0aaarrrr
1953        config +40+01: IDE0 slave  DATA PIO/NDMA speed : 0aaarrrr
1954        config +40+02: IDE1 master DATA PIO/NDMA speed : 0aaarrrr
1955        config +40+03: IDE1 slave  DATA PIO/NDMA speed : 0aaarrrr
1956        config +40+04: IDE0 UDMA mode (default 00H)
1957        config +40+05: IDE1 UDMA mode (default 00H)
1958                 bit7=0.
1959                 bit6-4 :slave-IDE UDMA MODE#
1960                 000 : disable UDMA
1961                 001 : UDMA mode 0
1962                 010 : UDMA mode 1
1963                 011 : UDMA mode 2
1964                 100 : UDMA mode 3
1965                 101 : UDMA mode 4
1966                 110 : UDMA mode 5
1967                 bit3=0.
1968                 bit2-0 :master-IDE UDMA MODE#
1969                 000 : disable UDMA
1970                 001 : UDMA mode 0
1971                 010 : UDMA mode 1
1972                 011 : UDMA mode 2
1973                 100 : UDMA mode 3
1974                 101 : UDMA mode 4
1975                 110 : UDMA mode 5
1976     */
1977 #ifdef IS865_DEBUG
1978         printk("is865: write PIO/DMA speed: 40,41,42,43=0x31. 44,45 =0 \n");
1979 #endif
1980     pci_write_config_byte(pdev, 0x40, 0x31);
1981     pci_write_config_byte(pdev, 0x41, 0x31);
1982     pci_write_config_byte(pdev, 0x42, 0x31);
1983     pci_write_config_byte(pdev, 0x43, 0x31);
1984     pci_write_config_byte(pdev, 0x44, 0x00);
1985     pci_write_config_byte(pdev, 0x45, 0x00);
1986
1987     /*  cbuf[0]: UDMA mode value for port 0x4B  IDE0
1988         cbuf[1]: UDMA mode value for port 0x5B  IDE1
1989         cbuf[2]: UDMA mode value for port 0x6B  IDE2
1990         cbuf[3]: UDMA mode value for port 0x7B  IDE3
1991     */
1992     cbuf[0] = 0x00;
1993     cbuf[1] = 0x00;
1994     cbuf[2] = 0x00;
1995     cbuf[3] = 0x00;
1996 #ifdef IS865_DEBUG
1997         printk("is865: scan 4 devices of 2 channels\n");
1998 #endif
1999     /* Scan device for master/slave of 2 channels */
2000     for ( i = 0 ; i < 4 ; i++ )
2001     {
2002         /* j = out to 1X6 value , i=xx0: Master 0xA0 or i=xx1: Slave 0xB0 */
2003         if (i<2) baseIoAddress=devext->BaseIoAddress[0];
2004         else     baseIoAddress=devext->BaseIoAddress[1];
2005         j=0xa0;
2006         if ((i & 0x01) != 0)
2007         {
2008            j=0xb0;
2009         }
2010 #ifdef IS865_DEBUG
2011         printk("is865: i=%2X out %2X to port %4lX \n",i,j,(unsigned long)(baseIoAddress+6));
2012 #endif
2013         Outpb(baseIoAddress,6,j);
2014         mdelay(10);
2015         /* k = in from 1X7 value */
2016         k=Inpb(baseIoAddress,7);
2017 #ifdef IS865_DEBUG
2018         printk("is865: i=%2X in port %4lX  = %2X\n",i,(unsigned long)(baseIoAddress+7),k);
2019 #endif
2020         if ((k & 0x88) != 0x00)
2021         {
2022            devext->hd_status[i]=0x7f;
2023            devext->cap[i]=0;
2024            continue;
2025         }
2026 #ifdef IS865_DEBUG
2027         printk("is865: i=%2X out 0xEC to port %4lX \n",i,(unsigned long)(baseIoAddress+7));
2028 #endif
2029         /* ATA Identify device command */
2030         Outpb(baseIoAddress,7,0xec);
2031         mdelay(400);
2032 wait_drq:
2033        l=Inpb(baseIoAddress,7);
2034 #ifdef IS865_DEBUG
2035         printk("is865: i=%2X in port %4lX  = %2X\n",i,(unsigned long)(baseIoAddress+7),l);
2036 #endif
2037        if ((l & 0x80) != 0 )
2038        {
2039           goto wait_drq;
2040        }
2041        if ((l & 0x01) == 0x01 )
2042        {
2043           devext->hd_status[i]=0x7f;
2044           devext->cap[i]=0;
2045           continue;
2046        }
2047        if ((l & 0xf8) != 0x58 )
2048        {
2049           devext->hd_status[i]=0x7f;
2050           devext->cap[i]=0;
2051           continue;
2052        }
2053        for (m=0; m < 0x100; m++)
2054        {
2055           mbuf[m]=Inpw(baseIoAddress,0);
2056        }
2057        /* Clear IRQ? */
2058         mdelay(1);
2059         k=Inpb(baseIoAddress,7);
2060        /* active_id = device exists */
2061        k=1;
2062        k=k<<i;
2063        devext->active_id |= k;
2064 #ifdef IS865_DEBUG
2065         printk("is865: Check 512bytes identify data\n");
2066 #endif
2067        /* device type =0, capacity = word 60:61 (28-bit LBA) or word 100:101 (48-bit LBA) */
2068        devext->devtype[i]=0;
2069 #ifdef IXP42X_SUPPORT
2070        devext->cap[i] =  mbuf[61]<<16;
2071        devext->cap[i] |= mbuf[60];
2072 #else
2073        devext->cap[i]=((PULONG)&mbuf[60])[0];
2074 #endif
2075        if (devext->cap[i] == 0x0fffffff)
2076        {
2077           if ((mbuf[100] != 0) || (mbuf[101] != 0) ||
2078               (mbuf[102] != 0) || (mbuf[103] != 0))
2079           {
2080              devext->bigdrv[i]=1;
2081 #ifdef IXP42X_SUPPORT
2082              devext->cap[i] =  mbuf[101]<<16;
2083              devext->cap[i] |= mbuf[100];
2084 #else
2085              devext->cap[i]=((PULONG)&mbuf[100])[0];
2086 #endif
2087              r=((PULONG)&mbuf[102])[0];
2088              if (r != 0)
2089              {
2090                 devext->cap[i]=0xffffffff;
2091              }
2092           }
2093        }
2094        /* capacity -2??  why ??*/
2095        devext->cap[i] -= 2;
2096
2097 #ifdef IS865_DEBUG
2098         printk("is865: capacity[%2x] = %8lX\n",i,devext->cap[i]);
2099 #endif
2100        /* fill inquiry data from byte 8 to byte 8+ 14*2 */
2101        k=4;
2102        for ( l=27; l < 41; l++ )
2103        {
2104            ((PUSHORT)&devext->inqdat[i][0])[k++]=(USHORT)((((PUCHAR)&mbuf[l])[0] << 8) | ((PUCHAR)&mbuf[l])[1]);
2105        }
2106        /* fill inquiry data from byte 0 to byte 7 */
2107 #ifdef  IXP42X_SUPPORT
2108        devext->inqdat[i][0]= 0x00;
2109        devext->inqdat[i][1]= 0x00;
2110        devext->inqdat[i][2]= 0x02;
2111        devext->inqdat[i][3]= 0x02;
2112        devext->inqdat[i][4]= 0x7D;
2113        devext->inqdat[i][5]= 0x00;
2114        devext->inqdat[i][6]= 0x00;
2115        devext->inqdat[i][7]= 0x32;
2116 #else
2117        ((PULONG)(&devext->inqdat[i][0]))[0]=0x02020000;
2118        ((PULONG)(&devext->inqdat[i][0]))[1]=0x3200007d;
2119 #endif
2120        devext->inqdat[i][36]=0;
2121 //axl+
2122        devext->inqdat[i][37] = 0;
2123        devext->inqdat[i][38] = 0;
2124        if((mbuf[83] & 0x4000) == 0x4000)
2125        {
2126                if((mbuf[82] & 0x01) == 0x01)
2127                {
2128                         devext->inqdat[i][37] = 1;
2129                                 if((mbuf[85] & 0x01) == 0x01)
2130                                 {
2131                                         devext->inqdat[i][38] = 1;
2132                                 }
2133                }
2134        }
2135
2136         devext->SamwiseBaseIoAddress = baseIoAddress;
2137         devext->SamwiseHDSelect          = j;
2138 //       printk("\n %x %x", devext->SamwiseBaseIoAddress, devext->SamwiseHDSelect);
2139 //axl end
2140        printk(KERN_INFO "         ID: %2d  %s     ", i, &devext->inqdat[i][8]);
2141 #ifndef DEBUG_UDMA
2142        printk("\n");
2143 #endif
2144        is66=0;
2145        iswd=0;
2146
2147 /* fill PIO/DMA/UDMA speed table and set feature to drive here */
2148
2149        /* 1X1 = 0x3  */
2150        Outpb(baseIoAddress,1,0x03);
2151        /* Identify device word 88:
2152                 F 15 Reserved
2153                 V 14 1 = Ultra DMA mode 6 is selected
2154                 0 = Ultra DMA mode 6 is not selected
2155                 V 13 1 = Ultra DMA mode 5 is selected
2156                 0 = Ultra DMA mode 5 is not selected
2157                 V 12 1 = Ultra DMA mode 4 is selected
2158                 0 = Ultra DMA mode 4 is not selected
2159                 V 11 1 = Ultra DMA mode 3 is selected
2160                 0 = Ultra DMA mode 3 is not selected
2161                 V 10 1 = Ultra DMA mode 2 is selected
2162                 0 = Ultra DMA mode 2 is not selected
2163                 V 9 1 = Ultra DMA mode 1 is selected
2164                 0 = Ultra DMA mode 1 is not selected
2165                 V 8 1 = Ultra DMA mode 0 is selected
2166                 0 = Ultra DMA mode 0 is not selected
2167                 F 7 Reserved
2168                 F 6 1 = Ultra DMA mode 6 and below are supported
2169                 F 5 1 = Ultra DMA mode 5 and below are supported
2170                 F 4 1 = Ultra DMA mode 4 and below are supported
2171                 F 3 1 = Ultra DMA mode 3 and below are supported
2172                 F 2 1 = Ultra DMA mode 2 and below are supported
2173                 F 1 1 = Ultra DMA mode 1 and below are supported
2174                 F 0 1 = Ultra DMA mode 0 is supported
2175        */
2176        if ((mbuf[88] & 0x0018) == 0)
2177        {
2178           if ((iswd == 0) && ((mbuf[88] & 0x007f) != 0))
2179           {
2180              /* UDMA mode 2 */
2181              Outpb(baseIoAddress,2,0x42);
2182 #ifdef DEBUG_UDMA
2183              printk("UDMA2 (33)\n");
2184 #endif
2185           }
2186           else
2187           {
2188 force_normdma:
2189              /* Multiword DMA mode 0-2 */
2190              k=(UCHAR)(mbuf[63] & 0x0007);
2191              k >>= 1;
2192              if (k > 2)
2193                 k=2;
2194 #ifdef DEBUG_UDMA
2195              printk("MwDMA %2X\n",k);
2196 #endif
2197              k |= 0x20;
2198              Outpb(baseIoAddress,2,k);
2199              iswd=1;
2200           }
2201        }
2202        else
2203        {
2204           if ( iswd != 0 )
2205           {
2206              goto force_normdma;
2207           }
2208
2209           if (((i < 2) && ((ata66 & 0x01) == 0)) ||
2210               ((i > 1) && ((ata66 & 0x02) == 0)))
2211           {
2212              if ((mbuf[88] & 0x0020) == 0)
2213              {
2214                 /* UDMA mode 4 */
2215                 Outpb(baseIoAddress,2,0x44);
2216                 is66=1;
2217 #ifdef DEBUG_UDMA
2218                 printk("UDMA4 (66)\n");
2219 #endif
2220              }
2221              else
2222              {
2223                 /* UDMA mode 5 */
2224                 if ((devext->chipver <=3) || ((mbuf[88] & 0x0040) == 0))
2225                 {
2226                    is66=2;
2227                    Outpb(baseIoAddress,2,0x45);
2228 #ifdef DEBUG_UDMA
2229                    printk("UDMA5 (100)\n");
2230 #endif
2231                 }
2232                 else
2233                 {
2234                 /* UDMA mode 6 */
2235                    is66=3;
2236                    Outpb(baseIoAddress,2,0x46);
2237 #ifdef DEBUG_UDMA
2238                    printk("UDMA6 (133)\n");
2239 #endif
2240                 }
2241              }
2242           }
2243           else
2244           {
2245              /* UDMA mode 2 */
2246              Outpb(baseIoAddress,2,0x42);
2247 #ifdef DEBUG_UDMA
2248              printk("UDMA2 (33)\n");
2249 #endif
2250           }
2251        }
2252 #ifdef IS865_DEBUG
2253         printk("is865: Set Featur: enable UDMA or NDMA\n");
2254 #endif
2255        /* set feature  UDMA or NDMA mode */
2256        Outpb(baseIoAddress,7,0xef);
2257        mdelay(1000);
2258        k=Inpb(baseIoAddress,7);
2259        while ((k & 0x80) != 0)
2260        {
2261          k=Inpb(baseIoAddress,7);
2262        }
2263        if ((k & 0xf9) == 0x50)
2264        {
2265           if ( is66 == 0)
2266           {
2267             if ( iswd == 0 )
2268             {
2269                if ( i == 0 )
2270                {
2271                   cbuf[0] |= 0x03;
2272                }
2273                if ( i == 1 )
2274                {
2275                   cbuf[0] |= 0x30;
2276                }
2277                if ( i == 2 )
2278                {
2279                   cbuf[1] |= 0x03;
2280                }
2281                if ( i == 3 )
2282                {
2283                   cbuf[1] |= 0x30;
2284                }
2285             }
2286           }
2287           else
2288           {
2289              if ( i == 0 )
2290              {
2291                 if ( is66 == 1 )
2292                 {
2293                    cbuf[0] |= 0x05;
2294                 }
2295                 else
2296                 {
2297                    if ( is66 == 2 )
2298                       cbuf[0] |= 0x06;
2299                    else
2300                       cbuf[0] |= 0x07;
2301                 }
2302              }
2303              if ( i == 1 )
2304              {
2305                 if ( is66 == 1 )
2306                 {
2307                    cbuf[0] |= 0x50;
2308                 }
2309                 else
2310                 {
2311                    if ( is66 == 2 )
2312                       cbuf[0] |= 0x60;
2313                    else
2314                       cbuf[0] |= 0x70;
2315                 }
2316              }
2317              if ( i == 2 )
2318              {
2319                 if ( is66 == 1 )
2320                 {
2321                    cbuf[1] |= 0x05;
2322                 }
2323                 else
2324                 {
2325                    if ( is66 == 2 )
2326                       cbuf[1] |= 0x06;
2327                    else
2328                       cbuf[1] |= 0x07;
2329                 }
2330              }
2331              if ( i == 3 )
2332              {
2333                 if ( is66 == 1 )
2334                 {
2335                    cbuf[1] |= 0x50;
2336                 }
2337                 else
2338                 {
2339                    if ( is66 == 2 )
2340                       cbuf[1] |= 0x60;
2341                    else
2342                       cbuf[1] |= 0x70;
2343                 }
2344              }
2345           }
2346        }
2347     }
2348 #ifdef IS865_DEBUG
2349         printk("is865: End : enable UDMA 44= %2x ,45= %2x \n",cbuf[0],cbuf[1]);
2350 #endif
2351     pci_write_config_byte(pdev, 0x44, cbuf[0]);
2352     pci_write_config_byte(pdev, 0x45, cbuf[1]);
2353     return;
2354
2355
2356 }
2357
2358 /* return non-zero on detection */
2359 int atp86x_detect(Scsi_Host_Template * tpnt)
2360 {
2361         UCHAR irq, h;
2362         ULONG long flags;
2363         ULONG baseIoAddress;
2364         unsigned int base_io, error;
2365         USHORT index = 0;
2366         struct pci_dev *pdev[5];
2367         UCHAR chip_ver[5];
2368         USHORT dev_id[5];
2369         struct Scsi_Host *shpnt = NULL;
2370         struct hw_device_ext *devext;
2371         int tmpcnt = 0;
2372         int count = 0;
2373         ULONG  k;
2374         UCHAR  j;
2375 #ifdef I2C_ENABLE
2376         USHORT t;
2377         UCHAR  n,l;
2378 #endif
2379
2380         static USHORT devid[4] = { ATP865_DEVID1,ATP865_DEVID2,ATP867_DEVID1, 0};
2381         static UCHAR page0[16]={0x0d,0,0,8,0,0,0,0,0,0,2,0,0,0,0,0};
2382         static UCHAR page1[24]={0x17,0,0,8,0,0,0,0,0,0,2,0,0x81,0x0a,0xc0,0x08,0x18,0x0a,0,0,0,0,0,0};
2383         static UCHAR page1c[24]={0x17,0,0,8,0,0,0,0,0,0,2,0,0x9c,0x0a,0,3,0,0,0,0,0,0,0,1};
2384
2385
2386         printk(KERN_INFO "atp86x_detect: \n");
2387         if (!pci_present()) {
2388                 printk(KERN_INFO"   NO PCI SUPPORT.\n");
2389                 return count;
2390         }
2391         tpnt->proc_name = "atp86x";
2392
2393         for (h = 0; h < 4; h++) {
2394             devext = &dev_ext[h];
2395             for (k=0; k < sizeof(struct hw_device_ext); k++) {
2396                 ((PUCHAR)devext)[k] = 0;
2397             }
2398
2399             devext->host_id = 0x08;
2400
2401             for (k=0; k < 8 ; k++) {
2402                 devext->devtype[k] = 0x7f;
2403             }
2404
2405             for (k=0; k < 16 ; k++) {
2406                 devext->page0[k]=page0[k];
2407             }
2408             for (k=0; k < 24 ; k++) {
2409                 devext->page1[k]=page1[k];
2410                 devext->page1c[k]=page1c[k];
2411             }
2412             for (j=0; j < 8; j++)
2413             {
2414                 for (k=0; k < 16 ; k++) {
2415                         devext->sensd[j][k]=0x0;
2416                 }
2417                 devext->dskerr_LBA[j]=0;
2418             }
2419 /*
2420             for (j=0; j < 4; j++)
2421             {
2422                 for (k=0; k < qcnt1; k++)
2423                 {
2424                     devext->plsrb[j][k]=&devext->lsrb[j][k];
2425 #ifdef IXP42X_SUPPORT
2426 //                  devext->lsrb[j][k].prd = kmalloc(256, GFP_ATOMIC|GFP_DMA);
2427                     devext->lsrb[j][k].prd = pci_alloc_consistent(hwif->pci_dev,
2428                                                   256,
2429                                                   &(devext->lsrb[j][k].prdaddr));
2430
2431 #else
2432                     devext->lsrb[j][k].prd = kmalloc(256, GFP_KERNEL);
2433                     devext->lsrb[j][k].prdaddr=(ULONG)virt_to_bus(devext->lsrb[j][k].prd);
2434 #endif
2435                 }
2436             }
2437 */
2438             pdev[h]=NULL;
2439             pdev[4]=NULL;
2440         }
2441         h = 0;
2442         while (devid[h] != 0) {
2443                 pdev[4] = pci_find_device(0x1191, devid[h], pdev[4]);
2444                 if (pdev[4] == NULL || pci_enable_device(pdev[4])) {
2445                         h++;
2446                         index = 0;
2447                         continue;
2448                 }
2449                 dev_id[4] = devid[h];
2450                 chip_ver[4] = 0;
2451                 error = pci_read_config_byte(pdev[4], 0x08, &chip_ver[4]);
2452 //              printk("Chip version = %2X\n",chip_ver[4]);
2453 //              pci_write_config_byte(pdev[4], 0x0D, 22);
2454                 pci_write_config_byte(pdev[4], 0x0D, 0x80);//JCC082803
2455                 pdev[tmpcnt] = pdev[4];
2456                 chip_ver[tmpcnt] = chip_ver[4];
2457                 dev_id[tmpcnt] = dev_id[4];
2458                 tmpcnt++;
2459                 index++;
2460                 if (index > 3) {
2461                         index = 0;
2462                         h++;
2463                 }
2464                 if(tmpcnt>3)
2465                         break;
2466         }
2467         for (h = 0; h < 4; h++) {
2468                 devext = &dev_ext[h];
2469                 if (pdev[h]==NULL) {
2470                         return count;
2471                 }
2472                 devext->pdev=pdev[h];
2473                 for (j=0; j < 4; j++)
2474                 {
2475                         for (k=0; k < qcnt1; k++)
2476                         {
2477                                 devext->plsrb[j][k]=&devext->lsrb[j][k];
2478 #ifdef IXP42X_SUPPORT
2479 //                              devext->lsrb[j][k].prd = kmalloc(256, GFP_ATOMIC|GFP_DMA);
2480                                 devext->lsrb[j][k].prd = pci_alloc_consistent(pdev[h],
2481                                                                  256,  &(devext->lsrb[j][k].prdaddr));
2482 #else
2483                                 devext->lsrb[j][k].prd = kmalloc(256, GFP_KERNEL);
2484                                 devext->lsrb[j][k].prdaddr=(ULONG)virt_to_bus(devext->lsrb[j][k].prd);
2485 #endif
2486                         }
2487                 }
2488                 /* Found an atp86x */
2489
2490                 base_io = pci_resource_start(pdev[h], 0);
2491                 irq = pdev[h]->irq;
2492
2493                 base_io &= 0xfffffff8;
2494 //#ifdef DETECT_DEBUG
2495 //              printk("atp86x:  dev_id[%d] = %X  base_io =  %X .\n",h, dev_id[h], base_io);
2496 //#endif
2497                 if (dev_id[h] ==0x0A)
2498                 {
2499                         if (check_region(base_io,0x80) != 0)
2500                         {
2501                                 return 0;
2502                         }
2503
2504                         printk(KERN_INFO "   ACARD ATP-867 PCI ATA133 4-Channels Host Adapter: %d    IO:%X, IRQ:%d.\n"
2505                                 ,h, base_io, irq);
2506                         devext->pdev = pdev[h];
2507                         devext->chipver = chip_ver[h];
2508 //                      printk("Chip version = %2X\n",devext->chipver);
2509                         devext->dev_id  = dev_id[h];
2510                         devext->BaseIoAddress[0] = base_io;
2511                         devext->BaseIoAddress[1] = base_io + 0x10;
2512                         devext->BaseIoAddress[2] = base_io + 0x20;
2513                         devext->BaseIoAddress[3] = base_io + 0x30;
2514                         devext->BaseIoAddresm[0] = base_io + 0x40;
2515                         devext->BaseIoAddresm[1] = base_io + 0x50;
2516                         devext->BaseIoAddresm[2] = base_io + 0x60;
2517                         devext->BaseIoAddresm[3] = base_io + 0x70;
2518                 }
2519                 else
2520                 {
2521                         devext->pdev = pdev[h];
2522                         devext->dev_id  = dev_id[h];
2523                         devext->chipver = chip_ver[h];
2524
2525                         if (check_region(base_io,0x8) != 0)
2526                         {
2527                                 return 0;
2528                         }
2529                         printk(KERN_INFO "   ACARD ATP-865 PCI ATA133 2-Channels Host Adapter: %d    IO:%X, IRQ:%d.\n"
2530                                 ,h, base_io, irq);
2531 //                      printk("Chip version = %2X\n",devext->chipver);
2532                         devext->BaseIoAddress[0] = base_io;
2533                         base_io = pci_resource_start(pdev[h],1);
2534 #ifdef DETECT_DEBUG
2535                         printk("atp865:  dev_id[%d] = %04X  base_io 1 =  %04X .\n",h, dev_id[h], base_io);
2536 #endif
2537                         if (check_region(base_io,0x3) != 0)
2538                         {
2539                                 return 0;
2540                         }
2541                         devext->BaseIoAddress[2] = base_io +2;
2542                         base_io = pci_resource_start(pdev[h],2);
2543 #ifdef DETECT_DEBUG
2544                         printk("atp865:  dev_id[%d] = %04X  base_io 2 =  %04X .\n",h, dev_id[h], base_io);
2545 #endif
2546                         if (check_region(base_io,0x8) != 0)
2547                         {
2548                                 return 0;
2549                         }
2550                         devext->BaseIoAddress[1] = base_io ;
2551                         base_io = pci_resource_start(pdev[h],3);
2552 #ifdef DETECT_DEBUG
2553                         printk("atp865:  dev_id[%d] = %04X  base_io 3 =  %04X .\n",h, dev_id[h], base_io);
2554 #endif
2555                         if (check_region(base_io,0x3) != 0)
2556                         {
2557                                 return 0;
2558                         }
2559                         devext->BaseIoAddress[3] = base_io +2;
2560                         base_io = pci_resource_start(pdev[h],4);
2561 #ifdef DETECT_DEBUG
2562                         printk("atp865:  dev_id[%d] = %04X  base_io 4 =  %04X .\n",h, dev_id[h], base_io);
2563 #endif
2564                         if (check_region(base_io,0x10) != 0)
2565                         {
2566                                 return 0;
2567                         }
2568                         devext->BaseIoAddresm[0] = base_io ;
2569                         devext->BaseIoAddresm[1] = base_io + 0x08;
2570                         devext->BaseIoAddresm[2] = base_io + 0x02;
2571                         devext->BaseIoAddresm[3] = base_io + 0x0A;
2572                 }
2573                 devext->irq = irq;
2574                 irqnumu[h] = irq;
2575
2576                 shpnt = scsi_register(tpnt, 4);
2577                 if(shpnt==NULL)
2578                 {
2579                         printk(KERN_INFO "scsi_register failure!!\n");
2580                         return count;
2581                 }
2582
2583                 save_flags(flags);
2584                 cli();
2585                 if (request_irq(irq, atp86x_intr_handle, SA_SHIRQ, "atp86x", devext)) {
2586                         printk(KERN_ERR "Unable to allocate IRQ for Acard controller.\n");
2587                         goto unregister;
2588                 }
2589
2590                 if (dev_id[h] ==0x0A)
2591                 {
2592 #ifdef DETECT_DEBUG
2593                         printk("atp867: Out 0x10 to port 0x28 \n");
2594 #endif
2595                         j=Inpb(base_io,0x28);
2596                         j |= 0x10;
2597                         Outpb(base_io,0x28,j);
2598 #ifdef DETECT_DEBUG
2599                         printk("atp867: is867 enter \n");
2600 #endif
2601                         is867(devext);
2602 #ifdef DETECT_DEBUG
2603                         printk("atp867: is867 exit \n");
2604                         printk("atp867: clear bit4,5 and set bit 6,7 to port 0x28 \n");
2605 #endif
2606                         j=Inpb(base_io,0x28);
2607                         j &= 0xcf;
2608                         j |= 0xc0;
2609                         Outpb(base_io,0x28,j);
2610 #ifdef DETECT_DEBUG
2611                         printk("atp867: clear bit0-3 to port 0x29 \n");
2612 #endif
2613                         baseIoAddress = devext->BaseIoAddress[0];
2614                         Outpb(baseIoAddress,0x29,(UCHAR)
2615                                 (Inpb(baseIoAddress,0x29) & 0xe0));
2616 #ifdef I2C_ENABLE
2617 #ifdef DETECT_DEBUG
2618                         printk("atp867: I2C init \n");
2619 #endif
2620                         for (t=0; t < 4; t++)
2621                         {
2622                                 baseIoAddress = devext->BaseIoAddress[t];
2623                                 j=0;
2624                                 n=0;
2625                                 l=0;
2626                                 Outpb(baseIoAddress,0x0e,0x08);
2627                                 i2cwrite(baseIoAddress,0x4e,0x80);
2628                                 i2cread(baseIoAddress,0x4f,&j);
2629                                 i2cwrite(baseIoAddress,0x4e,0x00);
2630                                 i2cread(baseIoAddress,0x4f,&n);
2631                                 i2cread(baseIoAddress,0x58,&l);
2632                                 if ((j == 0x5c) && (n == 0xa3) && (l == 0x40))
2633                                 {
2634                                         j=0x10;
2635                                         j <<= t;
2636                                         devext->c_mask |= j;
2637                                         i2cread(baseIoAddress,0x41,&j);
2638                                         i2cread(baseIoAddress,0x42,&j);
2639                                         i2cwrite(baseIoAddress,0x43,0xf8);
2640                                         i2cwrite(baseIoAddress,0x44,0x0e);
2641                                         i2cwrite(baseIoAddress,0x2b,0xff);
2642                                         i2cwrite(baseIoAddress,0x2c,0x3e);
2643                                         i2cwrite(baseIoAddress,0x2f,0xff);
2644                                         i2cwrite(baseIoAddress,0x30,0x3e);
2645                                         i2cwrite(baseIoAddress,0x33,0xff);
2646                                         i2cwrite(baseIoAddress,0x34,0x3e);
2647                                         i2cwrite(baseIoAddress,0x4d,0xc0);
2648                                         i2cread(baseIoAddress,0x40,&j);
2649                                         i2cread(baseIoAddress,0x41,&j);
2650                                         i2cread(baseIoAddress,0x42,&j);
2651                                         i2cread(baseIoAddress,0x43,&j);
2652                                         i2cread(baseIoAddress,0x44,&j);
2653                                         i2cread(baseIoAddress,0x2b,&j);
2654                                         i2cread(baseIoAddress,0x2c,&j);
2655                                         i2cread(baseIoAddress,0x2f,&j);
2656                                         i2cread(baseIoAddress,0x30,&j);
2657                                         i2cread(baseIoAddress,0x33,&j);
2658                                         i2cread(baseIoAddress,0x34,&j);
2659                                         i2cread(baseIoAddress,0x4d,&j);
2660                                         i2cwrite(baseIoAddress,0x40,0x43);
2661                                         Outpb(baseIoAddress,0x0e,0x08);
2662                                         i2cread(baseIoAddress,0x41,&j);
2663                                         i2cread(baseIoAddress,0x42,&j);
2664                                         if (devext->hd_status[t << 1] == 0)
2665                                         {
2666                                                 Outpb(baseIoAddress,0x43,0x84);
2667                                         }
2668                                         else
2669                                         {
2670                                                 Outpb(baseIoAddress,0x43,0x80);
2671                                         }
2672                                         Outpb(baseIoAddress,0x0e,0x08);
2673                                         Outpb(baseIoAddress,0x43,0x20);
2674                                         baseIoAddress = devext->BaseIoAddress[0];
2675                                         Outpb(baseIoAddress,0x29,(UCHAR)
2676                                                 (Inpb(baseIoAddress,0x29) | 0x10));
2677                                 }
2678                         }
2679 #endif
2680                         baseIoAddress = devext->BaseIoAddress[0];
2681 #ifdef DETECT_DEBUG
2682                         printk("atp867: Out 0x06 to port 0x42,0x52,0x62,0x72\n");
2683 #endif
2684                         Outpb(base_io,0x42,0x06);
2685                         Outpb(base_io,0x52,0x06);
2686                         Outpb(base_io,0x62,0x06);
2687                         Outpb(base_io,0x72,0x06);
2688                 }
2689                 else  // of device_id = 0x0A
2690                 {
2691 #ifdef DETECT_DEBUG
2692                         printk("atp865: scan device start here\n");
2693 #endif
2694
2695                         /*  PCI config + 0x40 + 0xA:    bit 0: 1= disable INTA  */
2696 #ifdef DETECT_DEBUG
2697                         printk("atp865: read config + 0x4A\n");
2698 #endif
2699                         pci_read_config_byte(pdev[h], 0x4A, &j);
2700 #ifdef DETECT_DEBUG
2701                         printk("atp865: read config + 0x4A = %X\n",j);
2702 #endif
2703                         j |= 0x01;
2704                         pci_write_config_byte(pdev[h], 0x4A, j);
2705 #ifdef DETECT_DEBUG
2706                         printk("atp865: write config + 0x4A = %X\n",j);
2707 #endif
2708                         is865(devext,pdev[h]);
2709 ////                    ATP865init(devext);
2710                         /*  PCI config + 0x40 + 0xA:    bit 0: 0= enable INTA
2711                                                         bit 7: 1= enable PCI bus master
2712                         */
2713 #ifdef DETECT_DEBUG
2714                         printk("atp865: read config + 0x4A\n");
2715 #endif
2716                         pci_read_config_byte(pdev[h], 0x4A, &j);
2717 #ifdef DETECT_DEBUG
2718                         printk("atp865: read config + 0x4A = %X\n",j);
2719 #endif
2720                         j &= 0xfe;
2721                         j |= 0x88;
2722                         pci_write_config_byte(pdev[h], 0x4A, j);
2723 #ifdef DETECT_DEBUG
2724                         printk("atp865: write config + 0x4A = %X\n",j);
2725 #endif
2726                         /* disable pre-read or post write ,  delayed IRQ */
2727                         pci_write_config_byte(pdev[h], 0x4B, 0);
2728 #ifdef DETECT_DEBUG
2729                         printk("atp865: write config + 0x4B = 0\n");
2730 #endif
2731                         /* Pre-read counter must be 0x000200  4C,4D,4E - 14,15,16*/
2732                         pci_write_config_byte(pdev[h], 0x4C, 0);
2733 #ifdef DETECT_DEBUG
2734                         printk("atp865: write config + 0x4C = 0\n");
2735 #endif
2736                         pci_write_config_byte(pdev[h], 0x4D, 0x02);
2737 #ifdef DETECT_DEBUG
2738                         printk("atp865: write config + 0x4D = 0x02\n");
2739 #endif
2740                         pci_write_config_byte(pdev[h], 0x4E, 0);
2741 #ifdef DETECT_DEBUG
2742                         printk("atp865: write config + 0x4E = 0\n");
2743 #endif
2744                         pci_write_config_byte(pdev[h], 0x14, 0);
2745 #ifdef DETECT_DEBUG
2746                         printk("atp865: write config + 0x14 = 0\n");
2747 #endif
2748                         pci_write_config_byte(pdev[h], 0x15, 0x02);
2749 #ifdef DETECT_DEBUG
2750                         printk("atp865: write config + 0x15 = 0x02\n");
2751 #endif
2752                         pci_write_config_byte(pdev[h], 0x16, 0);
2753 #ifdef DETECT_DEBUG
2754                         printk("atp865: write config + 0x16 = 0\n");
2755 #endif
2756
2757                         baseIoAddress = devext->BaseIoAddress[0];
2758
2759                         /* Clear Latched IRQ bit and DMA error bit for each channel */
2760                         /* set both drives DMA mode for each channel? */
2761                         base_io = devext->BaseIoAddresm[0];
2762 #ifdef DETECT_DEBUG
2763                         printk("atp865: write io= %X , 0x66\n", base_io+0x2);
2764                         printk("atp865: write io= %X , 0x66\n", base_io+0xA);
2765 #endif
2766                         Outpb(base_io,0x2,0x66);
2767                         Outpb(base_io,0xA,0x66);
2768 #ifdef DETECT_DEBUG
2769                         printk("atp865: scan device end here\n");
2770 #endif
2771                 }
2772
2773                 a867host[h] = shpnt;
2774                 shpnt->max_id = 9;
2775                 shpnt->this_id = 0x08;
2776                 shpnt->unique_id = base_io;
2777                 shpnt->io_port = base_io;
2778                 shpnt->n_io_port = 0x80;        /* Number of bytes of I/O space used */
2779                 shpnt->irq = irq;
2780                 restore_flags(flags);
2781                 if (dev_id[h] ==0x0A)
2782                 {
2783 #ifdef DETECT_DEBUG
2784                         printk("atp867: request region: base_io , 0x80\n");
2785 #endif
2786                         request_region(base_io, 0x80, "atp86x"); /* Register the IO ports that we use */
2787                 }
2788                 else
2789                 {
2790 #ifdef DETECT_DEBUG
2791                         printk("atp865: request region: devext->BaseIoAddress[0] , 0x8\n");
2792 #endif
2793                         request_region(devext->BaseIoAddress[0], 0x8, "atp86x"); /* Register the IO ports that we use */
2794 #ifdef DETECT_DEBUG
2795                         printk("atp865: request region: devext->BaseIoAddress[1] , 0x3\n");
2796 #endif
2797                         request_region(devext->BaseIoAddress[2], 0x3, "atp86x"); /* Register the IO ports that we use */
2798 #ifdef DETECT_DEBUG
2799                         printk("atp865: request region: devext->BaseIoAddress[2] , 0x8\n");
2800 #endif
2801                         request_region(devext->BaseIoAddress[1], 0x8, "atp86x"); /* Register the IO ports that we use */
2802 #ifdef DETECT_DEBUG
2803                         printk("atp865: request region: devext->BaseIoAddress[3] , 0x3\n");
2804 #endif
2805                         request_region(devext->BaseIoAddress[3], 0x3, "atp86x"); /* Register the IO ports that we use */
2806 #ifdef DETECT_DEBUG
2807                         printk("atp865: request region: devext->BaseIoAddresm[0] , 0x10\n");
2808 #endif
2809                         request_region(devext->BaseIoAddresm[0], 0x10, "atp86x"); /* Register the IO ports that we use */
2810
2811                 }
2812 // add for smart read  =================//
2813         init_timer(&(devext->AdapterTimer));
2814         (devext->AdapterTimer).expires  = jiffies + 100;         // active per second
2815         (devext->AdapterTimer).data             = (ULONG)(devext);
2816         (devext->AdapterTimer).function = smart_timer;
2817         add_timer(&(devext->AdapterTimer));
2818 //======================================//
2819                 count++;
2820                 index++;
2821                 continue;
2822 unregister:
2823                 scsi_unregister(shpnt);
2824                 restore_flags(flags);
2825                 index++;
2826                 continue;
2827         }
2828
2829         return count;
2830 }
2831
2832 #ifdef I2C_ENABLE
2833
2834 int i2cwrite(ULONG baseIoAddress, UCHAR Rindex, UCHAR Rval)
2835 {
2836        UCHAR    i,j,k,l;
2837
2838        Outpb(baseIoAddress,0x43,0x81);
2839        mdelay(0x10);
2840        j=0x81;
2841        k=0x5a;
2842        for (i=0; i < 8; i++)
2843        {
2844         j &= 0xfe;
2845         Outpb(baseIoAddress,0x43,j);
2846         mdelay(0x10);
2847         j &= 0xfd;
2848         if ((k & 0x80) != 0)
2849         {
2850            j |= 0x02;
2851         }
2852         k <<= 0x01;
2853         Outpb(baseIoAddress,0x43,j);
2854         mdelay(0x10);
2855         j |= 0x01;
2856         Outpb(baseIoAddress,0x43,j);
2857         mdelay(0x10);
2858        }
2859        j &= 0xfe;
2860        Outpb(baseIoAddress,0x43,j);
2861        mdelay(0x10);
2862        j |= 0x02;
2863        Outpb(baseIoAddress,0x43,j);
2864        j |= 0x01;
2865        Outpb(baseIoAddress,0x43,j);
2866        mdelay(0x10);
2867        l=Inpb(baseIoAddress,0x43);
2868        j &= 0xfe;
2869        Outpb(baseIoAddress,0x43,j);
2870        mdelay(0x10);
2871        if ((l & 0x02) != 0)
2872        {
2873           Outpb(baseIoAddress,0x43,1);
2874           return FALSE;
2875        }
2876        for (i=0; i < 8; i++)
2877        {
2878         j &= 0xfd;
2879         if ((Rindex & 0x80) != 0)
2880         {
2881            j |= 0x02;
2882         }
2883         Rindex <<= 0x01;
2884         Outpb(baseIoAddress,0x43,j);
2885         mdelay(0x10);
2886         j |= 0x01;
2887         Outpb(baseIoAddress,0x43,j);
2888         mdelay(0x10);
2889         j &= 0xfe;
2890         Outpb(baseIoAddress,0x43,j);
2891         mdelay(0x10);
2892        }
2893        j |= 0x02;
2894        Outpb(baseIoAddress,0x43,j);
2895        j |= 0x01;
2896        Outpb(baseIoAddress,0x43,j);
2897        mdelay(0x10);
2898        l=Inpb(baseIoAddress,0x43);
2899        j &= 0xfe;
2900        Outpb(baseIoAddress,0x43,j);
2901        mdelay(0x10);
2902        if ((l & 0x02) != 0)
2903        {
2904           Outpb(baseIoAddress,0x43,1);
2905           return FALSE;
2906        }
2907        for (i=0; i < 8; i++)
2908        {
2909         j &= 0xfd;
2910         if ((Rval & 0x80) != 0)
2911         {
2912            j |= 0x02;
2913         }
2914         Rval <<= 0x01;
2915         Outpb(baseIoAddress,0x43,j);
2916         mdelay(0x10);
2917         j |= 0x01;
2918         Outpb(baseIoAddress,0x43,j);
2919         mdelay(0x10);
2920         j &= 0xfe;
2921         Outpb(baseIoAddress,0x43,j);
2922         mdelay(0x10);
2923        }
2924        j |= 0x02;
2925        Outpb(baseIoAddress,0x43,j);
2926        j |= 0x01;
2927        Outpb(baseIoAddress,0x43,j);
2928        mdelay(0x10);
2929        l=Inpb(baseIoAddress,0x43);
2930        j &= 0xfe;
2931        Outpb(baseIoAddress,0x43,j);
2932        mdelay(0x10);
2933        Outpb(baseIoAddress,0x43,1);
2934        if ((l & 0x02) != 0)
2935        {
2936           return FALSE;
2937        }
2938        return TRUE;
2939 }
2940
2941 int i2cread(ULONG baseIoAddress, UCHAR Rindex, PUCHAR Rval)
2942 {
2943        UCHAR    i,j,k,l;
2944
2945        Outpb(baseIoAddress,0x43,0x81);
2946        mdelay(0x10);
2947        j=0x81;
2948        k=0x5a;
2949        for (i=0; i < 8; i++)
2950        {
2951         j &= 0xfe;
2952         Outpb(baseIoAddress,0x43,j);
2953         mdelay(0x10);
2954         j &= 0xfd;
2955         if ((k & 0x80) != 0)
2956         {
2957            j |= 0x02;
2958         }
2959         k <<= 0x01;
2960         Outpb(baseIoAddress,0x43,j);
2961         mdelay(0x10);
2962         j |= 0x01;
2963         Outpb(baseIoAddress,0x43,j);
2964         mdelay(0x10);
2965        }
2966        j &= 0xfe;
2967        Outpb(baseIoAddress,0x43,j);
2968        mdelay(0x10);
2969        j |= 0x02;
2970        Outpb(baseIoAddress,0x43,j);
2971        j |= 0x01;
2972        Outpb(baseIoAddress,0x43,j);
2973        mdelay(0x10);
2974        l=Inpb(baseIoAddress,0x43);
2975        j &= 0xfe;
2976        Outpb(baseIoAddress,0x43,j);
2977        mdelay(0x10);
2978        if ((l & 0x02) != 0)
2979        {
2980           Outpb(baseIoAddress,0x43,1);
2981           return FALSE;
2982        }
2983        for (i=0; i < 8; i++)
2984        {
2985         j &= 0xfd;
2986         if ((Rindex & 0x80) != 0)
2987         {
2988            j |= 0x02;
2989         }
2990         Rindex <<= 0x01;
2991         Outpb(baseIoAddress,0x43,j);
2992         mdelay(0x10);
2993         j |= 0x01;
2994         Outpb(baseIoAddress,0x43,j);
2995         mdelay(0x10);
2996         j &= 0xfe;
2997         Outpb(baseIoAddress,0x43,j);
2998         mdelay(0x10);
2999        }
3000        j |= 0x02;
3001        Outpb(baseIoAddress,0x43,j);
3002        j |= 0x01;
3003        Outpb(baseIoAddress,0x43,j);
3004        mdelay(0x10);
3005        l=Inpb(baseIoAddress,0x43);
3006        j &= 0xfe;
3007        Outpb(baseIoAddress,0x43,j);
3008        mdelay(0x10);
3009        j |= 0x01;
3010        Outpb(baseIoAddress,0x43,j);
3011        mdelay(0x10);
3012        if ((l & 0x02) != 0)
3013        {
3014           Outpb(baseIoAddress,0x43,1);
3015           return FALSE;
3016        }
3017
3018        Outpb(baseIoAddress,0x43,0x81);
3019        mdelay(0x10);
3020        j=0x81;
3021        k=0x5b;
3022        for (i=0; i < 8; i++)
3023        {
3024         j &= 0xfe;
3025         Outpb(baseIoAddress,0x43,j);
3026         mdelay(0x10);
3027         j &= 0xfd;
3028         if ((k & 0x80) != 0)
3029         {
3030            j |= 0x02;
3031         }
3032         k <<= 0x01;
3033         Outpb(baseIoAddress,0x43,j);
3034         mdelay(0x10);
3035         j |= 0x01;
3036         Outpb(baseIoAddress,0x43,j);
3037         mdelay(0x10);
3038        }
3039        j &= 0xfe;
3040        Outpb(baseIoAddress,0x43,j);
3041        mdelay(0x10);
3042        j |= 0x02;
3043        Outpb(baseIoAddress,0x43,j);
3044        j |= 0x01;
3045        Outpb(baseIoAddress,0x43,j);
3046        mdelay(0x10);
3047        l=Inpb(baseIoAddress,0x43);
3048        j &= 0xfe;
3049        Outpb(baseIoAddress,0x43,j);
3050        mdelay(0x10);
3051        if ((l & 0x02) != 0)
3052        {
3053           Outpb(baseIoAddress,0x43,1);
3054           return FALSE;
3055        }
3056        *Rval=0;
3057        for (i=0; i < 8; i++)
3058        {
3059         *Rval <<= 0x01;
3060         j |= 0x01;
3061         Outpb(baseIoAddress,0x43,j);
3062         mdelay(0x10);
3063         l=Inpb(baseIoAddress,0x43);
3064         if ((l & 0x02) != 0)
3065         {
3066            *Rval |= 0x01;
3067         }
3068         j &= 0xfe;
3069         Outpb(baseIoAddress,0x43,j);
3070         mdelay(0x10);
3071        }
3072        j |= 0x01;
3073        Outpb(baseIoAddress,0x43,j);
3074        mdelay(0x10);
3075        j &= 0xfd;
3076        Outpb(baseIoAddress,0x43,j);
3077        mdelay(0x10);
3078        j &= 0xfe;
3079        Outpb(baseIoAddress,0x43,j);
3080        mdelay(0x10);
3081        j |= 0x01;
3082        Outpb(baseIoAddress,0x43,j);
3083        mdelay(0x10);
3084        j |= 0x02;
3085        Outpb(baseIoAddress,0x43,j);
3086        mdelay(0x10);
3087        j &= 0xfe;
3088        Outpb(baseIoAddress,0x43,j);
3089        Outpb(baseIoAddress,0x43,1);
3090        return TRUE;
3091 }
3092 #endif
3093
3094 /* The abort command does not leave the device in a clean state where
3095    it is available to be used again.  Until this gets worked out, we will
3096    leave it commented out.  */
3097
3098 int atp86x_abort(Scsi_Cmnd * SCpnt)
3099 {
3100         unsigned char h;
3101         ULONG tmport;
3102         struct hw_device_ext *devext;
3103
3104         for (h = 0; h <= admaxu; h++) {
3105                 if (SCpnt->host == a867host[h]) {
3106                         goto find_adp;
3107                 }
3108         }
3109         panic("Abort host not found !");
3110 find_adp:
3111         devext=&dev_ext[h];
3112         printk(KERN_DEBUG "c0=%x c1=%x c2=%x c3=%x ", (u_int)devext->CSrb[0],
3113           (u_int)devext->CSrb[1],(u_int)devext->CSrb[2],(u_int)devext->CSrb[3]);
3114         tmport=devext->BaseIoAddress[0];
3115         printk(KERN_DEBUG " r%2x=%2x", 0x2a, inb(tmport+0x2a));
3116         return (SCSI_ABORT_SNOOZE);
3117 }
3118
3119 int atp86x_reset(Scsi_Cmnd * SCpnt, unsigned int reset_flags)
3120 {
3121         UCHAR h,i,j;
3122 #ifdef I2C_ENABLE
3123         UCHAR k,l;
3124 #endif
3125         ULONG baseIoAddress;
3126         struct hw_device_ext *devext;
3127         /*
3128          * See if a bus reset was suggested.
3129          */
3130         for (h = 0; h <= admaxu; h++) {
3131                 if (SCpnt->host == a867host[h]) {
3132                         goto find_host;
3133                 }
3134         }
3135         panic("Reset bus host not found !");
3136 find_host:
3137         devext=&dev_ext[h];
3138         if (devext->dev_id == ATP867_DEVID1)
3139         {
3140                 // BaseIO+0x28: bit 4=1 disable INTA
3141                 baseIoAddress = devext->BaseIoAddress[0];
3142                 Outpb(baseIoAddress,0x28,(UCHAR)
3143                         (Inpb(baseIoAddress,0x28) | 0x10));
3144                 // Stop PCI transfer for all channels
3145                 Outpb(baseIoAddress,0x40,0);
3146                 Outpb(baseIoAddress,0x50,0);
3147                 Outpb(baseIoAddress,0x60,0);
3148                 Outpb(baseIoAddress,0x70,0);
3149 #ifdef I2C_ENABLE
3150                 if (devext->c_mask != 0)
3151                 {
3152                         i=devext->c_mask;
3153                         for (k=0; k < 4; k++)
3154                         {
3155                                 if ((i & 0x10) != 0)
3156                                 {
3157                                         baseIoAddress = devext->BaseIoAddress[k];
3158                                         i2cread(baseIoAddress,0x41,&l);
3159                                         i2cread(baseIoAddress,0x42,&l);
3160                                         i2cread(baseIoAddress,0x40,&l);
3161                                         i2cread(baseIoAddress,0x41,&l);
3162                                         i2cread(baseIoAddress,0x42,&l);
3163                                         Outpb(baseIoAddress,0x43,0x20);
3164                                 }
3165                                 i >>= 1;
3166                         }
3167                         baseIoAddress = devext->BaseIoAddress[0];
3168                 }
3169 #else
3170                 baseIoAddress = devext->BaseIoAddress[0];
3171 #endif
3172                 // Enable Master IDE PreRead
3173                 Outpb(baseIoAddress,0x41,(UCHAR)
3174                         (Inpb(baseIoAddress,0x41) | 0x10));
3175                 Outpb(baseIoAddress,0x51,(UCHAR)
3176                         (Inpb(baseIoAddress,0x51) | 0x10));
3177                 Outpb(baseIoAddress,0x61,(UCHAR)
3178                         (Inpb(baseIoAddress,0x61) | 0x10));
3179                 Outpb(baseIoAddress,0x71,(UCHAR)
3180                         (Inpb(baseIoAddress,0x71) | 0x10));
3181                 mdelay(0x100);
3182                 // Disable Master IDE PreRead
3183                 Outpb(baseIoAddress,0x41,(UCHAR)
3184                         (Inpb(baseIoAddress,0x41) & 0xef));
3185                 Outpb(baseIoAddress,0x51,(UCHAR)
3186                         (Inpb(baseIoAddress,0x51) & 0xef));
3187                 Outpb(baseIoAddress,0x61,(UCHAR)
3188                         (Inpb(baseIoAddress,0x61) & 0xef));
3189                 Outpb(baseIoAddress,0x71,(UCHAR)
3190                         (Inpb(baseIoAddress,0x71) & 0xef));
3191                 ATP867init(devext);
3192         }
3193         else
3194         {
3195
3196                 // CFG_base+0x40+0x0A: bit 0 =1 disable INTA
3197                 pci_read_config_byte(devext->pdev, 0x4A, &j);
3198 #ifdef RESET_DEBUG
3199                 printk("865RESET: Read: config+0x4A= %2X\n",j);
3200 #endif
3201                 j |= 0x01;
3202                 pci_write_config_byte(devext->pdev, 0x4A, j);
3203 #ifdef RESET_DEBUG
3204                 printk("865RESET: Write: config+0x4A= %2X\n",j);
3205 #endif
3206
3207                 // Stop PCI transfer for all channels
3208                 Outpb(devext->BaseIoAddresm[0],0,0);
3209                 Outpb(devext->BaseIoAddresm[1],0,0);
3210 #ifdef RESET_DEBUG
3211                 printk("865RESET: Write: IO%4lX and %4lX=0\n",devext->BaseIoAddresm[0],devext->BaseIoAddresm[1]);
3212 #endif
3213                 /* disable pre-read or post write ,  delayed IRQ */
3214                 pci_write_config_byte(devext->pdev, 0x4B, 0);
3215                 mdelay(0x100);
3216                 /* Pre-read counter must be 0x000200  4C,4D,4E - 14,15,16*/
3217                 pci_write_config_byte(devext->pdev, 0x4C, 0);
3218                 pci_write_config_byte(devext->pdev, 0x4D, 0x02);
3219                 pci_write_config_byte(devext->pdev, 0x4E, 0);
3220                 pci_write_config_byte(devext->pdev, 0x14, 0);
3221                 pci_write_config_byte(devext->pdev, 0x15, 0x02);
3222                 pci_write_config_byte(devext->pdev, 0x16, 0);
3223
3224                 ATP865init(devext);
3225
3226                 /*  PCI config + 0x40 + 0xA:    bit 0: 0= enable INTA
3227                                                         bit 7: 1= enable PCI bus master
3228                 */
3229 #ifdef RESET_DEBUG
3230                 printk("atp865: read config + 0x4A\n");
3231 #endif
3232                 pci_read_config_byte(devext->pdev, 0x4A, &j);
3233 #ifdef RESET_DEBUG
3234                 printk("atp865: read config + 0x4A = %X\n",j);
3235 #endif
3236                 j &= 0xfe;
3237                 j |= 0x88;
3238                 pci_write_config_byte(devext->pdev, 0x4A, j);
3239
3240 /*              // Enable Master IDE PreRead
3241                 Outpb(baseIoAddress,0x41,(UCHAR)
3242                         (Inpb(baseIoAddress,0x41) | 0x10));
3243                 Outpb(baseIoAddress,0x51,(UCHAR)
3244                         (Inpb(baseIoAddress,0x51) | 0x10));
3245                 Outpb(baseIoAddress,0x61,(UCHAR)
3246                         (Inpb(baseIoAddress,0x61) | 0x10));
3247                 Outpb(baseIoAddress,0x71,(UCHAR)
3248                         (Inpb(baseIoAddress,0x71) | 0x10));
3249                 mdelay(0x100);
3250                 // Disable Master IDE PreRead
3251                 Outpb(baseIoAddress,0x41,(UCHAR)
3252                         (Inpb(baseIoAddress,0x41) & 0xef));
3253                 Outpb(baseIoAddress,0x51,(UCHAR)
3254                         (Inpb(baseIoAddress,0x51) & 0xef));
3255                 Outpb(baseIoAddress,0x61,(UCHAR)
3256                         (Inpb(baseIoAddress,0x61) & 0xef));
3257                 Outpb(baseIoAddress,0x71,(UCHAR)
3258                         (Inpb(baseIoAddress,0x71) & 0xef));
3259 */
3260
3261         }
3262
3263 //      S3init(devext);
3264
3265         for (i=0; i < 4 ; i++) {
3266                 devext->CSrb[i]=0;
3267                 devext->que_hd[i]=0;
3268                 devext->que_end[i]=0;
3269         }
3270         devext->in_int=0;
3271 /*
3272         SCpnt->result = 0x00080000;
3273         SCpnt->scsi_done(SCpnt);
3274         return (SCSI_RESET_SUCCESS | SCSI_RESET_BUS_RESET);  */
3275         return (SCSI_RESET_SNOOZE);
3276 }
3277
3278 void ATP867init(struct hw_device_ext * devext)
3279 {
3280     ULONG baseIoAddress = devext->BaseIoAddress[0];
3281     ULONG baseIoAddresm = devext->BaseIoAddresm[0];
3282     UCHAR  i,j,k,l,ata66,is66,iswd;
3283     UCHAR  cbuf[4];
3284     USHORT m,mbuf[256];
3285 #ifdef I2C_ENABLE
3286     UCHAR  n;
3287 #endif
3288
3289     mdelay(10000);
3290     Outpb(baseIoAddress,0x28,(UCHAR)
3291             (Inpb(baseIoAddress,0x28) | 0x10));
3292
3293     if (devext->chipver < 0x10)
3294     {
3295        Outpb(baseIoAddress,0x3f,0x08);
3296     }
3297     else
3298     {
3299        Outpb(baseIoAddress,0x3f,0x0a);
3300     }
3301     Outpb(baseIoAddress,0x4a,0x43);
3302     Outpb(baseIoAddress,0x5a,0x43);
3303     Outpb(baseIoAddress,0x6a,0x43);
3304     Outpb(baseIoAddress,0x7a,0x43);
3305     ata66=devext->ata66;
3306     Outpb(baseIoAddress,0x48,0x31);
3307     Outpb(baseIoAddress,0x49,0x31);
3308     Outpb(baseIoAddress,0x4b,0x00);
3309     Outpb(baseIoAddress,0x58,0x31);
3310     Outpb(baseIoAddress,0x59,0x31);
3311     Outpb(baseIoAddress,0x5b,0x00);
3312     Outpb(baseIoAddress,0x68,0x31);
3313     Outpb(baseIoAddress,0x69,0x31);
3314     Outpb(baseIoAddress,0x6b,0x00);
3315     Outpb(baseIoAddress,0x78,0x31);
3316     Outpb(baseIoAddress,0x79,0x31);
3317     Outpb(baseIoAddress,0x7b,0x00);
3318     cbuf[0] = 0x00;
3319     cbuf[1] = 0x00;
3320     cbuf[2] = 0x00;
3321     cbuf[3] = 0x00;
3322
3323     for ( i = 0 ; i < 8 ; i++ )
3324     {
3325         baseIoAddress=devext->BaseIoAddress[i >> 1];
3326         j=0xa0;
3327         if ((i & 0x01) != 0)
3328         {
3329            j=0xb0;
3330         }
3331         Outpb(baseIoAddress,6,j);
3332         mdelay(100);
3333         k=Inpb(baseIoAddress,7);
3334         if ((k & 0x88) != 0x00)
3335         {
3336            devext->hd_status[i]=0x7f;
3337            devext->cap[i]=0;
3338            continue;
3339         }
3340 wait_drdy:
3341         l=Inpb(baseIoAddress,7);
3342         if ((l & 0x80) != 0 )
3343         {
3344            goto wait_drdy;
3345         }
3346         Outpb(baseIoAddress,7,0xec);
3347         mdelay(400);
3348 wait_drq:
3349        l=Inpb(baseIoAddress,7);
3350        if ((l & 0x80) != 0 )
3351        {
3352           goto wait_drq;
3353        }
3354        if ((l & 0x01) == 0x01 )
3355        {
3356           devext->hd_status[i]=0x7f;
3357           devext->cap[i]=0;
3358           continue;
3359        }
3360        if ((l & 0xf8) != 0x58 )
3361        {
3362           devext->hd_status[i]=0x7f;
3363           devext->cap[i]=0;
3364           continue;
3365        }
3366        for (m=0; m < 0x100; m++)
3367        {
3368           mbuf[m]=Inpw(baseIoAddress,0);
3369        }
3370
3371        is66=0;
3372        iswd=0;
3373
3374        Outpb(baseIoAddress,1,0x03);
3375        if ((mbuf[88] & 0x0018) == 0)
3376        {
3377           if ((iswd == 0) && ((mbuf[88] & 0x007f) != 0))
3378           {
3379              Outpb(baseIoAddress,2,0x42);
3380           }
3381           else
3382           {
3383 force_normdma:
3384              k=(UCHAR)(mbuf[63] & 0x0007);
3385              k >>= 1;
3386              if (k > 2)
3387                 k=2;
3388              k |= 0x20;
3389              Outpb(baseIoAddress,2,k);
3390              iswd=1;
3391           }
3392        }
3393        else
3394        {
3395           if ( iswd != 0 )
3396           {
3397              goto force_normdma;
3398           }
3399
3400           if (((i < 2) && ((ata66 & 0x01) == 0)) ||
3401               ((i > 1) && ((ata66 & 0x02) == 0)))
3402           {
3403              if ((mbuf[88] & 0x0020) == 0)
3404              {
3405                 Outpb(baseIoAddress,2,0x44);
3406                 is66=1;
3407              }
3408              else
3409              {
3410                 if ((mbuf[88] & 0x0040) == 0)
3411                 {
3412                    is66=2;
3413                    Outpb(baseIoAddress,2,0x45);
3414                 }
3415                 else
3416                 {
3417                    is66=3;
3418                    Outpb(baseIoAddress,2,0x46);
3419                 }
3420              }
3421           }
3422           else
3423           {
3424              Outpb(baseIoAddress,2,0x42);
3425           }
3426        }
3427        Outpb(baseIoAddress,7,0xef);
3428        mdelay(1000);
3429        k=Inpb(baseIoAddress,7);
3430        while ((k & 0x80) != 0)
3431        {
3432          k=Inpb(baseIoAddress,7);
3433        }
3434        if ((k & 0xf9) == 0x50)
3435        {
3436           if ( is66 == 0)
3437           {
3438             if ( iswd == 0 )
3439             {
3440                if ( i == 0 )
3441                {
3442                   cbuf[0] |= 0x03;
3443                }
3444                if ( i == 1 )
3445                {
3446                   cbuf[0] |= 0x30;
3447                }
3448                if ( i == 2 )
3449                {
3450                   cbuf[1] |= 0x03;
3451                }
3452                if ( i == 3 )
3453                {
3454                   cbuf[1] |= 0x30;
3455                }
3456                if ( i == 4 )
3457                {
3458                   cbuf[2] |= 0x03;
3459                }
3460                if ( i == 5 )
3461                {
3462                   cbuf[2] |= 0x30;
3463                }
3464                if ( i == 6 )
3465                {
3466                   cbuf[3] |= 0x03;
3467                }
3468                if ( i == 7 )
3469                {
3470                   cbuf[3] |= 0x30;
3471                }
3472             }
3473           }
3474           else
3475           {
3476              if ( i == 0 )
3477              {
3478                 if ( is66 == 1 )
3479                 {
3480                    cbuf[0] |= 0x05;
3481                 }
3482                 else
3483                 {
3484                    if ( is66 == 2 )
3485                       cbuf[0] |= 0x06;
3486                    else
3487                       cbuf[0] |= 0x07;
3488                 }
3489              }
3490              if ( i == 1 )
3491              {
3492                 if ( is66 == 1 )
3493                 {
3494                    cbuf[0] |= 0x50;
3495                 }
3496                 else
3497                 {
3498                    if ( is66 == 2 )
3499                       cbuf[0] |= 0x60;
3500                    else
3501                       cbuf[0] |= 0x70;
3502                 }
3503              }
3504              if ( i == 2 )
3505              {
3506                 if ( is66 == 1 )
3507                 {
3508                    cbuf[1] |= 0x05;
3509                 }
3510                 else
3511                 {
3512                    if ( is66 == 2 )
3513                       cbuf[1] |= 0x06;
3514                    else
3515                       cbuf[1] |= 0x07;
3516                 }
3517              }
3518              if ( i == 3 )
3519              {
3520                 if ( is66 == 1 )
3521                 {
3522                    cbuf[1] |= 0x50;
3523                 }
3524                 else
3525                 {
3526                    if ( is66 == 2 )
3527                       cbuf[1] |= 0x60;
3528                    else
3529                       cbuf[1] |= 0x70;
3530                 }
3531              }
3532              if ( i == 4 )
3533              {
3534                 if ( is66 == 1 )
3535                 {
3536                    cbuf[2] |= 0x05;
3537                 }
3538                 else
3539                 {
3540                    if ( is66 == 2 )
3541                       cbuf[2] |= 0x06;
3542                    else
3543                       cbuf[2] |= 0x07;
3544                 }
3545              }
3546              if ( i == 5 )
3547              {
3548                 if ( is66 == 1 )
3549                 {
3550                    cbuf[2] |= 0x50;
3551                 }
3552                 else
3553                 {
3554                    if ( is66 == 2 )
3555                       cbuf[2] |= 0x60;
3556                    else
3557                       cbuf[2] |= 0x70;
3558                 }
3559              }
3560              if ( i == 6 )
3561              {
3562                 if ( is66 == 1 )
3563                 {
3564                    cbuf[3] |= 0x05;
3565                 }
3566                 else
3567                 {
3568                    if ( is66 == 2 )
3569                       cbuf[3] |= 0x06;
3570                    else
3571                       cbuf[3] |= 0x07;
3572                 }
3573              }
3574              if ( i == 7 )
3575              {
3576                 if ( is66 == 1 )
3577                 {
3578                    cbuf[3] |= 0x50;
3579                 }
3580                 else
3581                 {
3582                    if ( is66 == 2 )
3583                       cbuf[3] |= 0x60;
3584                    else
3585                       cbuf[3] |= 0x70;
3586                 }
3587              }
3588           }
3589        }
3590     }
3591     baseIoAddress=devext->BaseIoAddress[0];
3592     Outpb(baseIoAddress,0x4b,cbuf[0]);
3593     Outpb(baseIoAddress,0x5b,cbuf[1]);
3594     Outpb(baseIoAddress,0x6b,cbuf[2]);
3595     Outpb(baseIoAddress,0x7b,cbuf[3]);
3596
3597     j=Inpb(baseIoAddress,0x28);
3598     j &= 0xcf;
3599     j |= 0xd0;
3600     Outpb(baseIoAddress,0x28,j);
3601     Outpb(baseIoAddress,0x29,(UCHAR)
3602             (Inpb(baseIoAddress,0x29) & 0xe0));
3603     devext->c_mask = 0;
3604 #ifdef I2C_ENABLE
3605     for (i=0; i < 4; i++)
3606     {
3607         baseIoAddress = devext->BaseIoAddress[i];
3608         j=0;
3609         n=0;
3610         l=0;
3611         Outpb(baseIoAddress,0x0e,0x08);
3612         i2cwrite(baseIoAddress,0x4e,0x80);
3613         i2cread(baseIoAddress,0x4f,&j);
3614         i2cwrite(baseIoAddress,0x4e,0x00);
3615         i2cread(baseIoAddress,0x4f,&n);
3616         i2cread(baseIoAddress,0x58,&l);
3617         if ((j == 0x5c) && (n == 0xa3) && (l == 0x40))
3618         {
3619            j=0x10;
3620            j <<= i;
3621            devext->c_mask |= j;
3622            i2cread(baseIoAddress,0x41,&j);
3623            i2cread(baseIoAddress,0x42,&j);
3624            i2cwrite(baseIoAddress,0x43,0xf8);
3625            i2cwrite(baseIoAddress,0x44,0x0e);
3626            i2cwrite(baseIoAddress,0x2b,0xff);
3627            i2cwrite(baseIoAddress,0x2c,0x3e);
3628            i2cwrite(baseIoAddress,0x2f,0xff);
3629            i2cwrite(baseIoAddress,0x30,0x3e);
3630            i2cwrite(baseIoAddress,0x33,0xff);
3631            i2cwrite(baseIoAddress,0x34,0x3e);
3632            i2cwrite(baseIoAddress,0x4d,0xc0);
3633            i2cread(baseIoAddress,0x40,&j);
3634            i2cread(baseIoAddress,0x41,&j);
3635            i2cread(baseIoAddress,0x42,&j);
3636            i2cread(baseIoAddress,0x43,&j);
3637            i2cread(baseIoAddress,0x44,&j);
3638            i2cread(baseIoAddress,0x2b,&j);
3639            i2cread(baseIoAddress,0x2c,&j);
3640            i2cread(baseIoAddress,0x2f,&j);
3641            i2cread(baseIoAddress,0x30,&j);
3642            i2cread(baseIoAddress,0x33,&j);
3643            i2cread(baseIoAddress,0x34,&j);
3644            i2cwrite(baseIoAddress,0x40,0x43);
3645            Outpb(baseIoAddress,0x0e,0x08);
3646            i2cread(baseIoAddress,0x41,&j);
3647            i2cread(baseIoAddress,0x42,&j);
3648            if (devext->hd_status[i << 1] == 0)
3649            {
3650               Outpb(baseIoAddress,0x43,0x84);
3651            }
3652            else
3653            {
3654               Outpb(baseIoAddress,0x43,0x80);
3655            }
3656            Outpb(baseIoAddress,0x0e,0x08);
3657            Outpb(baseIoAddress,0x43,0x20);
3658            baseIoAddress = devext->BaseIoAddress[0];
3659            Outpb(baseIoAddress,0x29,(UCHAR)
3660                  (Inpb(baseIoAddress,0x29) | 0x10));
3661         }
3662     }
3663 #endif
3664     baseIoAddress=devext->BaseIoAddress[0];
3665
3666     Outpb(baseIoAddresm,2,0x06);
3667     Outpb(baseIoAddresm,0x12,0x06);
3668     Outpb(baseIoAddresm,0x22,0x06);
3669     Outpb(baseIoAddresm,0x32,0x06);
3670     Outpb(baseIoAddress,0x28,(UCHAR)
3671             (Inpb(baseIoAddress,0x28) & 0xef));
3672     return;
3673 }
3674
3675 void ATP865init(struct hw_device_ext * devext)
3676 {
3677 //    ULONG baseIoAddress = devext->BaseIoAddress[1];
3678 //    ULONG baseIoAddresm = devext->BaseIoAddresm[0];
3679 //    UCHAR  i,j,k,l,n,ata66,is66,iswd;
3680 //    UCHAR  cbuf[4];
3681 //    USHORT m,mbuf[256];
3682
3683     mdelay(1000);
3684 #ifdef RESET_DEBUG
3685     printk("865RESET: Should h/w or s/w reset IDE first.\n");
3686 #endif
3687     // 3X6=
3688     Outpb(devext->BaseIoAddress[0],6,0xA0);
3689     Outpb(devext->BaseIoAddress[2],2,0x04);
3690     Outpb(devext->BaseIoAddress[0],6,0xB0);
3691     Outpb(devext->BaseIoAddress[2],2,0x04);
3692     Outpb(devext->BaseIoAddress[1],6,0xA0);
3693     Outpb(devext->BaseIoAddress[3],2,0x04);
3694     Outpb(devext->BaseIoAddress[1],6,0xB0);
3695     Outpb(devext->BaseIoAddress[3],2,0x04);
3696     mdelay(10);
3697     Outpb(devext->BaseIoAddress[0],6,0xA0);
3698     Outpb(devext->BaseIoAddress[2],2,0x00);
3699     Outpb(devext->BaseIoAddress[0],6,0xB0);
3700     Outpb(devext->BaseIoAddress[2],2,0x00);
3701     Outpb(devext->BaseIoAddress[1],6,0xA0);
3702     Outpb(devext->BaseIoAddress[3],2,0x00);
3703     Outpb(devext->BaseIoAddress[1],6,0xB0);
3704     Outpb(devext->BaseIoAddress[3],2,0x00);
3705     mdelay(5000);
3706     Outpb(devext->BaseIoAddress[0],6,0xA0);
3707     Inpb(devext->BaseIoAddress[0],0x7);
3708     Outpb(devext->BaseIoAddress[0],6,0xB0);
3709     Inpb(devext->BaseIoAddress[0],0x7);
3710     Outpb(devext->BaseIoAddress[1],6,0xA0);
3711     Inpb(devext->BaseIoAddress[1],0x7);
3712     Outpb(devext->BaseIoAddress[1],6,0xB0);
3713     Inpb(devext->BaseIoAddress[1],0x7);
3714 #ifdef RESET_DEBUG
3715     printk("865RESET: init routine not ready, use is865() instead.\n");
3716 #endif
3717     is865(devext,devext->pdev);
3718     return;
3719 }
3720
3721
3722 const char *atp86x_info(struct Scsi_Host *notused)
3723 {
3724         static char buffer[128];
3725
3726         strcpy(buffer, "ACARD ATP86X PCI ATA133 Adapter Driver Ver: 0.78  Date: 2004/01/15\n");
3727
3728         notused->ide_hdd = 1;   //+Wilson05112005, IDE Bridge exist
3729
3730         return buffer;
3731 }
3732
3733 int atp86x_set_info(char *buffer, int length, struct Scsi_Host *HBAptr)
3734 {
3735         return -ENOSYS;         /* Currently this is a no-op */
3736 }
3737
3738 #define BLS buffer + len + size
3739 int atp86x_proc_info(char *buffer, char **start, off_t offset, int length,
3740                       int hostno, int inout)
3741 {
3742         struct Scsi_Host *HBAptr;
3743         static u8 buff[512];
3744         int i;
3745         int size = 0;
3746         int len = 0;
3747         off_t begin = 0;
3748         off_t pos = 0;
3749
3750         HBAptr = NULL;
3751         for (i = 0; i < 4; i++) {
3752                 if ((HBAptr = a867host[i]) != NULL) {
3753                         if (HBAptr->host_no == hostno) {
3754                                 break;
3755                         }
3756                         HBAptr = NULL;
3757                 }
3758         }
3759
3760         if (HBAptr == NULL) {
3761                 size += sprintf(BLS, "Can't find adapter for host number %d\n", hostno);
3762                 len += size;
3763                 pos = begin + len;
3764                 size = 0;
3765                 goto stop_output;
3766         }
3767         if (inout == TRUE) {    /* Has data been written to the file? */
3768                 return (atp86x_set_info(buffer, length, HBAptr));
3769         }
3770         if (offset == 0) {
3771                 memset(buff, 0, sizeof(buff));
3772         }
3773         size += sprintf(BLS, "ACARD ATP86X PCI ATA133 Adapter Driver Ver: 0.78  Date: 2004/01/15\n");
3774         len += size;
3775         pos = begin + len;
3776         size = 0;
3777
3778         size += sprintf(BLS, "\n");
3779         size += sprintf(BLS, "Adapter Configuration:\n");
3780         size += sprintf(BLS, "               Base IO: %#.4lx\n", HBAptr->io_port);
3781         size += sprintf(BLS, "                   IRQ: %d\n", HBAptr->irq);
3782         len += size;
3783         pos = begin + len;
3784         size = 0;
3785
3786 stop_output:
3787         *start = buffer + (offset - begin);     /* Start of wanted data */
3788         len -= (offset - begin);        /* Start slop */
3789         if (len > length) {
3790                 len = length;   /* Ending slop */
3791         }
3792         return (len);
3793 }
3794
3795 #include "sd.h"
3796
3797 int atp86x_biosparam(Scsi_Disk * disk, kdev_t dev, int *ip)
3798 {
3799         int heads, sectors, cylinders;
3800
3801         heads = 64;
3802         sectors = 32;
3803         cylinders = disk->capacity / (heads * sectors);
3804
3805         if (cylinders > 1024) {
3806                 heads = 255;
3807                 sectors = 63;
3808                 cylinders = disk->capacity / (heads * sectors);
3809         }
3810         ip[0] = heads;
3811         ip[1] = sectors;
3812         ip[2] = cylinders;
3813
3814         return 0;
3815 }
3816
3817 int atp86x_release (struct Scsi_Host *pshost)
3818 {
3819         int h,i,k;
3820         struct hw_device_ext *devext;
3821
3822         for (h = 0; h <= admaxu; h++)
3823         {
3824                 if (pshost == a867host[h]) {
3825                         devext = &dev_ext[h];
3826                         free_irq (pshost->irq, devext);
3827                         if (devext->dev_id == ATP867_DEVID1)
3828                                 release_region (pshost->io_port, pshost->n_io_port);
3829                         else
3830                         {
3831                                 release_region(devext->BaseIoAddress[0],  0x8); /* Register the IO ports that we use */
3832                                 release_region(devext->BaseIoAddress[2],  0x3); /* Register the IO ports that we use */
3833                                 release_region(devext->BaseIoAddress[1],  0x8); /* Register the IO ports that we use */
3834                                 release_region(devext->BaseIoAddress[3],  0x3); /* Register the IO ports that we use */
3835                                 release_region(devext->BaseIoAddresm[0], 0x10); /* Register the IO ports that we use */
3836                         }
3837                         scsi_unregister(pshost);
3838                         for(i=0;i < 4;i++)
3839                         {
3840                            for(k=0;k < qcnt1;k++)
3841                            {
3842 #ifdef IXP42X_SUPPORT
3843                                 pci_free_consistent(devext->pdev, 256,
3844                                     devext->lsrb[i][k].prd, devext->lsrb[i][k].prdaddr);
3845 #else
3846                               kfree(devext->lsrb[i][k].prd);
3847 #endif
3848                            }
3849                         }
3850                         // add for smart read  =================//
3851                         devext->FG_TimerStop = 1;
3852                         mdelay(30);
3853                         del_timer_sync(&(devext->AdapterTimer));
3854                         //======================================//
3855                         return 0;
3856                 }
3857         }
3858         panic("atp86x: bad scsi host passed.\n");
3859 }
3860 // add for smart read  =================//
3861 void smart_timer(ULONG para)
3862 {
3863         struct hw_device_ext * devext;
3864         Scsi_Cmnd *pScsiCmd;
3865
3866         devext  = (struct hw_device_ext *)para;
3867         if (   (devext->FG_SmartRead == 0)
3868              &&(devext->cap[0] != 0)
3869              &&(devext->hd_status[0] != 0x7f)
3870            )
3871         {       // if smart read command not send to channel queue of hard disk yet
3872 //              printk("send smart read command\n");
3873                 pScsiCmd = &(devext->SmartSrb);
3874                 pScsiCmd->cmnd[0]   = 0xB0;
3875                 pScsiCmd->lun       = 0;
3876                 pScsiCmd->target    = 0;
3877                 pScsiCmd->scsi_done = internal_done;
3878                 if ((devext->que_end[0] += 1) > qcnt1 - 1)
3879         {
3880                    devext->que_end[0]=0;
3881         }
3882         devext->QSrb[0][devext->que_end[0]] = pScsiCmd;
3883                 devext->FG_SmartRead = 1;
3884                 if (devext->in_int == 0)
3885                 {
3886                         if ( (devext->CSrb[0]   == 0) &&
3887                                  (devext->que_hd[0] != devext->que_end[0]) )
3888                         {
3889                                 if ( devext->que_hd[0] == qcnt1 - 1 )
3890                                 {
3891                                         devext->que_hd[0]=0;
3892                                 }else
3893                                 {
3894                                         devext->que_hd[0]++;
3895                                 }
3896                                 devext->CSrb[0]=devext->QSrb[0][devext->que_hd[0]];
3897                                 devext->Cplsrb[0]=devext->plsrb[0][devext->que_hd[0]];
3898                                 SendScsi(devext,devext->CSrb[0],0);
3899                         }
3900                 }
3901         }
3902
3903         if( !(devext->FG_TimerStop) )
3904         {
3905                 (devext->AdapterTimer).expires = jiffies + HZ*30;
3906                 add_timer(&(devext->AdapterTimer));
3907         }
3908 }
3909 //======================================//
3910 MODULE_LICENSE("GPL");
3911
3912 static Scsi_Host_Template driver_template = {
3913         next: NULL,
3914         module: NULL,
3915         proc_info: atp86x_proc_info,
3916         name: NULL,
3917         detect: atp86x_detect,
3918         release: atp86x_release,
3919         info: atp86x_info,
3920         command: atp86x_command,
3921         queuecommand: atp86x_queuecommand,
3922         eh_strategy_handler: NULL,
3923         eh_abort_handler: NULL,
3924         eh_device_reset_handler: NULL,
3925         eh_bus_reset_handler: NULL,
3926         eh_host_reset_handler: NULL,
3927         abort: atp86x_abort,
3928         reset: atp86x_reset,
3929         slave_attach: NULL,
3930         bios_param: atp86x_biosparam,
3931         can_queue: qcnt,         /* max simultaneous cmds      */
3932         this_id: 8,            /* scsi id of host adapter    */
3933         sg_tablesize: ATP86X_SCATTER,   /* max scatter-gather cmds    */
3934         cmd_per_lun: ATP86X_CMDLUN,     /* cmds per lun (linked cmds) */
3935         present: 0,             /* number of xxx's present   */
3936         unchecked_isa_dma: 0,   /* no memory DMA restrictions */
3937         use_clustering: ENABLE_CLUSTERING,
3938         use_new_eh_code: 0
3939 };
3940 #include "scsi_module.c"
3941