1 /**************************************************************************
2 * Initio A100 device driver for Linux.
4 * Copyright (c) 1994-1998 Initio Corporation
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2, or (at your option)
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; see the file COPYING. If not, write to
19 * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
21 * --------------------------------------------------------------------------
23 * Redistribution and use in source and binary forms, with or without
24 * modification, are permitted provided that the following conditions
26 * 1. Redistributions of source code must retain the above copyright
27 * notice, this list of conditions, and the following disclaimer,
28 * without modification, immediately at the beginning of the file.
29 * 2. Redistributions in binary form must reproduce the above copyright
30 * notice, this list of conditions and the following disclaimer in the
31 * documentation and/or other materials provided with the distribution.
32 * 3. The name of the author may not be used to endorse or promote products
33 * derived from this software without specific prior written permission.
35 * Where this Software is combined with software released under the terms of
36 * the GNU General Public License ("GPL") and the terms of the GPL would require the
37 * combined work to also be released under the terms of the GPL, the terms
38 * and conditions of this License will apply in addition to those of the
39 * GPL with the exception of any terms or conditions of this License that
40 * conflict with, or are expressly prohibited by, the GPL.
42 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
43 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
45 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
46 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
48 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
49 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
50 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
51 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
54 **************************************************************************
57 * Description: INI-A100U2W LINUX device driver header
59 * 06/18/98 HL, Initial Version 1.02
60 * 12/19/98 bv, v1.02a Use spinlocks for 2.1.95 and up.
61 **************************************************************************/
63 #include <linux/config.h>
64 #include <linux/types.h>
66 #define ULONG unsigned long
68 #define USHORT unsigned short
69 #define UCHAR unsigned char
70 #define BYTE unsigned char
71 #define WORD unsigned short
72 #define DWORD unsigned long
73 #define UBYTE unsigned char
74 #define UWORD unsigned short
75 #define UDWORD unsigned long
79 #define NULL 0 /* zero */
82 #define TRUE (1) /* boolean true */
85 #define FALSE (0) /* boolean false */
91 #define ORC_MAXQUEUE 245
93 #define ORC_MAXQUEUE 25
96 #define TOTAL_SG_ENTRY 32
97 #define MAX_TARGETS 16
100 #define MAX_SUPPORTED_ADAPTERS 4
101 #define SUCCESSFUL 0x00
103 #define I920_DEVICE_ID 0x0002 /* Initio's inic-950 product ID */
105 /************************************************************************/
106 /* Scatter-Gather Element Structure */
107 /************************************************************************/
108 typedef struct ORC_SG_Struc {
109 U32 SG_Ptr; /* Data Pointer */
110 U32 SG_Len; /* Data Length */
113 typedef struct inia100_Adpt_Struc {
114 UWORD ADPT_BIOS; /* 0 */
115 UWORD ADPT_BASE; /* 1 */
116 UBYTE ADPT_Bus; /* 2 */
117 UBYTE ADPT_Device; /* 3 */
118 UBYTE ADPT_INTR; /* 4 */
119 } INIA100_ADPT_STRUCT;
122 /* SCSI related definition */
123 #define DISC_NOT_ALLOW 0x80 /* Disconnect is not allowed */
124 #define DISC_ALLOW 0xC0 /* Disconnect is allowed */
127 #define ORC_OFFSET_SCB 16
128 #define ORC_MAX_SCBS 250
129 #define MAX_CHANNELS 2
130 #define MAX_ESCB_ELE 64
131 #define TCF_DRV_255_63 0x0400
133 /********************************************************/
134 /* Orchid Configuration Register Set */
135 /********************************************************/
136 #define ORC_PVID 0x00 /* Vendor ID */
137 #define ORC_VENDOR_ID 0x1101 /* Orchid vendor ID */
138 #define ORC_PDID 0x02 /* Device ID */
139 #define ORC_DEVICE_ID 0x1060 /* Orchid device ID */
140 #define ORC_COMMAND 0x04 /* Command */
141 #define BUSMS 0x04 /* BUS MASTER Enable */
142 #define IOSPA 0x01 /* IO Space Enable */
143 #define ORC_STATUS 0x06 /* Status register */
144 #define ORC_REVISION 0x08 /* Revision number */
145 #define ORC_BASE 0x10 /* Base address */
146 #define ORC_BIOS 0x50 /* Expansion ROM base address */
147 #define ORC_INT_NUM 0x3C /* Interrupt line */
148 #define ORC_INT_PIN 0x3D /* Interrupt pin */
151 /********************************************************/
152 /* Orchid Host Command Set */
153 /********************************************************/
154 #define ORC_CMD_NOP 0x00 /* Host command - NOP */
155 #define ORC_CMD_VERSION 0x01 /* Host command - Get F/W version */
156 #define ORC_CMD_ECHO 0x02 /* Host command - ECHO */
157 #define ORC_CMD_SET_NVM 0x03 /* Host command - Set NVRAM */
158 #define ORC_CMD_GET_NVM 0x04 /* Host command - Get NVRAM */
159 #define ORC_CMD_GET_BUS_STATUS 0x05 /* Host command - Get SCSI bus status */
160 #define ORC_CMD_ABORT_SCB 0x06 /* Host command - Abort SCB */
161 #define ORC_CMD_ISSUE_SCB 0x07 /* Host command - Issue SCB */
163 /********************************************************/
164 /* Orchid Register Set */
165 /********************************************************/
166 #define ORC_GINTS 0xA0 /* Global Interrupt Status */
167 #define QINT 0x04 /* Reply Queue Interrupt */
168 #define ORC_GIMSK 0xA1 /* Global Interrupt MASK */
169 #define MQINT 0x04 /* Mask Reply Queue Interrupt */
170 #define ORC_GCFG 0xA2 /* Global Configure */
171 #define EEPRG 0x01 /* Enable EEPROM programming */
172 #define ORC_GSTAT 0xA3 /* Global status */
173 #define WIDEBUS 0x10 /* Wide SCSI Devices connected */
174 #define ORC_HDATA 0xA4 /* Host Data */
175 #define ORC_HCTRL 0xA5 /* Host Control */
176 #define SCSIRST 0x80 /* SCSI bus reset */
177 #define HDO 0x40 /* Host data out */
178 #define HOSTSTOP 0x02 /* Host stop RISC engine */
179 #define DEVRST 0x01 /* Device reset */
180 #define ORC_HSTUS 0xA6 /* Host Status */
181 #define HDI 0x02 /* Host data in */
182 #define RREADY 0x01 /* RISC engine is ready to receive */
183 #define ORC_NVRAM 0xA7 /* Nvram port address */
188 #define ORC_PQUEUE 0xA8 /* Posting queue FIFO */
189 #define ORC_PQCNT 0xA9 /* Posting queue FIFO Cnt */
190 #define ORC_RQUEUE 0xAA /* Reply queue FIFO */
191 #define ORC_RQUEUECNT 0xAB /* Reply queue FIFO Cnt */
192 #define ORC_FWBASEADR 0xAC /* Firmware base address */
194 #define ORC_EBIOSADR0 0xB0 /* External Bios address */
195 #define ORC_EBIOSADR1 0xB1 /* External Bios address */
196 #define ORC_EBIOSADR2 0xB2 /* External Bios address */
197 #define ORC_EBIOSDATA 0xB3 /* External Bios address */
199 #define ORC_SCBSIZE 0xB7 /* SCB size register */
200 #define ORC_SCBBASE0 0xB8 /* SCB base address 0 */
201 #define ORC_SCBBASE1 0xBC /* SCB base address 1 */
203 #define ORC_RISCCTL 0xE0 /* RISC Control */
204 #define PRGMRST 0x002
205 #define DOWNLOAD 0x001
206 #define ORC_PRGMCTR0 0xE2 /* RISC program counter */
207 #define ORC_PRGMCTR1 0xE3 /* RISC program counter */
208 #define ORC_RISCRAM 0xEC /* RISC RAM data port 4 bytes */
210 typedef struct orc_extended_scb { /* Extended SCB */
211 ORC_SG ESCB_SGList[TOTAL_SG_ENTRY]; /*0 Start of SG list */
212 unsigned char *SCB_Srb; /*50 SRB Pointer */
213 // Scsi_Cmnd *SCB_Srb; /*50 SRB Pointer */
216 /***********************************************************************
218 ************************************************************************/
219 typedef struct orc_scb { /* Scsi_Ctrl_Blk */
220 UBYTE SCB_Opcode; /*00 SCB command code&residual */
221 UBYTE SCB_Flags; /*01 SCB Flags */
222 UBYTE SCB_Target; /*02 Target Id */
223 UBYTE SCB_Lun; /*03 Lun */
224 U32 SCB_Reserved0; /*04 Reserved for ORCHID must 0 */
225 U32 SCB_XferLen; /*08 Data Transfer Length */
226 U32 SCB_Reserved1; /*0C Reserved for ORCHID must 0 */
227 U32 SCB_SGLen; /*10 SG list # * 8 */
228 U32 SCB_SGPAddr; /*14 SG List Buf physical Addr */
229 U32 SCB_SGPAddrHigh; /*18 SG Buffer high physical Addr */
230 UBYTE SCB_HaStat; /*1C Host Status */
231 UBYTE SCB_TaStat; /*1D Target Status */
232 UBYTE SCB_Status; /*1E SCB status */
233 UBYTE SCB_Link; /*1F Link pointer, default 0xFF */
234 UBYTE SCB_SenseLen; /*20 Sense Allocation Length */
235 UBYTE SCB_CDBLen; /*21 CDB Length */
236 UBYTE SCB_Ident; /*22 Identify */
237 UBYTE SCB_TagMsg; /*23 Tag Message */
238 UBYTE SCB_CDB[IMAX_CDB]; /*24 SCSI CDBs */
239 UBYTE SCB_ScbIdx; /*3C Index for this ORCSCB */
240 U32 SCB_SensePAddr; /*34 Sense Buffer physical Addr */
242 ESCB *SCB_EScb; /*38 Extended SCB Pointer */
244 UBYTE SCB_Reserved2[4]; /*3E Reserved for Driver use */
248 /* Opcodes of ORCSCB_Opcode */
249 #define ORC_EXECSCSI 0x00 /* SCSI initiator command with residual */
250 #define ORC_BUSDEVRST 0x01 /* SCSI Bus Device Reset */
252 /* Status of ORCSCB_Status */
253 #define SCB_COMPLETE 0x00 /* SCB request completed */
254 #define SCB_POST 0x01 /* SCB is posted by the HOST */
256 /* Bit Definition for ORCSCB_Flags */
257 #define SCF_DISINT 0x01 /* Disable HOST interrupt */
258 #define SCF_DIR 0x18 /* Direction bits */
259 #define SCF_NO_DCHK 0x00 /* Direction determined by SCSI */
260 #define SCF_DIN 0x08 /* From Target to Initiator */
261 #define SCF_DOUT 0x10 /* From Initiator to Target */
262 #define SCF_NO_XF 0x18 /* No data transfer */
263 #define SCF_POLL 0x40
265 /* Error Codes for ORCSCB_HaStat */
266 #define HOST_SEL_TOUT 0x11
267 #define HOST_DO_DU 0x12
268 #define HOST_BUS_FREE 0x13
269 #define HOST_BAD_PHAS 0x14
270 #define HOST_INV_CMD 0x16
271 #define HOST_SCSI_RST 0x1B
272 #define HOST_DEV_RST 0x1C
275 /* Error Codes for ORCSCB_TaStat */
276 #define TARGET_CHK_COND 0x02
277 #define TARGET_BUSY 0x08
278 #define TARGET_TAG_FULL 0x28
281 /* Queue tag msg: Simple_quque_tag, Head_of_queue_tag, Ordered_queue_tag */
282 #define MSG_STAG 0x20
283 #define MSG_HTAG 0x21
284 #define MSG_OTAG 0x22
286 #define MSG_IGNOREWIDE 0x23
288 #define MSG_IDENT 0x80
289 #define MSG_DISC 0x40 /* Disconnect allowed */
293 #define MSG_EXTEND 0x01
295 #define MSG_ABORT 0x06
298 #define MSG_PARITY 0x09
299 #define MSG_DEVRST 0x0C
300 #define MSG_STAG 0x20
302 /***********************************************************************
303 Target Device Control Structure
304 **********************************************************************/
306 typedef struct ORC_Tar_Ctrl_Struc {
307 UBYTE TCS_DrvDASD; /* 6 */
308 UBYTE TCS_DrvSCSI; /* 7 */
309 UBYTE TCS_DrvHead; /* 8 */
310 UWORD TCS_DrvFlags; /* 4 */
311 UBYTE TCS_DrvSector; /* 7 */
312 } ORC_TCS, *PORC_TCS;
314 /* Bit Definition for TCF_DrvFlags */
315 #define TCS_DF_NODASD_SUPT 0x20 /* Suppress OS/2 DASD Mgr support */
316 #define TCS_DF_NOSCSI_SUPT 0x40 /* Suppress OS/2 SCSI Mgr support */
319 /***********************************************************************
320 Host Adapter Control Structure
321 ************************************************************************/
322 typedef struct ORC_Ha_Ctrl_Struc {
323 USHORT HCS_Base; /* 00 */
324 UBYTE HCS_Index; /* 02 */
325 UBYTE HCS_Intr; /* 04 */
326 UBYTE HCS_SCSI_ID; /* 06 H/A SCSI ID */
327 UBYTE HCS_BIOS; /* 07 BIOS configuration */
329 UBYTE HCS_Flags; /* 0B */
330 UBYTE HCS_HAConfig1; /* 1B SCSI0MAXTags */
331 UBYTE HCS_MaxTar; /* 1B SCSI0MAXTags */
333 USHORT HCS_Units; /* Number of units this adapter */
334 USHORT HCS_AFlags; /* Adapter info. defined flags */
335 ULONG HCS_Timeout; /* Adapter timeout value */
336 PVOID HCS_virScbArray; /* 28 Virtual Pointer to SCB array */
337 U32 HCS_physScbArray; /* Scb Physical address */
338 PVOID HCS_virEscbArray; /* Virtual pointer to ESCB Scatter list */
339 U32 HCS_physEscbArray; /* scatter list Physical address */
340 UBYTE TargetFlag[16]; /* 30 target configuration, TCF_EN_TAG */
341 UBYTE MaximumTags[16]; /* 40 ORC_MAX_SCBS */
342 UBYTE ActiveTags[16][16]; /* 50 */
343 ORC_TCS HCS_Tcs[16]; /* 28 */
344 U32 BitAllocFlag[MAX_CHANNELS][8]; /* Max STB is 256, So 256/32 */
345 spinlock_t BitAllocFlagLock;
348 spinlock_t pSRB_lock;
351 /* Bit Definition for HCS_Flags */
353 #define HCF_SCSI_RESET 0x01 /* SCSI BUS RESET */
354 #define HCF_PARITY 0x02 /* parity card */
355 #define HCF_LVDS 0x10 /* parity card */
357 /* Bit Definition for TargetFlag */
359 #define TCF_EN_255 0x08
360 #define TCF_EN_TAG 0x10
361 #define TCF_BUSY 0x20
362 #define TCF_DISCONNECT 0x40
363 #define TCF_SPIN_UP 0x80
365 /* Bit Definition for HCS_AFlags */
366 #define HCS_AF_IGNORE 0x01 /* Adapter ignore */
367 #define HCS_AF_DISABLE_RESET 0x10 /* Adapter disable reset */
368 #define HCS_AF_DISABLE_ADPT 0x80 /* Adapter disable */
371 /*---------------------------------------*/
372 /* TimeOut for RESET to complete (30s) */
374 /* After a RESET the drive is checked */
376 /*---------------------------------------*/
377 #define DELAYED_RESET_MAX (30*1000L)
378 #define DELAYED_RESET_INTERVAL 200L
380 /*----------------------------------------------*/
381 /* TimeOut for IRQ from last interrupt (5s) */
382 /*----------------------------------------------*/
383 #define IRQ_TIMEOUT_INTERVAL (5*1000L)
385 /*----------------------------------------------*/
386 /* Retry Delay interval (200ms) */
387 /*----------------------------------------------*/
388 #define DELAYED_RETRY_INTERVAL 200L
390 #define INQUIRY_SIZE 36
391 #define CAPACITY_SIZE 8
392 #define DEFAULT_SENSE_LEN 14
394 #define DEVICE_NOT_FOUND 0x86
396 /*----------------------------------------------*/
397 /* Definition for PCI device */
398 /*----------------------------------------------*/
399 #define MAX_PCI_DEVICES 21
400 #define MAX_PCI_BUSES 8
402 typedef struct Adpt_Struc {
403 USHORT ADPT_BIOS; /* 0 */
404 UBYTE ADPT_BASE; /* 1 */
405 UBYTE ADPT_Bus; /* 2 */
406 UBYTE ADPT_Device; /* 3 */
407 UBYTE ADPT_Reserved[3];
410 typedef struct _NVRAM {
411 /*----------header ---------------*/
412 UCHAR SubVendorID0; /* 00 - Sub Vendor ID */
413 UCHAR SubVendorID1; /* 00 - Sub Vendor ID */
414 UCHAR SubSysID0; /* 02 - Sub System ID */
415 UCHAR SubSysID1; /* 02 - Sub System ID */
416 UCHAR SubClass; /* 04 - Sub Class */
417 UCHAR VendorID0; /* 05 - Vendor ID */
418 UCHAR VendorID1; /* 05 - Vendor ID */
419 UCHAR DeviceID0; /* 07 - Device ID */
420 UCHAR DeviceID1; /* 07 - Device ID */
421 UCHAR Reserved0[2]; /* 09 - Reserved */
422 UCHAR Revision; /* 0B - Revision of data structure */
423 /* ----Host Adapter Structure ---- */
424 UCHAR NumOfCh; /* 0C - Number of SCSI channel */
425 UCHAR BIOSConfig1; /* 0D - BIOS configuration 1 */
426 UCHAR BIOSConfig2; /* 0E - BIOS boot channel&target ID */
427 UCHAR BIOSConfig3; /* 0F - BIOS configuration 3 */
428 /* ----SCSI channel Structure ---- */
429 /* from "CTRL-I SCSI Host Adapter SetUp menu " */
430 UCHAR SCSI0Id; /* 10 - Channel 0 SCSI ID */
431 UCHAR SCSI0Config; /* 11 - Channel 0 SCSI configuration */
432 UCHAR SCSI0MaxTags; /* 12 - Channel 0 Maximum tags */
433 UCHAR SCSI0ResetTime; /* 13 - Channel 0 Reset recovering time */
434 UCHAR ReservedforChannel0[2]; /* 14 - Reserved */
436 /* ----SCSI target Structure ---- */
437 /* from "CTRL-I SCSI device SetUp menu " */
438 UCHAR Target00Config; /* 16 - Channel 0 Target 0 config */
439 UCHAR Target01Config; /* 17 - Channel 0 Target 1 config */
440 UCHAR Target02Config; /* 18 - Channel 0 Target 2 config */
441 UCHAR Target03Config; /* 19 - Channel 0 Target 3 config */
442 UCHAR Target04Config; /* 1A - Channel 0 Target 4 config */
443 UCHAR Target05Config; /* 1B - Channel 0 Target 5 config */
444 UCHAR Target06Config; /* 1C - Channel 0 Target 6 config */
445 UCHAR Target07Config; /* 1D - Channel 0 Target 7 config */
446 UCHAR Target08Config; /* 1E - Channel 0 Target 8 config */
447 UCHAR Target09Config; /* 1F - Channel 0 Target 9 config */
448 UCHAR Target0AConfig; /* 20 - Channel 0 Target A config */
449 UCHAR Target0BConfig; /* 21 - Channel 0 Target B config */
450 UCHAR Target0CConfig; /* 22 - Channel 0 Target C config */
451 UCHAR Target0DConfig; /* 23 - Channel 0 Target D config */
452 UCHAR Target0EConfig; /* 24 - Channel 0 Target E config */
453 UCHAR Target0FConfig; /* 25 - Channel 0 Target F config */
455 UCHAR SCSI1Id; /* 26 - Channel 1 SCSI ID */
456 UCHAR SCSI1Config; /* 27 - Channel 1 SCSI configuration */
457 UCHAR SCSI1MaxTags; /* 28 - Channel 1 Maximum tags */
458 UCHAR SCSI1ResetTime; /* 29 - Channel 1 Reset recovering time */
459 UCHAR ReservedforChannel1[2]; /* 2A - Reserved */
461 /* ----SCSI target Structure ---- */
462 /* from "CTRL-I SCSI device SetUp menu " */
463 UCHAR Target10Config; /* 2C - Channel 1 Target 0 config */
464 UCHAR Target11Config; /* 2D - Channel 1 Target 1 config */
465 UCHAR Target12Config; /* 2E - Channel 1 Target 2 config */
466 UCHAR Target13Config; /* 2F - Channel 1 Target 3 config */
467 UCHAR Target14Config; /* 30 - Channel 1 Target 4 config */
468 UCHAR Target15Config; /* 31 - Channel 1 Target 5 config */
469 UCHAR Target16Config; /* 32 - Channel 1 Target 6 config */
470 UCHAR Target17Config; /* 33 - Channel 1 Target 7 config */
471 UCHAR Target18Config; /* 34 - Channel 1 Target 8 config */
472 UCHAR Target19Config; /* 35 - Channel 1 Target 9 config */
473 UCHAR Target1AConfig; /* 36 - Channel 1 Target A config */
474 UCHAR Target1BConfig; /* 37 - Channel 1 Target B config */
475 UCHAR Target1CConfig; /* 38 - Channel 1 Target C config */
476 UCHAR Target1DConfig; /* 39 - Channel 1 Target D config */
477 UCHAR Target1EConfig; /* 3A - Channel 1 Target E config */
478 UCHAR Target1FConfig; /* 3B - Channel 1 Target F config */
479 UCHAR reserved[3]; /* 3C - Reserved */
480 /* ---------- CheckSum ---------- */
481 UCHAR CheckSum; /* 3F - Checksum of NVRam */
484 /* Bios Configuration for nvram->BIOSConfig1 */
485 #define NBC_BIOSENABLE 0x01 /* BIOS enable */
486 #define NBC_CDROM 0x02 /* Support bootable CDROM */
487 #define NBC_REMOVABLE 0x04 /* Support removable drive */
489 /* Bios Configuration for nvram->BIOSConfig2 */
490 #define NBB_TARGET_MASK 0x0F /* Boot SCSI target ID number */
491 #define NBB_CHANL_MASK 0xF0 /* Boot SCSI channel number */
493 /* Bit definition for nvram->SCSIConfig */
494 #define NCC_BUSRESET 0x01 /* Reset SCSI bus at power up */
495 #define NCC_PARITYCHK 0x02 /* SCSI parity enable */
496 #define NCC_LVDS 0x10 /* Enable LVDS */
497 #define NCC_ACTTERM1 0x20 /* Enable active terminator 1 */
498 #define NCC_ACTTERM2 0x40 /* Enable active terminator 2 */
499 #define NCC_AUTOTERM 0x80 /* Enable auto termination */
501 /* Bit definition for nvram->TargetxConfig */
502 #define NTC_PERIOD 0x07 /* Maximum Sync. Speed */
503 #define NTC_1GIGA 0x08 /* 255 head / 63 sectors (64/32) */
504 #define NTC_NO_SYNC 0x10 /* NO SYNC. NEGO */
505 #define NTC_NO_WIDESYNC 0x20 /* NO WIDE SYNC. NEGO */
506 #define NTC_DISC_ENABLE 0x40 /* Enable SCSI disconnect */
507 #define NTC_SPINUP 0x80 /* Start disk drive */
509 /* Default NVRam values */
510 #define NBC_DEFAULT (NBC_ENABLE)
511 #define NCC_DEFAULT (NCC_BUSRESET | NCC_AUTOTERM | NCC_PARITYCHK)
512 #define NCC_MAX_TAGS 0x20 /* Maximum tags per target */
513 #define NCC_RESET_TIME 0x0A /* SCSI RESET recovering time */
514 #define NTC_DEFAULT (NTC_1GIGA | NTC_NO_WIDESYNC | NTC_DISC_ENABLE)
516 typedef union { /* Union define for mechanism 1 */
518 unsigned char RegNum;
519 unsigned char FcnNum:3;
520 unsigned char DeviceNum:5;
521 unsigned char BusNum;
522 unsigned char Reserved:7;
523 unsigned char Enable:1;
525 unsigned long lConfigAdr;
528 typedef union { /* Union define for mechanism 2 */
530 unsigned char RegNum;
531 unsigned char DeviceNum;
532 unsigned short Reserved;
534 unsigned long lHostAdr;
537 #define ORC_RD(x,y) (UCHAR)(inb( (int)((ULONG)((ULONG)x+(UCHAR)y)) ))
538 #define ORC_RDLONG(x,y) (long)(inl((int)((ULONG)((ULONG)x+(UCHAR)y)) ))
540 #define ORC_WR( adr,data) outb( (UCHAR)(data), (int)(adr))
541 #define ORC_WRSHORT(adr,data) outw( (UWORD)(data), (int)(adr))
542 #define ORC_WRLONG( adr,data) outl( (ULONG)(data), (int)(adr))
545 #define SCSI_ABORT_SNOOZE 0
546 #define SCSI_ABORT_SUCCESS 1
547 #define SCSI_ABORT_PENDING 2
548 #define SCSI_ABORT_BUSY 3
549 #define SCSI_ABORT_NOT_RUNNING 4
550 #define SCSI_ABORT_ERROR 5
552 #define SCSI_RESET_SNOOZE 0
553 #define SCSI_RESET_PUNT 1
554 #define SCSI_RESET_SUCCESS 2
555 #define SCSI_RESET_PENDING 3
556 #define SCSI_RESET_WAKEUP 4
557 #define SCSI_RESET_NOT_RUNNING 5
558 #define SCSI_RESET_ERROR 6
560 #define SCSI_RESET_SYNCHRONOUS 0x01
561 #define SCSI_RESET_ASYNCHRONOUS 0x02
562 #define SCSI_RESET_SUGGEST_BUS_RESET 0x04
563 #define SCSI_RESET_SUGGEST_HOST_RESET 0x08
565 #define SCSI_RESET_BUS_RESET 0x100
566 #define SCSI_RESET_HOST_RESET 0x200
567 #define SCSI_RESET_ACTION 0xff