1 /*****************************************************************************/
2 /* ips.h -- driver for the Adaptec / IBM ServeRAID controller */
4 /* Written By: Keith Mitchell, IBM Corporation */
5 /* Jack Hammer, Adaptec, Inc. */
6 /* David Jeffery, Adaptec, Inc. */
8 /* Copyright (C) 1999 IBM Corporation */
9 /* Copyright (C) 2003 Adaptec, Inc. */
11 /* This program is free software; you can redistribute it and/or modify */
12 /* it under the terms of the GNU General Public License as published by */
13 /* the Free Software Foundation; either version 2 of the License, or */
14 /* (at your option) any later version. */
16 /* This program is distributed in the hope that it will be useful, */
17 /* but WITHOUT ANY WARRANTY; without even the implied warranty of */
18 /* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */
19 /* GNU General Public License for more details. */
22 /* THE PROGRAM IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR */
23 /* CONDITIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED INCLUDING, WITHOUT */
24 /* LIMITATION, ANY WARRANTIES OR CONDITIONS OF TITLE, NON-INFRINGEMENT, */
25 /* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE. Each Recipient is */
26 /* solely responsible for determining the appropriateness of using and */
27 /* distributing the Program and assumes all risks associated with its */
28 /* exercise of rights under this Agreement, including but not limited to */
29 /* the risks and costs of program errors, damage to or loss of data, */
30 /* programs or equipment, and unavailability or interruption of operations. */
32 /* DISCLAIMER OF LIABILITY */
33 /* NEITHER RECIPIENT NOR ANY CONTRIBUTORS SHALL HAVE ANY LIABILITY FOR ANY */
34 /* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL */
35 /* DAMAGES (INCLUDING WITHOUT LIMITATION LOST PROFITS), HOWEVER CAUSED AND */
36 /* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR */
37 /* TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE */
38 /* USE OR DISTRIBUTION OF THE PROGRAM OR THE EXERCISE OF ANY RIGHTS GRANTED */
39 /* HEREUNDER, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGES */
41 /* You should have received a copy of the GNU General Public License */
42 /* along with this program; if not, write to the Free Software */
43 /* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA */
45 /* Bugs/Comments/Suggestions should be mailed to: */
46 /* ipslinux@adaptec.com */
48 /*****************************************************************************/
53 #include <asm/uaccess.h>
57 extern int ips_detect(Scsi_Host_Template *);
58 extern int ips_release(struct Scsi_Host *);
59 extern int ips_eh_abort(Scsi_Cmnd *);
60 extern int ips_eh_reset(Scsi_Cmnd *);
61 extern int ips_queue(Scsi_Cmnd *, void (*) (Scsi_Cmnd *));
62 extern const char * ips_info(struct Scsi_Host *);
67 #if LINUX_VERSION_CODE >= KERNEL_VERSION(2,4,20) || defined CONFIG_HIGHIO
71 #define IPS_HA(x) ((ips_ha_t *) x->hostdata)
72 #define IPS_COMMAND_ID(ha, scb) (int) (scb - ha->scbs)
73 #define IPS_IS_TROMBONE(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
74 (ha->revision_id >= IPS_REVID_TROMBONE32) && \
75 (ha->revision_id <= IPS_REVID_TROMBONE64)) ? 1 : 0)
76 #define IPS_IS_CLARINET(ha) (((ha->device_id == IPS_DEVICEID_COPPERHEAD) && \
77 (ha->revision_id >= IPS_REVID_CLARINETP1) && \
78 (ha->revision_id <= IPS_REVID_CLARINETP3)) ? 1 : 0)
79 #define IPS_IS_MORPHEUS(ha) (ha->device_id == IPS_DEVICEID_MORPHEUS)
80 #define IPS_IS_MARCO(ha) (ha->device_id == IPS_DEVICEID_MARCO)
81 #define IPS_USE_I2O_DELIVER(ha) ((IPS_IS_MORPHEUS(ha) || \
82 (IPS_IS_TROMBONE(ha) && \
83 (ips_force_i2o))) ? 1 : 0)
84 #define IPS_USE_MEMIO(ha) ((IPS_IS_MORPHEUS(ha) || \
85 ((IPS_IS_TROMBONE(ha) || IPS_IS_CLARINET(ha)) && \
86 (ips_force_memio))) ? 1 : 0)
88 #define IPS_HAS_ENH_SGLIST(ha) (IPS_IS_MORPHEUS(ha) || IPS_IS_MARCO(ha))
89 #define IPS_USE_ENH_SGLIST(ha) ((ha)->flags & IPS_HA_ENH_SG)
90 #define IPS_SGLIST_SIZE(ha) (IPS_USE_ENH_SGLIST(ha) ? \
91 sizeof(IPS_ENH_SG_LIST) : sizeof(IPS_STD_SG_LIST))
93 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,4,4)
94 #define pci_set_dma_mask(dev,mask) ( mask > 0xffffffff ? 1:0 )
95 #define scsi_set_pci_device(sh,dev) (0)
99 typedef void irqreturn_t;
102 #define IRQ_RETVAL(x)
104 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
105 #define IPS_REGISTER_HOSTS(SHT) scsi_register_module(MODULE_SCSI_HA,SHT)
106 #define IPS_UNREGISTER_HOSTS(SHT) scsi_unregister_module(MODULE_SCSI_HA,SHT)
107 #define IPS_ADD_HOST(shost,device)
108 #define IPS_REMOVE_HOST(shost)
109 #define IPS_SCSI_SET_DEVICE(sh,ha) scsi_set_pci_device(sh, (ha)->pcidev)
110 #define IPS_PRINTK(level, pcidev, format, arg...) \
111 printk(level "%s %s:" format , "ips" , \
112 (pcidev)->slot_name , ## arg)
113 #define scsi_host_alloc(sh,size) scsi_register(sh,size)
114 #define scsi_host_put(sh) scsi_unregister(sh)
116 #define IPS_REGISTER_HOSTS(SHT) (!ips_detect(SHT))
117 #define IPS_UNREGISTER_HOSTS(SHT)
118 #define IPS_ADD_HOST(shost,device) do { scsi_add_host(shost,device); scsi_scan_host(shost); } while (0)
119 #define IPS_REMOVE_HOST(shost) scsi_remove_host(shost)
120 #define IPS_SCSI_SET_DEVICE(sh,ha) scsi_set_device(sh, &(ha)->pcidev->dev)
121 #define IPS_PRINTK(level, pcidev, format, arg...) \
122 dev_printk(level , &((pcidev)->dev) , format , ## arg)
126 #define MDELAY mdelay
130 #define min(x,y) ((x) < (y) ? x : y)
133 #define pci_dma_hi32(a) ((a >> 16) >> 16)
134 #define pci_dma_lo32(a) (a & 0xffffffff)
136 #if (BITS_PER_LONG > 32) || (defined CONFIG_HIGHMEM64G && defined IPS_HIGHIO)
137 #define IPS_ENABLE_DMA64 (1)
139 #define IPS_ENABLE_DMA64 (0)
143 * Adapter address map equates
145 #define IPS_REG_HISR 0x08 /* Host Interrupt Status Reg */
146 #define IPS_REG_CCSAR 0x10 /* Cmd Channel System Addr Reg */
147 #define IPS_REG_CCCR 0x14 /* Cmd Channel Control Reg */
148 #define IPS_REG_SQHR 0x20 /* Status Q Head Reg */
149 #define IPS_REG_SQTR 0x24 /* Status Q Tail Reg */
150 #define IPS_REG_SQER 0x28 /* Status Q End Reg */
151 #define IPS_REG_SQSR 0x2C /* Status Q Start Reg */
152 #define IPS_REG_SCPR 0x05 /* Subsystem control port reg */
153 #define IPS_REG_ISPR 0x06 /* interrupt status port reg */
154 #define IPS_REG_CBSP 0x07 /* CBSP register */
155 #define IPS_REG_FLAP 0x18 /* Flash address port */
156 #define IPS_REG_FLDP 0x1C /* Flash data port */
157 #define IPS_REG_NDAE 0x38 /* Anaconda 64 NDAE Register */
158 #define IPS_REG_I2O_INMSGQ 0x40 /* I2O Inbound Message Queue */
159 #define IPS_REG_I2O_OUTMSGQ 0x44 /* I2O Outbound Message Queue */
160 #define IPS_REG_I2O_HIR 0x30 /* I2O Interrupt Status */
161 #define IPS_REG_I960_IDR 0x20 /* i960 Inbound Doorbell */
162 #define IPS_REG_I960_MSG0 0x18 /* i960 Outbound Reg 0 */
163 #define IPS_REG_I960_MSG1 0x1C /* i960 Outbound Reg 1 */
164 #define IPS_REG_I960_OIMR 0x34 /* i960 Oubound Int Mask Reg */
167 * Adapter register bit equates
169 #define IPS_BIT_GHI 0x04 /* HISR General Host Interrupt */
170 #define IPS_BIT_SQO 0x02 /* HISR Status Q Overflow */
171 #define IPS_BIT_SCE 0x01 /* HISR Status Channel Enqueue */
172 #define IPS_BIT_SEM 0x08 /* CCCR Semaphore Bit */
173 #define IPS_BIT_ILE 0x10 /* CCCR ILE Bit */
174 #define IPS_BIT_START_CMD 0x101A /* CCCR Start Command Channel */
175 #define IPS_BIT_START_STOP 0x0002 /* CCCR Start/Stop Bit */
176 #define IPS_BIT_RST 0x80 /* SCPR Reset Bit */
177 #define IPS_BIT_EBM 0x02 /* SCPR Enable Bus Master */
178 #define IPS_BIT_EI 0x80 /* HISR Enable Interrupts */
179 #define IPS_BIT_OP 0x01 /* OP bit in CBSP */
180 #define IPS_BIT_I2O_OPQI 0x08 /* General Host Interrupt */
181 #define IPS_BIT_I960_MSG0I 0x01 /* Message Register 0 Interrupt*/
182 #define IPS_BIT_I960_MSG1I 0x02 /* Message Register 1 Interrupt*/
185 * Adapter Command ID Equates
187 #define IPS_CMD_GET_LD_INFO 0x19
188 #define IPS_CMD_GET_SUBSYS 0x40
189 #define IPS_CMD_READ_CONF 0x38
190 #define IPS_CMD_RW_NVRAM_PAGE 0xBC
191 #define IPS_CMD_READ 0x02
192 #define IPS_CMD_WRITE 0x03
193 #define IPS_CMD_FFDC 0xD7
194 #define IPS_CMD_ENQUIRY 0x05
195 #define IPS_CMD_FLUSH 0x0A
196 #define IPS_CMD_READ_SG 0x82
197 #define IPS_CMD_WRITE_SG 0x83
198 #define IPS_CMD_DCDB 0x04
199 #define IPS_CMD_DCDB_SG 0x84
200 #define IPS_CMD_EXTENDED_DCDB 0x95
201 #define IPS_CMD_EXTENDED_DCDB_SG 0x96
202 #define IPS_CMD_CONFIG_SYNC 0x58
203 #define IPS_CMD_ERROR_TABLE 0x17
204 #define IPS_CMD_DOWNLOAD 0x20
205 #define IPS_CMD_RW_BIOSFW 0x22
206 #define IPS_CMD_GET_VERSION_INFO 0xC6
207 #define IPS_CMD_RESET_CHANNEL 0x1A
213 #define IPS_POCL 0x30
214 #define IPS_NORM_STATE 0x00
215 #define IPS_MAX_ADAPTER_TYPES 3
216 #define IPS_MAX_ADAPTERS 16
217 #define IPS_MAX_IOCTL 1
218 #define IPS_MAX_IOCTL_QUEUE 8
219 #define IPS_MAX_QUEUE 128
220 #define IPS_BLKSIZE 512
221 #define IPS_MAX_SG 17
223 #define IPS_MAX_CHANNELS 4
224 #define IPS_MAX_TARGETS 15
225 #define IPS_MAX_CHUNKS 16
226 #define IPS_MAX_CMDS 128
227 #define IPS_MAX_XFER 0x10000
228 #define IPS_NVRAM_P5_SIG 0xFFDDBB99
229 #define IPS_MAX_POST_BYTES 0x02
230 #define IPS_MAX_CONFIG_BYTES 0x02
231 #define IPS_GOOD_POST_STATUS 0x80
232 #define IPS_SEM_TIMEOUT 2000
233 #define IPS_IOCTL_COMMAND 0x0D
234 #define IPS_INTR_ON 0
235 #define IPS_INTR_IORL 1
237 #define IPS_ADAPTER_ID 0xF
238 #define IPS_VENDORID_IBM 0x1014
239 #define IPS_VENDORID_ADAPTEC 0x9005
240 #define IPS_DEVICEID_COPPERHEAD 0x002E
241 #define IPS_DEVICEID_MORPHEUS 0x01BD
242 #define IPS_DEVICEID_MARCO 0x0250
243 #define IPS_SUBDEVICEID_4M 0x01BE
244 #define IPS_SUBDEVICEID_4L 0x01BF
245 #define IPS_SUBDEVICEID_4MX 0x0208
246 #define IPS_SUBDEVICEID_4LX 0x020E
247 #define IPS_SUBDEVICEID_5I2 0x0259
248 #define IPS_SUBDEVICEID_5I1 0x0258
249 #define IPS_SUBDEVICEID_6M 0x0279
250 #define IPS_SUBDEVICEID_6I 0x028C
251 #define IPS_SUBDEVICEID_7k 0x028E
252 #define IPS_SUBDEVICEID_7M 0x028F
253 #define IPS_IOCTL_SIZE 8192
254 #define IPS_STATUS_SIZE 4
255 #define IPS_STATUS_Q_SIZE (IPS_MAX_CMDS+1) * IPS_STATUS_SIZE
256 #define IPS_IMAGE_SIZE 500 * 1024
257 #define IPS_MEMMAP_SIZE 128
258 #define IPS_ONE_MSEC 1
259 #define IPS_ONE_SEC 1000
264 #define IPS_COMP_HEADS 128
265 #define IPS_COMP_SECTORS 32
266 #define IPS_NORM_HEADS 254
267 #define IPS_NORM_SECTORS 63
270 * Adapter Basic Status Codes
272 #define IPS_BASIC_STATUS_MASK 0xFF
273 #define IPS_GSC_STATUS_MASK 0x0F
274 #define IPS_CMD_SUCCESS 0x00
275 #define IPS_CMD_RECOVERED_ERROR 0x01
276 #define IPS_INVAL_OPCO 0x03
277 #define IPS_INVAL_CMD_BLK 0x04
278 #define IPS_INVAL_PARM_BLK 0x05
279 #define IPS_BUSY 0x08
280 #define IPS_CMD_CMPLT_WERROR 0x0C
281 #define IPS_LD_ERROR 0x0D
282 #define IPS_CMD_TIMEOUT 0x0E
283 #define IPS_PHYS_DRV_ERROR 0x0F
286 * Adapter Extended Status Equates
288 #define IPS_ERR_SEL_TO 0xF0
289 #define IPS_ERR_OU_RUN 0xF2
290 #define IPS_ERR_HOST_RESET 0xF7
291 #define IPS_ERR_DEV_RESET 0xF8
292 #define IPS_ERR_RECOVERY 0xFC
293 #define IPS_ERR_CKCOND 0xFF
296 * Operating System Defines
298 #define IPS_OS_WINDOWS_NT 0x01
299 #define IPS_OS_NETWARE 0x02
300 #define IPS_OS_OPENSERVER 0x03
301 #define IPS_OS_UNIXWARE 0x04
302 #define IPS_OS_SOLARIS 0x05
303 #define IPS_OS_OS2 0x06
304 #define IPS_OS_LINUX 0x07
305 #define IPS_OS_FREEBSD 0x08
308 * Adapter Revision ID's
310 #define IPS_REVID_SERVERAID 0x02
311 #define IPS_REVID_NAVAJO 0x03
312 #define IPS_REVID_SERVERAID2 0x04
313 #define IPS_REVID_CLARINETP1 0x05
314 #define IPS_REVID_CLARINETP2 0x07
315 #define IPS_REVID_CLARINETP3 0x0D
316 #define IPS_REVID_TROMBONE32 0x0F
317 #define IPS_REVID_TROMBONE64 0x10
320 * NVRAM Page 5 Adapter Defines
322 #define IPS_ADTYPE_SERVERAID 0x01
323 #define IPS_ADTYPE_SERVERAID2 0x02
324 #define IPS_ADTYPE_NAVAJO 0x03
325 #define IPS_ADTYPE_KIOWA 0x04
326 #define IPS_ADTYPE_SERVERAID3 0x05
327 #define IPS_ADTYPE_SERVERAID3L 0x06
328 #define IPS_ADTYPE_SERVERAID4H 0x07
329 #define IPS_ADTYPE_SERVERAID4M 0x08
330 #define IPS_ADTYPE_SERVERAID4L 0x09
331 #define IPS_ADTYPE_SERVERAID4MX 0x0A
332 #define IPS_ADTYPE_SERVERAID4LX 0x0B
333 #define IPS_ADTYPE_SERVERAID5I2 0x0C
334 #define IPS_ADTYPE_SERVERAID5I1 0x0D
335 #define IPS_ADTYPE_SERVERAID6M 0x0E
336 #define IPS_ADTYPE_SERVERAID6I 0x0F
337 #define IPS_ADTYPE_SERVERAID7t 0x10
338 #define IPS_ADTYPE_SERVERAID7k 0x11
339 #define IPS_ADTYPE_SERVERAID7M 0x12
342 * Adapter Command/Status Packet Definitions
344 #define IPS_SUCCESS 0x01 /* Successfully completed */
345 #define IPS_SUCCESS_IMM 0x02 /* Success - Immediately */
346 #define IPS_FAILURE 0x04 /* Completed with Error */
349 * Logical Drive Equates
351 #define IPS_LD_OFFLINE 0x02
352 #define IPS_LD_OKAY 0x03
353 #define IPS_LD_FREE 0x00
354 #define IPS_LD_SYS 0x06
355 #define IPS_LD_CRS 0x24
360 #define IPS_NO_DISCONNECT 0x00
361 #define IPS_DISCONNECT_ALLOWED 0x80
362 #define IPS_NO_AUTO_REQSEN 0x40
363 #define IPS_DATA_NONE 0x00
364 #define IPS_DATA_UNK 0x00
365 #define IPS_DATA_IN 0x01
366 #define IPS_DATA_OUT 0x02
367 #define IPS_TRANSFER64K 0x08
368 #define IPS_NOTIMEOUT 0x00
369 #define IPS_TIMEOUT10 0x10
370 #define IPS_TIMEOUT60 0x20
371 #define IPS_TIMEOUT20M 0x30
374 * SCSI Inquiry Data Flags
376 #define IPS_SCSI_INQ_TYPE_DASD 0x00
377 #define IPS_SCSI_INQ_TYPE_PROCESSOR 0x03
378 #define IPS_SCSI_INQ_LU_CONNECTED 0x00
379 #define IPS_SCSI_INQ_RD_REV2 0x02
380 #define IPS_SCSI_INQ_REV2 0x02
381 #define IPS_SCSI_INQ_REV3 0x03
382 #define IPS_SCSI_INQ_Address16 0x01
383 #define IPS_SCSI_INQ_Address32 0x02
384 #define IPS_SCSI_INQ_MedChanger 0x08
385 #define IPS_SCSI_INQ_MultiPort 0x10
386 #define IPS_SCSI_INQ_EncServ 0x40
387 #define IPS_SCSI_INQ_SoftReset 0x01
388 #define IPS_SCSI_INQ_CmdQue 0x02
389 #define IPS_SCSI_INQ_Linked 0x08
390 #define IPS_SCSI_INQ_Sync 0x10
391 #define IPS_SCSI_INQ_WBus16 0x20
392 #define IPS_SCSI_INQ_WBus32 0x40
393 #define IPS_SCSI_INQ_RelAdr 0x80
396 * SCSI Request Sense Data Flags
398 #define IPS_SCSI_REQSEN_VALID 0x80
399 #define IPS_SCSI_REQSEN_CURRENT_ERR 0x70
400 #define IPS_SCSI_REQSEN_NO_SENSE 0x00
403 * SCSI Mode Page Equates
405 #define IPS_SCSI_MP3_SoftSector 0x01
406 #define IPS_SCSI_MP3_HardSector 0x02
407 #define IPS_SCSI_MP3_Removeable 0x04
408 #define IPS_SCSI_MP3_AllocateSurface 0x08
414 #define IPS_HA_ENH_SG 0x1
419 #define IPS_SCB_MAP_SG 0x00008
420 #define IPS_SCB_MAP_SINGLE 0X00010
425 #define IPS_COPPUSRCMD (('C'<<8) | 65)
426 #define IPS_COPPIOCCMD (('C'<<8) | 66)
427 #define IPS_NUMCTRLS (('C'<<8) | 68)
428 #define IPS_CTRLINFO (('C'<<8) | 69)
430 /* flashing defines */
431 #define IPS_FW_IMAGE 0x00
432 #define IPS_BIOS_IMAGE 0x01
433 #define IPS_WRITE_FW 0x01
434 #define IPS_WRITE_BIOS 0x02
435 #define IPS_ERASE_BIOS 0x03
436 #define IPS_BIOS_HEADER 0xC0
438 /* time oriented stuff */
439 #define IPS_IS_LEAP_YEAR(y) (((y % 4 == 0) && ((y % 100 != 0) || (y % 400 == 0))) ? 1 : 0)
440 #define IPS_NUM_LEAP_YEARS_THROUGH(y) ((y) / 4 - (y) / 100 + (y) / 400)
442 #define IPS_SECS_MIN 60
443 #define IPS_SECS_HOUR 3600
444 #define IPS_SECS_8HOURS 28800
445 #define IPS_SECS_DAY 86400
446 #define IPS_DAYS_NORMAL_YEAR 365
447 #define IPS_DAYS_LEAP_YEAR 366
448 #define IPS_EPOCH_YEAR 1970
453 #if LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)
454 static int ips_proc24_info(char *, char **, off_t, int, int, int);
455 static void ips_select_queue_depth(struct Scsi_Host *, Scsi_Device *);
456 static int ips_biosparam(Disk *disk, kdev_t dev, int geom[]);
458 int ips_proc_info(struct Scsi_Host *, char *, char **, off_t, int, int);
459 static int ips_biosparam(struct scsi_device *sdev, struct block_device *bdev,
460 sector_t capacity, int geom[]);
461 int ips_slave_configure(Scsi_Device *SDptr);
465 * Raid Command Formats
474 uint16_t sector_count;
479 } IPS_IO_CMD, *PIPS_IO_CMD;
486 uint32_t buffer_addr;
490 } IPS_LD_CMD, *PIPS_LD_CMD;
498 uint32_t buffer_addr;
500 } IPS_IOCTL_CMD, *PIPS_IOCTL_CMD;
518 uint8_t adapter_flag;
519 } IPS_RESET_CMD, *PIPS_RESET_CMD;
526 uint32_t dcdb_address;
532 } IPS_DCDB_CMD, *PIPS_DCDB_CMD;
538 uint8_t source_target;
544 } IPS_CS_CMD, *PIPS_CS_CMD;
556 } IPS_US_CMD, *PIPS_US_CMD;
568 } IPS_FC_CMD, *PIPS_FC_CMD;
576 uint32_t buffer_addr;
580 } IPS_STATUS_CMD, *PIPS_STATUS_CMD;
588 uint32_t buffer_addr;
592 } IPS_NVRAM_CMD, *PIPS_NVRAM_CMD;
600 uint32_t buffer_addr;
602 } IPS_VERSION_INFO, *PIPS_VERSION_INFO;
613 uint8_t reserved1[4];
618 } IPS_FFDC_CMD, *PIPS_FFDC_CMD;
626 uint32_t buffer_addr;
627 uint8_t total_packets;
630 } IPS_FLASHFW_CMD, *PIPS_FLASHFW_CMD;
638 uint32_t buffer_addr;
640 } IPS_FLASHBIOS_CMD, *PIPS_FLASHBIOS_CMD;
644 IPS_LD_CMD logical_info;
645 IPS_IOCTL_CMD ioctl_info;
647 IPS_CS_CMD config_sync;
648 IPS_US_CMD unlock_stripe;
649 IPS_FC_CMD flush_cache;
650 IPS_STATUS_CMD status;
653 IPS_FLASHFW_CMD flashfw;
654 IPS_FLASHBIOS_CMD flashbios;
655 IPS_VERSION_INFO version_info;
657 } IPS_HOST_COMMAND, *PIPS_HOST_COMMAND;
664 uint32_t sector_count;
665 } IPS_DRIVE_INFO, *PIPS_DRIVE_INFO;
668 uint8_t no_of_log_drive;
670 IPS_DRIVE_INFO drive_info[IPS_MAX_LD];
671 } IPS_LD_INFO, *PIPS_LD_INFO;
674 uint8_t device_address;
675 uint8_t cmd_attribute;
676 uint16_t transfer_length;
677 uint32_t buffer_pointer;
679 uint8_t sense_length;
682 uint8_t scsi_cdb[12];
683 uint8_t sense_info[64];
685 uint8_t reserved2[3];
686 } IPS_DCDB_TABLE, *PIPS_DCDB_TABLE;
689 uint8_t device_address;
690 uint8_t cmd_attribute;
692 uint8_t reserved_for_LUN;
693 uint32_t transfer_length;
694 uint32_t buffer_pointer;
696 uint8_t sense_length;
699 uint8_t scsi_cdb[16];
700 uint8_t sense_info[56];
701 } IPS_DCDB_TABLE_TAPE, *PIPS_DCDB_TABLE_TAPE;
705 volatile uint8_t reserved;
706 volatile uint8_t command_id;
707 volatile uint8_t basic_status;
708 volatile uint8_t extended_status;
711 volatile uint32_t value;
712 } IPS_STATUS, *PIPS_STATUS;
715 IPS_STATUS status[IPS_MAX_CMDS + 1];
716 volatile PIPS_STATUS p_status_start;
717 volatile PIPS_STATUS p_status_end;
718 volatile PIPS_STATUS p_status_tail;
719 volatile uint32_t hw_status_start;
720 volatile uint32_t hw_status_tail;
721 } IPS_ADAPTER, *PIPS_ADAPTER;
724 uint8_t ucLogDriveCount;
729 uint8_t ucWrongAdrCnt;
730 uint8_t ucUnidentCnt;
731 uint8_t ucNVramDevChgCnt;
732 uint8_t CodeBlkVersion[8];
733 uint8_t BootBlkVersion[8];
734 uint32_t ulDriveSize[IPS_MAX_LD];
735 uint8_t ucConcurrentCmdCount;
736 uint8_t ucMaxPhysicalDevices;
737 uint16_t usFlashRepgmCount;
738 uint8_t ucDefunctDiskCount;
739 uint8_t ucRebuildFlag;
740 uint8_t ucOfflineLogDrvCount;
741 uint8_t ucCriticalDrvCount;
742 uint16_t usConfigUpdateCount;
745 uint16_t usAddrDeadDisk[IPS_MAX_CHANNELS * (IPS_MAX_TARGETS + 1)];
746 } IPS_ENQ, *PIPS_ENQ;
750 uint8_t ucParameters;
753 uint32_t ulBlockCount;
754 uint8_t ucDeviceId[28];
755 } IPS_DEVSTATE, *PIPS_DEVSTATE;
761 uint32_t ulStartSect;
762 uint32_t ulNoOfSects;
763 } IPS_CHUNK, *PIPS_CHUNK;
766 uint16_t ucUserField;
768 uint8_t ucRaidCacheParam;
769 uint8_t ucNoOfChunkUnits;
770 uint8_t ucStripeSize;
773 uint32_t ulLogDrvSize;
774 IPS_CHUNK chunk[IPS_MAX_CHUNKS];
778 uint8_t board_disc[8];
779 uint8_t processor[8];
780 uint8_t ucNoChanType;
781 uint8_t ucNoHostIntType;
782 uint8_t ucCompression;
784 uint32_t ulNvramSize;
785 } IPS_HARDWARE, *PIPS_HARDWARE;
788 uint8_t ucLogDriveCount;
794 uint8_t time_sign[8];
797 uint8_t ucRebuildRate;
799 IPS_HARDWARE hardware_disc;
800 IPS_LD logical_drive[IPS_MAX_LD];
801 IPS_DEVSTATE dev[IPS_MAX_CHANNELS][IPS_MAX_TARGETS+1];
802 uint8_t reserved[512];
803 } IPS_CONF, *PIPS_CONF;
808 uint8_t adapter_slot;
809 uint16_t adapter_type;
810 uint8_t ctrl_bios[8];
811 uint8_t versioning; /* 1 = Versioning Supported, else 0 */
812 uint8_t version_mismatch; /* 1 = Versioning MisMatch, else 0 */
814 uint8_t operating_system;
815 uint8_t driver_high[4];
816 uint8_t driver_low[4];
817 uint8_t BiosCompatibilityID[8];
818 uint8_t ReservedForOS2[8];
819 uint8_t bios_high[4]; /* Adapter's Flashed BIOS Version */
821 uint8_t adapter_order[16]; /* BIOS Telling us the Sort Order */
823 } IPS_NVRAM_P5, *PIPS_NVRAM_P5;
825 /*--------------------------------------------------------------------------*/
826 /* Data returned from a GetVersion Command */
827 /*--------------------------------------------------------------------------*/
829 /* SubSystem Parameter[4] */
830 #define IPS_GET_VERSION_SUPPORT 0x00018000 /* Mask for Versioning Support */
835 uint8_t bootBlkVersion[32];
836 uint8_t bootBlkAttributes[4];
837 uint8_t codeBlkVersion[32];
838 uint8_t biosVersion[32];
839 uint8_t biosAttributes[4];
840 uint8_t compatibilityId[32];
845 typedef struct _IPS_SUBSYS {
847 } IPS_SUBSYS, *PIPS_SUBSYS;
854 * Inquiry Data Format
858 uint8_t DeviceTypeQualifier;
860 uint8_t ResponseDataFormat;
861 uint8_t AdditionalLength;
865 uint8_t ProductId[16];
866 uint8_t ProductRevisionLevel[4];
867 uint8_t Reserved2; /* Provides NULL terminator to name */
868 } IPS_SCSI_INQ_DATA, *PIPS_SCSI_INQ_DATA;
871 * Read Capacity Data Format
879 * Request Sense Data Format
882 uint8_t ResponseCode;
883 uint8_t SegmentNumber;
885 uint8_t Information[4];
886 uint8_t AdditionalLength;
887 uint8_t CommandSpecific[4];
888 uint8_t AdditionalSenseCode;
889 uint8_t AdditionalSenseCodeQual;
891 uint8_t SenseKeySpecific[3];
895 * Sense Data Format - Page 3
900 uint16_t TracksPerZone;
901 uint16_t AltSectorsPerZone;
902 uint16_t AltTracksPerZone;
903 uint16_t AltTracksPerVolume;
904 uint16_t SectorsPerTrack;
905 uint16_t BytesPerSector;
908 uint16_t CylinderSkew;
911 } IPS_SCSI_MODE_PAGE3;
914 * Sense Data Format - Page 4
919 uint16_t CylindersHigh;
920 uint8_t CylindersLow;
922 uint16_t WritePrecompHigh;
923 uint8_t WritePrecompLow;
924 uint16_t ReducedWriteCurrentHigh;
925 uint8_t ReducedWriteCurrentLow;
927 uint16_t LandingZoneHigh;
928 uint8_t LandingZoneLow;
930 uint8_t RotationalOffset;
932 uint16_t MediumRotationRate;
933 uint8_t Reserved2[2];
934 } IPS_SCSI_MODE_PAGE4;
937 * Sense Data Format - Page 8
944 uint16_t DisPrefetchLen;
945 uint16_t MinPrefetchLen;
946 uint16_t MaxPrefetchLen;
947 uint16_t MaxPrefetchCeiling;
948 } IPS_SCSI_MODE_PAGE8;
951 * Sense Data Format - Block Descriptor (DASD)
954 uint32_t NumberOfBlocks;
956 uint16_t BlockLengthHigh;
957 uint8_t BlockLengthLow;
958 } IPS_SCSI_MODE_PAGE_BLKDESC;
961 * Sense Data Format - Mode Page Header
967 uint8_t BlockDescLength;
968 } IPS_SCSI_MODE_PAGE_HEADER;
971 IPS_SCSI_MODE_PAGE_HEADER hdr;
972 IPS_SCSI_MODE_PAGE_BLKDESC blkdesc;
975 IPS_SCSI_MODE_PAGE3 pg3;
976 IPS_SCSI_MODE_PAGE4 pg4;
977 IPS_SCSI_MODE_PAGE8 pg8;
979 } IPS_SCSI_MODE_PAGE_DATA;
982 * Scatter Gather list format
984 typedef struct ips_sglist {
989 typedef struct ips_enh_sglist {
998 IPS_STD_SG_LIST *std_list;
999 IPS_ENH_SG_LIST *enh_list;
1002 typedef struct _IPS_INFOSTR {
1019 typedef struct ips_stat {
1020 uint32_t residue_len;
1022 uint8_t padding[12 - sizeof(void *)];
1028 typedef struct ips_scb_queue {
1029 struct ips_scb *head;
1030 struct ips_scb *tail;
1037 typedef struct ips_wait_queue {
1043 typedef struct ips_copp_wait_item {
1044 Scsi_Cmnd *scsi_cmd;
1045 struct ips_copp_wait_item *next;
1046 } ips_copp_wait_item_t;
1048 typedef struct ips_copp_queue {
1049 struct ips_copp_wait_item *head;
1050 struct ips_copp_wait_item *tail;
1054 /* forward decl for host structure */
1058 int (*reset)(struct ips_ha *);
1059 int (*issue)(struct ips_ha *, struct ips_scb *);
1060 int (*isinit)(struct ips_ha *);
1061 int (*isintr)(struct ips_ha *);
1062 int (*init)(struct ips_ha *);
1063 int (*erasebios)(struct ips_ha *);
1064 int (*programbios)(struct ips_ha *, char *, uint32_t, uint32_t);
1065 int (*verifybios)(struct ips_ha *, char *, uint32_t, uint32_t);
1066 void (*statinit)(struct ips_ha *);
1067 int (*intr)(struct ips_ha *);
1068 void (*enableint)(struct ips_ha *);
1069 uint32_t (*statupd)(struct ips_ha *);
1072 typedef struct ips_ha {
1073 uint8_t ha_id[IPS_MAX_CHANNELS+1];
1074 uint32_t dcdb_active[IPS_MAX_CHANNELS];
1075 uint32_t io_addr; /* Base I/O address */
1076 uint8_t irq; /* IRQ for adapter */
1077 uint8_t ntargets; /* Number of targets */
1078 uint8_t nbus; /* Number of buses */
1079 uint8_t nlun; /* Number of Luns */
1080 uint16_t ad_type; /* Adapter type */
1081 uint16_t host_num; /* Adapter number */
1082 uint32_t max_xfer; /* Maximum Xfer size */
1083 uint32_t max_cmds; /* Max concurrent commands */
1084 uint32_t num_ioctl; /* Number of Ioctls */
1085 ips_stat_t sp; /* Status packer pointer */
1086 struct ips_scb *scbs; /* Array of all CCBS */
1087 struct ips_scb *scb_freelist; /* SCB free list */
1088 ips_wait_queue_t scb_waitlist; /* Pending SCB list */
1089 ips_copp_queue_t copp_waitlist; /* Pending PT list */
1090 ips_scb_queue_t scb_activelist; /* Active SCB list */
1091 IPS_IO_CMD *dummy; /* dummy command */
1092 IPS_ADAPTER *adapt; /* Adapter status area */
1093 IPS_LD_INFO *logical_drive_info; /* Adapter Logical Drive Info */
1094 dma_addr_t logical_drive_info_dma_addr; /* Logical Drive Info DMA Address */
1095 IPS_ENQ *enq; /* Adapter Enquiry data */
1096 IPS_CONF *conf; /* Adapter config data */
1097 IPS_NVRAM_P5 *nvram; /* NVRAM page 5 data */
1098 IPS_SUBSYS *subsys; /* Subsystem parameters */
1099 char *ioctl_data; /* IOCTL data area */
1100 uint32_t ioctl_datasize; /* IOCTL data size */
1101 uint32_t cmd_in_progress; /* Current command in progress*/
1103 uint8_t waitflag; /* are we waiting for cmd */
1105 int ioctl_reset; /* IOCTL Requested Reset Flag */
1106 uint16_t reset_count; /* number of resets */
1107 time_t last_ffdc; /* last time we sent ffdc info*/
1108 uint8_t revision_id; /* Revision level */
1109 uint16_t device_id; /* PCI device ID */
1110 uint8_t slot_num; /* PCI Slot Number */
1111 uint16_t subdevice_id; /* Subsystem device ID */
1112 int ioctl_len; /* size of ioctl buffer */
1113 dma_addr_t ioctl_busaddr; /* dma address of ioctl buffer*/
1114 uint8_t bios_version[8]; /* BIOS Revision */
1115 uint32_t mem_addr; /* Memory mapped address */
1116 uint32_t io_len; /* Size of IO Address */
1117 uint32_t mem_len; /* Size of memory address */
1118 char *mem_ptr; /* Memory mapped Ptr */
1119 char *ioremap_ptr; /* ioremapped memory pointer */
1120 ips_hw_func_t func; /* hw function pointers */
1121 struct pci_dev *pcidev; /* PCI device handle */
1122 char *flash_data; /* Save Area for flash data */
1123 int flash_len; /* length of flash buffer */
1124 u32 flash_datasize; /* Save Area for flash data size */
1125 dma_addr_t flash_busaddr; /* dma address of flash buffer*/
1126 dma_addr_t enq_busaddr; /* dma address of enq struct */
1127 uint8_t requires_esl; /* Requires an EraseStripeLock */
1130 typedef void (*ips_scb_callback) (ips_ha_t *, struct ips_scb *);
1135 typedef struct ips_scb {
1136 IPS_HOST_COMMAND cmd;
1137 IPS_DCDB_TABLE dcdb;
1142 uint32_t scb_busaddr;
1143 uint32_t old_data_busaddr; // Obsolete, but kept for old utility compatibility
1145 uint8_t basic_status;
1146 uint8_t extended_status;
1153 IPS_SG_LIST sg_list;
1154 Scsi_Cmnd *scsi_cmd;
1155 struct ips_scb *q_next;
1156 ips_scb_callback callback;
1157 uint32_t sg_busaddr;
1159 dma_addr_t data_busaddr;
1162 typedef struct ips_scb_pt {
1163 IPS_HOST_COMMAND cmd;
1164 IPS_DCDB_TABLE dcdb;
1169 uint32_t scb_busaddr;
1170 uint32_t data_busaddr;
1172 uint8_t basic_status;
1173 uint8_t extended_status;
1179 IPS_SG_LIST *sg_list;
1180 Scsi_Cmnd *scsi_cmd;
1181 struct ips_scb *q_next;
1182 ips_scb_callback callback;
1186 * Passthru Command Format
1194 ips_scb_pt_t CoppCP;
1196 uint8_t BasicStatus;
1197 uint8_t ExtendedStatus;
1198 uint8_t AdapterType;
1204 /* The Version Information below gets created by SED during the build process. */
1205 /* Do not modify the next line; it's what SED is looking for to do the insert. */
1207 /*************************************************************************
1209 * VERSION.H -- version numbers and copyright notices in various formats
1211 *************************************************************************/
1213 #define IPS_VER_MAJOR 7
1214 #define IPS_VER_MAJOR_STRING "7"
1215 #define IPS_VER_MINOR 10
1216 #define IPS_VER_MINOR_STRING "10"
1217 #define IPS_VER_BUILD 18
1218 #define IPS_VER_BUILD_STRING "18"
1219 #define IPS_VER_STRING "7.10.18"
1220 #define IPS_RELEASE_ID 0x00020000
1221 #define IPS_BUILD_IDENT 731
1222 #define IPS_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002. All Rights Reserved."
1223 #define IPS_ADAPTECCOPYRIGHT_STRING "(c) Copyright Adaptec, Inc. 2002 to 2004. All Rights Reserved."
1224 #define IPS_DELLCOPYRIGHT_STRING "(c) Copyright Dell 2004. All Rights Reserved."
1225 #define IPS_NT_LEGALCOPYRIGHT_STRING "(C) Copyright IBM Corp. 1994, 2002."
1227 /* Version numbers for various adapters */
1228 #define IPS_VER_SERVERAID1 "2.25.01"
1229 #define IPS_VER_SERVERAID2 "2.88.13"
1230 #define IPS_VER_NAVAJO "2.88.13"
1231 #define IPS_VER_SERVERAID3 "6.10.24"
1232 #define IPS_VER_SERVERAID4H "7.10.11"
1233 #define IPS_VER_SERVERAID4MLx "7.10.18"
1234 #define IPS_VER_SARASOTA "7.10.18"
1235 #define IPS_VER_MARCO "7.10.18"
1236 #define IPS_VER_SEBRING "7.10.18"
1237 #define IPS_VER_KEYWEST "7.10.18"
1239 /* Compatability IDs for various adapters */
1240 #define IPS_COMPAT_UNKNOWN ""
1241 #define IPS_COMPAT_CURRENT "KW710"
1242 #define IPS_COMPAT_SERVERAID1 "2.25.01"
1243 #define IPS_COMPAT_SERVERAID2 "2.88.13"
1244 #define IPS_COMPAT_NAVAJO "2.88.13"
1245 #define IPS_COMPAT_KIOWA "2.88.13"
1246 #define IPS_COMPAT_SERVERAID3H "SB610"
1247 #define IPS_COMPAT_SERVERAID3L "SB610"
1248 #define IPS_COMPAT_SERVERAID4H "KW710"
1249 #define IPS_COMPAT_SERVERAID4M "KW710"
1250 #define IPS_COMPAT_SERVERAID4L "KW710"
1251 #define IPS_COMPAT_SERVERAID4Mx "KW710"
1252 #define IPS_COMPAT_SERVERAID4Lx "KW710"
1253 #define IPS_COMPAT_SARASOTA "KW710"
1254 #define IPS_COMPAT_MARCO "KW710"
1255 #define IPS_COMPAT_SEBRING "KW710"
1256 #define IPS_COMPAT_TAMPA "KW710"
1257 #define IPS_COMPAT_KEYWEST "KW710"
1258 #define IPS_COMPAT_BIOS "KW710"
1260 #define IPS_COMPAT_MAX_ADAPTER_TYPE 18
1261 #define IPS_COMPAT_ID_LENGTH 8
1263 #define IPS_DEFINE_COMPAT_TABLE(tablename) \
1264 char tablename[IPS_COMPAT_MAX_ADAPTER_TYPE] [IPS_COMPAT_ID_LENGTH] = { \
1265 IPS_COMPAT_UNKNOWN, \
1266 IPS_COMPAT_SERVERAID1, \
1267 IPS_COMPAT_SERVERAID2, \
1268 IPS_COMPAT_NAVAJO, \
1270 IPS_COMPAT_SERVERAID3H, \
1271 IPS_COMPAT_SERVERAID3L, \
1272 IPS_COMPAT_SERVERAID4H, \
1273 IPS_COMPAT_SERVERAID4M, \
1274 IPS_COMPAT_SERVERAID4L, \
1275 IPS_COMPAT_SERVERAID4Mx, \
1276 IPS_COMPAT_SERVERAID4Lx, \
1277 IPS_COMPAT_SARASOTA, /* one-channel variety of SARASOTA */ \
1278 IPS_COMPAT_SARASOTA, /* two-channel variety of SARASOTA */ \
1280 IPS_COMPAT_SEBRING, \
1282 IPS_COMPAT_KEYWEST \
1287 * Overrides for Emacs so that we almost follow Linus's tabbing style.
1288 * Emacs will notice this stuff at the end of the file and automatically
1289 * adjust the settings for this buffer only. This must remain at the end
1291 * ---------------------------------------------------------------------------
1294 * c-brace-imaginary-offset: 0
1295 * c-brace-offset: -2
1296 * c-argdecl-indent: 2
1297 * c-label-offset: -2
1298 * c-continued-statement-offset: 2
1299 * c-continued-brace-offset: 0
1300 * indent-tabs-mode: nil