2 * mac53c94.h: definitions for the driver for the 53c94 SCSI bus adaptor
3 * found on Power Macintosh computers, controlling the external SCSI chain.
5 * Copyright (C) 1996 Paul Mackerras.
10 int mac53c94_detect(Scsi_Host_Template *);
11 int mac53c94_release(struct Scsi_Host *);
12 int mac53c94_command(Scsi_Cmnd *);
13 int mac53c94_queue(Scsi_Cmnd *, void (*done)(Scsi_Cmnd *));
14 int mac53c94_abort(Scsi_Cmnd *);
15 int mac53c94_reset(Scsi_Cmnd *, unsigned int);
17 #define SCSI_MAC53C94 { \
20 detect: mac53c94_detect, \
21 release: mac53c94_release, \
22 command: mac53c94_command, \
23 queuecommand: mac53c94_queue, \
24 abort: mac53c94_abort, \
25 reset: mac53c94_reset, \
28 sg_tablesize: SG_ALL, \
30 use_clustering: DISABLE_CLUSTERING, \
35 * Registers in the 53C94 controller.
38 struct mac53c94_regs {
39 unsigned char count_lo;
41 unsigned char count_mid;
45 unsigned char command;
49 unsigned char interrupt;
51 unsigned char seqstep;
55 unsigned char config1;
57 unsigned char clk_factor;
61 unsigned char config2;
63 unsigned char config3;
65 unsigned char config4;
67 unsigned char count_hi;
69 unsigned char fifo_res;
74 * Alternate functions for some registers.
76 #define dest_id status
77 #define sel_timeout interrupt
78 #define sync_period seqstep
79 #define sync_offset flags
82 * Bits in command register.
84 #define CMD_DMA_MODE 0x80
85 #define CMD_MODE_MASK 0x70
86 #define CMD_MODE_INIT 0x10
87 #define CMD_MODE_TARG 0x20
88 #define CMD_MODE_DISC 0x40
93 #define CMD_SCSI_RESET 3
95 #define CMD_XFER_DATA 0x10
96 #define CMD_I_COMPLETE 0x11
97 #define CMD_ACCEPT_MSG 0x12
98 #define CMD_XFER_PAD 0x18
99 #define CMD_SET_ATN 0x1a
100 #define CMD_CLR_ATN 0x1b
102 #define CMD_SEND_MSG 0x20
103 #define CMD_SEND_STATUS 0x21
104 #define CMD_SEND_DATA 0x22
105 #define CMD_DISC_SEQ 0x23
106 #define CMD_TERMINATE 0x24
107 #define CMD_T_COMPLETE 0x25
108 #define CMD_DISCONNECT 0x27
109 #define CMD_RECV_MSG 0x28
110 #define CMD_RECV_CDB 0x29
111 #define CMD_RECV_DATA 0x2a
112 #define CMD_RECV_CMD 0x2b
113 #define CMD_ABORT_DMA 0x04
115 #define CMD_RESELECT 0x40
116 #define CMD_SELECT 0x41
117 #define CMD_SELECT_ATN 0x42
118 #define CMD_SELATN_STOP 0x43
119 #define CMD_ENABLE_SEL 0x44
120 #define CMD_DISABLE_SEL 0x45
121 #define CMD_SEL_ATN3 0x46
122 #define CMD_RESEL_ATN3 0x47
125 * Bits in status register.
127 #define STAT_IRQ 0x80
128 #define STAT_ERROR 0x40
129 #define STAT_PARITY 0x20
130 #define STAT_TC_ZERO 0x10
131 #define STAT_DONE 0x08
132 #define STAT_PHASE 0x07
133 #define STAT_MSG 0x04
138 * Bits in interrupt register.
140 #define INTR_RESET 0x80 /* SCSI bus was reset */
141 #define INTR_ILL_CMD 0x40 /* illegal command */
142 #define INTR_DISCONNECT 0x20 /* we got disconnected */
143 #define INTR_BUS_SERV 0x10 /* bus service requested */
144 #define INTR_DONE 0x08 /* function completed */
145 #define INTR_RESELECTED 0x04 /* we were reselected */
146 #define INTR_SEL_ATN 0x02 /* we were selected, ATN asserted */
147 #define INTR_SELECT 0x01 /* we were selected, ATN negated */
150 * Encoding for the select timeout.
152 #define TIMO_VAL(x) ((x) * 5000 / 7682)
155 * Bits in sequence step register.
158 #define SS_ARB_SEL 0 /* Selection & arbitration complete */
159 #define SS_MSG_SENT 1 /* One message byte sent */
160 #define SS_NOT_CMD 2 /* Not in command phase */
161 #define SS_PHASE_CHG 3 /* Early phase change, cmd bytes lost */
162 #define SS_DONE 4 /* Command was sent OK */
165 * Encoding for sync transfer period.
167 #define SYNCP_MASK 0x1f
172 * Bits in flags register.
174 #define FLAGS_FIFO_LEV 0x1f
175 #define FLAGS_SEQ_STEP 0xe0
178 * Encoding for sync offset.
180 #define SYNCO_MASK 0x0f
181 #define SYNCO_ASS_CTRL 0x30 /* REQ/ACK assertion control */
182 #define SYNCO_NEG_CTRL 0xc0 /* REQ/ACK negation control */
185 * Bits in config1 register.
187 #define CF1_SLOW_CABLE 0x80 /* Slow cable mode */
188 #define CF1_NO_RES_REP 0x40 /* Disable SCSI reset reports */
189 #define CF1_PAR_TEST 0x20 /* Parity test mode enable */
190 #define CF1_PAR_ENABLE 0x10 /* Enable parity checks */
191 #define CF1_TEST 0x08 /* Chip tests */
192 #define CF1_MY_ID 0x07 /* Controller's address on bus */
195 * Encoding for clk_factor register.
198 #define CLKF_VAL(freq) ((((freq) + 4999999) / 5000000) & CLKF_MASK)
201 * Bits in test mode register.
203 #define TEST_TARGET 1 /* target test mode */
204 #define TEST_INITIATOR 2 /* initiator test mode */
205 #define TEST_TRISTATE 4 /* tristate (hi-z) test mode */
208 * Bits in config2 register.
211 #define CF2_FEATURE_EN 0x40 /* enable features / phase latch */
212 #define CF2_BYTECTRL 0x20
213 #define CF2_DREQ_HIZ 0x10
214 #define CF2_SCSI2 0x08
215 #define CF2_PAR_ABORT 0x04 /* bad parity target abort */
216 #define CF2_REG_PARERR 0x02 /* register parity error */
217 #define CF2_DMA_PARERR 0x01 /* DMA parity error */
220 * Bits in the config3 register.
222 #define CF3_ID_MSG_CHK 0x80
223 #define CF3_3B_MSGS 0x40
224 #define CF3_CDB10 0x20
225 #define CF3_FASTSCSI 0x10 /* enable fast SCSI support */
226 #define CF3_FASTCLOCK 0x08
227 #define CF3_SAVERESID 0x04
228 #define CF3_ALT_DMA 0x02
229 #define CF3_THRESH_8 0x01
232 * Bits in the config4 register.
235 #define CF4_TEST 0x02
236 #define CF4_BBTE 0x01
238 #endif /* _MAC53C94_H */