drivers/scsi/nsp32_io.h

   1 /*
   2  * Workbit NinjaSCSI-32Bi/UDE PCI/Cardbus SCSI Host Bus Adapter driver
   3  * I/O routine
   4  *
   5  * This software may be used and distributed according to the terms of
   6  * the GNU General Public License.
   7  */
   8
   9 #ifndef _NSP32_IO_H
  10 #define _NSP32_IO_H
  11
  12 static inline void nsp32_write1(unsigned int  base,
  13                                 unsigned int  index,
  14                                 unsigned char val)
  15 {
  16         outb(val, (base + index));
  17 }
  18
  19 static inline unsigned char nsp32_read1(unsigned int base,
  20                                         unsigned int index)
  21 {
  22         return inb(base + index);
  23 }
  24
  25 static inline void nsp32_write2(unsigned int  base,
  26                                 unsigned int  index,
  27                                 unsigned short val)
  28 {
  29         outw(cpu_to_le16(val), (base + index));
  30 }
  31
  32 static inline unsigned short nsp32_read2(unsigned int base,
  33                                          unsigned int index)
  34 {
  35         return le16_to_cpu(inw(base + index));
  36 }
  37
  38 static inline void nsp32_write4(unsigned int  base,
  39                                 unsigned int  index,
  40                                 unsigned long val)
  41 {
  42         outl(cpu_to_le32(val), (base + index));
  43 }
  44
  45 static inline unsigned long nsp32_read4(unsigned int base,
  46                                         unsigned int index)
  47 {
  48         return le32_to_cpu(inl(base + index));
  49 }
  50
  51 /*==============================================*/
  52
  53 static inline void nsp32_mmio_write1(unsigned long base,
  54                                      unsigned int  index,
  55                                      unsigned char val)
  56 {
  57         volatile unsigned char *ptr;
  58
  59         ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index);
  60
  61         *ptr = val;
  62 }
  63
  64 static inline unsigned char nsp32_mmio_read1(unsigned long base,
  65                                              unsigned int  index)
  66 {
  67         volatile unsigned char *ptr;
  68
  69         ptr = (unsigned char *)(base + NSP32_MMIO_OFFSET + index);
  70
  71         return *ptr;
  72 }
  73
  74 static inline void nsp32_mmio_write2(unsigned long base,
  75                                      unsigned int  index,
  76                                      unsigned short val)
  77 {
  78         volatile unsigned short *ptr;
  79
  80         ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index);
  81
  82         *ptr = cpu_to_le16(val);
  83 }
  84
  85 static inline unsigned short nsp32_mmio_read2(unsigned long base,
  86                                               unsigned int  index)
  87 {
  88         volatile unsigned short *ptr;
  89
  90         //printk(__FUNCTION__ "\n");
  91
  92         ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + index);
  93
  94         return le16_to_cpu(*ptr);
  95 }
  96
  97 static inline void nsp32_mmio_write4(unsigned long base,
  98                                      unsigned int  index,
  99                                      unsigned long val)
 100 {
 101         volatile unsigned long *ptr;
 102
 103         ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index);
 104
 105         *ptr = cpu_to_le32(val);
 106 }
 107
 108 static inline unsigned long nsp32_mmio_read4(unsigned long base,
 109                                              unsigned int  index)
 110 {
 111         volatile unsigned long *ptr;
 112
 113         //printk(__FUNCTION__ "\n");
 114
 115         ptr = (unsigned long *)(base + NSP32_MMIO_OFFSET + index);
 116
 117         return le32_to_cpu(*ptr);
 118 }
 119
 120
 121 /*=============================================*/
 122
 123
 124 static inline unsigned char nsp32_index_read1(unsigned int base,
 125                                               unsigned int reg)
 126 {
 127         outb(reg, base + INDEX_REG);
 128         return inb(base + DATA_REG_LOW);
 129 }
 130
 131 static inline void nsp32_index_write1(unsigned int  base,
 132                                       unsigned int  reg,
 133                                       unsigned char val)
 134 {
 135         outb(reg, base + INDEX_REG);
 136         outb(val, base + DATA_REG_LOW);
 137 }
 138
 139 static inline unsigned short nsp32_index_read2(unsigned int base,
 140                                                unsigned int reg)
 141 {
 142         outb(reg, base + INDEX_REG);
 143         return le16_to_cpu(inw(base + DATA_REG_LOW));
 144 }
 145
 146 static inline void nsp32_index_write2(unsigned int  base,
 147                                       unsigned int  reg,
 148                                       unsigned short val)
 149 {
 150         outb(reg, base + INDEX_REG);
 151         outw(cpu_to_le16(val), base + DATA_REG_LOW);
 152 }
 153
 154 static inline unsigned long nsp32_index_read4(unsigned int base,
 155                                               unsigned int reg)
 156 {
 157         unsigned long h,l;
 158
 159         outb(reg, base + INDEX_REG);
 160         l = le16_to_cpu(inw(base + DATA_REG_LOW));
 161         h = le16_to_cpu(inw(base + DATA_REG_HI ));
 162
 163         return ((h << 16) | l);
 164 }
 165
 166 static inline void nsp32_index_write4(unsigned int  base,
 167                                       unsigned int  reg,
 168                                       unsigned long val)
 169 {
 170         unsigned long h,l;
 171
 172         h = (val & 0xffff0000) >> 16;
 173         l = (val & 0x0000ffff) >> 0;
 174
 175         outb(reg, base + INDEX_REG);
 176         outw(cpu_to_le16(l), base + DATA_REG_LOW);
 177         outw(cpu_to_le16(h), base + DATA_REG_HI);
 178 }
 179
 180
 181 /* ===================================*/
 182
 183 static inline unsigned char nsp32_mmio_index_read1(unsigned int base,
 184                                                    unsigned int reg)
 185 {
 186         volatile unsigned short *index_ptr, *data_ptr;
 187
 188         index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
 189         data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
 190
 191         *index_ptr = reg;
 192
 193         return ((*data_ptr) & 0xff);
 194 }
 195
 196 static inline void nsp32_mmio_index_write1(unsigned int base,
 197                                            unsigned int reg,
 198                                            unsigned char val)
 199 {
 200         volatile unsigned short *index_ptr, *data_ptr;
 201
 202         index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
 203         data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
 204
 205         *index_ptr = reg;
 206         *data_ptr  = (unsigned short)val;
 207 }
 208
 209 static inline unsigned short nsp32_mmio_index_read2(unsigned int base,
 210                                                     unsigned int reg)
 211 {
 212         volatile unsigned short *index_ptr, *data_ptr;
 213
 214         index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
 215         data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
 216
 217         *index_ptr = reg;
 218
 219         return le16_to_cpu(*data_ptr);
 220 }
 221
 222 static inline void nsp32_mmio_index_write2(unsigned int base,
 223                                            unsigned int reg,
 224                                            unsigned short val)
 225 {
 226         volatile unsigned short *index_ptr, *data_ptr;
 227
 228         index_ptr = (unsigned short *)(base + NSP32_MMIO_OFFSET + INDEX_REG);
 229         data_ptr  = (unsigned short *)(base + NSP32_MMIO_OFFSET + DATA_REG_LOW);
 230
 231         *index_ptr = reg;
 232         *data_ptr  = val;
 233 }
 234
 235 /*-------------------------------------------------------------------*/
 236
 237 static inline void nsp32_multi_read4(unsigned int   BaseAddr,
 238                                      unsigned int   Register,
 239                                      void          *buf,
 240                                      unsigned long  count)
 241 {
 242         insl(BaseAddr + Register, buf, count);
 243 }
 244
 245 static inline void nsp32_fifo_read(unsigned int   base,
 246                                    void          *buf,
 247                                    unsigned long  count)
 248 {
 249         //DEBUG(0, __FUNCTION__ "() buf=0x%p, count=0x%lx*4\n", buf, count);
 250         nsp32_multi_read4(base, FIFO_DATA_LOW, buf, count);
 251 }
 252
 253 static inline void nsp32_multi_write4(unsigned int   BaseAddr,
 254                                       unsigned int   Register,
 255                                       void          *buf,
 256                                       unsigned long  count)
 257 {
 258         outsl(BaseAddr + Register, buf, count);
 259 }
 260
 261 static inline void nsp32_fifo_write(unsigned int   base,
 262                                     void          *buf,
 263                                     unsigned long  count)
 264 {
 265         nsp32_multi_write4(base, FIFO_DATA_LOW, buf, count);
 266 }
 267
 268 #endif _NSP32_IO_H
 269 /* end */