2 * URB OHCI HCD (Host Controller Driver) for USB.
4 * (C) Copyright 1999 Roman Weissgaerber <weissg@vienna.at>
5 * (C) Copyright 2000-2001 David Brownell <dbrownell@users.sourceforge.net>
11 static int cc_to_error[16] = {
13 /* mapping of the OHCI CC status to error codes */
14 /* No Error */ USB_ST_NOERROR,
15 /* CRC Error */ USB_ST_CRC,
16 /* Bit Stuff */ USB_ST_BITSTUFF,
17 /* Data Togg */ USB_ST_CRC,
18 /* Stall */ USB_ST_STALL,
19 /* DevNotResp */ USB_ST_NORESPONSE,
20 /* PIDCheck */ USB_ST_BITSTUFF,
21 /* UnExpPID */ USB_ST_BITSTUFF,
22 /* DataOver */ USB_ST_DATAOVERRUN,
23 /* DataUnder */ USB_ST_DATAUNDERRUN,
24 /* reservd */ USB_ST_NORESPONSE,
25 /* reservd */ USB_ST_NORESPONSE,
26 /* BufferOver */ USB_ST_BUFFEROVERRUN,
27 /* BuffUnder */ USB_ST_BUFFERUNDERRUN,
28 /* Not Access */ USB_ST_NORESPONSE,
29 /* Not Access */ USB_ST_NORESPONSE
32 #include <linux/config.h>
37 #define ED_UNLINK 0x01
40 #define ED_URB_DEL 0x08
57 struct ed * ed_rm_list;
61 } __attribute((aligned(16)));
62 typedef struct ed ed_t;
66 #define TD_CC 0xf0000000
67 #define TD_CC_GET(td_p) ((td_p >>28) & 0x0f)
68 #define TD_CC_SET(td_p, cc) (td_p) = ((td_p) & 0x0fffffff) | (((cc) & 0x0f) << 28)
69 #define TD_EC 0x0C000000
70 #define TD_T 0x03000000
71 #define TD_T_DATA0 0x02000000
72 #define TD_T_DATA1 0x03000000
73 #define TD_T_TOGGLE 0x00000000
74 #define TD_R 0x00040000
75 #define TD_DI 0x00E00000
76 #define TD_DI_SET(X) (((X) & 0x07)<< 21)
77 #define TD_DP 0x00180000
78 #define TD_DP_SETUP 0x00000000
79 #define TD_DP_IN 0x00100000
80 #define TD_DP_OUT 0x00080000
82 #define TD_ISO 0x00010000
83 #define TD_DEL 0x00020000
86 #define TD_CC_NOERROR 0x00
87 #define TD_CC_CRC 0x01
88 #define TD_CC_BITSTUFFING 0x02
89 #define TD_CC_DATATOGGLEM 0x03
90 #define TD_CC_STALL 0x04
91 #define TD_DEVNOTRESP 0x05
92 #define TD_PIDCHECKFAIL 0x06
93 #define TD_UNEXPECTEDPID 0x07
94 #define TD_DATAOVERRUN 0x08
95 #define TD_DATAUNDERRUN 0x09
96 #define TD_BUFFEROVERRUN 0x0C
97 #define TD_BUFFERUNDERRUN 0x0D
98 #define TD_NOTACCESSED 0x0F
105 __u32 hwCBP; /* Current Buffer Pointer */
106 __u32 hwNextTD; /* Next TD Pointer */
107 __u32 hwBE; /* Memory Buffer End Pointer */
113 struct td * next_dl_td;
119 } __attribute((aligned(32))); /* normally 16, iso needs 32 */
120 typedef struct td td_t;
122 #define OHCI_ED_SKIP (1 << 14)
125 * The HCCA (Host Controller Communications Area) is a 256 byte
126 * structure defined in the OHCI spec. that the host controller is
127 * told the base address of. It must be 256-byte aligned.
130 #define NUM_INTS 32 /* part of the OHCI standard */
132 __u32 int_table[NUM_INTS]; /* Interrupt ED table */
133 __u16 frame_no; /* current frame number */
134 __u16 pad1; /* set to 0 on each frame_no change */
135 __u32 done_head; /* info returned for an interrupt */
136 u8 reserved_for_hc[116];
137 } __attribute((aligned(256)));
141 * Maximum number of root hub ports.
143 #define MAX_ROOT_PORTS 15 /* maximum OHCI root hub ports */
146 * This is the structure of the OHCI controller's memory mapped I/O
147 * region. This is Memory Mapped I/O. You must use the readl() and
148 * writel() macros defined in asm/io.h to access these!!
151 /* control and status registers */
158 /* memory pointers */
160 __u32 ed_periodcurrent;
161 __u32 ed_controlhead;
162 __u32 ed_controlcurrent;
164 __u32 ed_bulkcurrent;
173 struct ohci_roothub_regs {
177 __u32 portstatus[MAX_ROOT_PORTS];
179 } __attribute((aligned(32)));
182 /* OHCI CONTROL AND STATUS REGISTER MASKS */
185 * HcControl (control) register masks
187 #define OHCI_CTRL_CBSR (3 << 0) /* control/bulk service ratio */
188 #define OHCI_CTRL_PLE (1 << 2) /* periodic list enable */
189 #define OHCI_CTRL_IE (1 << 3) /* isochronous enable */
190 #define OHCI_CTRL_CLE (1 << 4) /* control list enable */
191 #define OHCI_CTRL_BLE (1 << 5) /* bulk list enable */
192 #define OHCI_CTRL_HCFS (3 << 6) /* host controller functional state */
193 #define OHCI_CTRL_IR (1 << 8) /* interrupt routing */
194 #define OHCI_CTRL_RWC (1 << 9) /* remote wakeup connected */
195 #define OHCI_CTRL_RWE (1 << 10) /* remote wakeup enable */
197 /* pre-shifted values for HCFS */
198 # define OHCI_USB_RESET (0 << 6)
199 # define OHCI_USB_RESUME (1 << 6)
200 # define OHCI_USB_OPER (2 << 6)
201 # define OHCI_USB_SUSPEND (3 << 6)
204 * HcCommandStatus (cmdstatus) register masks
206 #define OHCI_HCR (1 << 0) /* host controller reset */
207 #define OHCI_CLF (1 << 1) /* control list filled */
208 #define OHCI_BLF (1 << 2) /* bulk list filled */
209 #define OHCI_OCR (1 << 3) /* ownership change request */
210 #define OHCI_SOC (3 << 16) /* scheduling overrun count */
213 * masks used with interrupt registers:
214 * HcInterruptStatus (intrstatus)
215 * HcInterruptEnable (intrenable)
216 * HcInterruptDisable (intrdisable)
218 #define OHCI_INTR_SO (1 << 0) /* scheduling overrun */
219 #define OHCI_INTR_WDH (1 << 1) /* writeback of done_head */
220 #define OHCI_INTR_SF (1 << 2) /* start frame */
221 #define OHCI_INTR_RD (1 << 3) /* resume detect */
222 #define OHCI_INTR_UE (1 << 4) /* unrecoverable error */
223 #define OHCI_INTR_FNO (1 << 5) /* frame number overflow */
224 #define OHCI_INTR_RHSC (1 << 6) /* root hub status change */
225 #define OHCI_INTR_OC (1 << 30) /* ownership change */
226 #define OHCI_INTR_MIE (1 << 31) /* master interrupt enable */
230 /* Virtual Root HUB */
231 struct virt_root_hub {
232 int devnum; /* Address of Root Hub endpoint */
237 struct timer_list rh_int_timer;
241 /* USB HUB CONSTANTS (not OHCI-specific; see hub.h) */
243 /* destination of request */
244 #define RH_INTERFACE 0x01
245 #define RH_ENDPOINT 0x02
246 #define RH_OTHER 0x03
248 #define RH_CLASS 0x20
249 #define RH_VENDOR 0x40
251 /* Requests: bRequest << 8 | bmRequestType */
252 #define RH_GET_STATUS 0x0080
253 #define RH_CLEAR_FEATURE 0x0100
254 #define RH_SET_FEATURE 0x0300
255 #define RH_SET_ADDRESS 0x0500
256 #define RH_GET_DESCRIPTOR 0x0680
257 #define RH_SET_DESCRIPTOR 0x0700
258 #define RH_GET_CONFIGURATION 0x0880
259 #define RH_SET_CONFIGURATION 0x0900
260 #define RH_GET_STATE 0x0280
261 #define RH_GET_INTERFACE 0x0A80
262 #define RH_SET_INTERFACE 0x0B00
263 #define RH_SYNC_FRAME 0x0C80
264 /* Our Vendor Specific Request */
265 #define RH_SET_EP 0x2000
268 /* Hub port features */
269 #define RH_PORT_CONNECTION 0x00
270 #define RH_PORT_ENABLE 0x01
271 #define RH_PORT_SUSPEND 0x02
272 #define RH_PORT_OVER_CURRENT 0x03
273 #define RH_PORT_RESET 0x04
274 #define RH_PORT_POWER 0x08
275 #define RH_PORT_LOW_SPEED 0x09
277 #define RH_C_PORT_CONNECTION 0x10
278 #define RH_C_PORT_ENABLE 0x11
279 #define RH_C_PORT_SUSPEND 0x12
280 #define RH_C_PORT_OVER_CURRENT 0x13
281 #define RH_C_PORT_RESET 0x14
284 #define RH_C_HUB_LOCAL_POWER 0x00
285 #define RH_C_HUB_OVER_CURRENT 0x01
287 #define RH_DEVICE_REMOTE_WAKEUP 0x00
288 #define RH_ENDPOINT_STALL 0x01
291 #define RH_REQ_ERR -1
295 /* OHCI ROOT HUB REGISTER MASKS */
297 /* roothub.portstatus [i] bits */
298 #define RH_PS_CCS 0x00000001 /* current connect status */
299 #define RH_PS_PES 0x00000002 /* port enable status*/
300 #define RH_PS_PSS 0x00000004 /* port suspend status */
301 #define RH_PS_POCI 0x00000008 /* port over current indicator */
302 #define RH_PS_PRS 0x00000010 /* port reset status */
303 #define RH_PS_PPS 0x00000100 /* port power status */
304 #define RH_PS_LSDA 0x00000200 /* low speed device attached */
305 #define RH_PS_CSC 0x00010000 /* connect status change */
306 #define RH_PS_PESC 0x00020000 /* port enable status change */
307 #define RH_PS_PSSC 0x00040000 /* port suspend status change */
308 #define RH_PS_OCIC 0x00080000 /* over current indicator change */
309 #define RH_PS_PRSC 0x00100000 /* port reset status change */
311 /* roothub.status bits */
312 #define RH_HS_LPS 0x00000001 /* local power status */
313 #define RH_HS_OCI 0x00000002 /* over current indicator */
314 #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
315 #define RH_HS_LPSC 0x00010000 /* local power status change */
316 #define RH_HS_OCIC 0x00020000 /* over current indicator change */
317 #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
319 /* roothub.b masks */
320 #define RH_B_DR 0x0000ffff /* device removable flags */
321 #define RH_B_PPCM 0xffff0000 /* port power control mask */
323 /* roothub.a masks */
324 #define RH_A_NDP (0xff << 0) /* number of downstream ports */
325 #define RH_A_PSM (1 << 8) /* power switching mode */
326 #define RH_A_NPS (1 << 9) /* no power switching */
327 #define RH_A_DT (1 << 10) /* device type (mbz) */
328 #define RH_A_OCPM (1 << 11) /* over current protection mode */
329 #define RH_A_NOCP (1 << 12) /* no over current protection */
330 #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
336 __u16 length; // number of tds associated with this request
337 __u16 td_cnt; // number of tds already serviced
339 wait_queue_head_t * wait;
340 td_t * td[0]; // list pointer to all corresponding TDs associated with this request
346 /* Hash struct used for TD/ED hashing */
350 struct hash_t *next; // chaining for collision cases
353 /* List of TD/ED hash entries */
359 #define TD_HASH_SIZE 64 /* power'o'two */
360 #define ED_HASH_SIZE 64 /* power'o'two */
362 #define TD_HASH_FUNC(td_dma) ((td_dma ^ (td_dma >> 5)) % TD_HASH_SIZE)
363 #define ED_HASH_FUNC(ed_dma) ((ed_dma ^ (ed_dma >> 5)) % ED_HASH_SIZE)
367 * This is the full ohci controller description
369 * Note how the "proper" USB information is just
370 * a subset of what the full implementation needs. (Linus)
374 typedef struct ohci {
375 struct ohci_hcca *hcca; /* hcca */
379 int disabled; /* e.g. got a UE, we're hung */
381 atomic_t resume_count; /* defending against multiple resumes */
382 unsigned long flags; /* for HC bugs */
383 #define OHCI_QUIRK_AMD756 0x01 /* erratum #4 */
384 #define OHCI_QUIRK_SUCKYIO 0x02 /* NSC superio */
386 struct ohci_regs * regs; /* OHCI controller's memory */
388 struct list_head timeout_list;
389 // struct list_head urb_list; // list of all pending urbs
390 spinlock_t ohci_lock; /* Covers all fields up & down */
391 struct urb *complete_head, *complete_tail;
393 int ohci_int_load[32]; /* load of the 32 Interrupt Chains (for load balancing)*/
394 ed_t * ed_rm_list[2]; /* lists of all endpoints to be removed */
395 ed_t * ed_bulktail; /* last endpoint of bulk list */
396 ed_t * ed_controltail; /* last endpoint of control list */
397 ed_t * ed_isotail; /* last endpoint of iso list */
399 __u32 hc_control; /* copy of the hc control reg */
400 struct usb_bus * bus;
401 struct usb_device * dev[128];
402 struct virt_root_hub rh;
404 /* PCI device handle, settings, ... */
405 struct pci_dev *ohci_dev;
407 struct pci_pool *td_cache;
408 struct pci_pool *dev_cache;
409 struct hash_list_t td_hash[TD_HASH_SIZE];
410 struct hash_list_t ed_hash[ED_HASH_SIZE];
414 #define NUM_EDS 32 /* num of preallocated endpoint descriptors */
420 wait_queue_head_t wait;
423 // #define ohci_to_usb(ohci) ((ohci)->usb)
424 #define usb_to_ohci(usb) ((struct ohci_device *)(usb)->hcpriv)
428 static int ep_link(ohci_t * ohci, ed_t * ed);
429 static int ep_unlink(ohci_t * ohci, ed_t * ed);
430 static ed_t * ep_add_ed(struct usb_device * usb_dev, unsigned int pipe, int interval, int load, int mem_flags);
431 static void ep_rm_ed(struct usb_device * usb_dev, ed_t * ed);
433 static void td_fill(ohci_t * ohci, unsigned int info, dma_addr_t data, int len, struct urb * urb, int index);
434 static void td_submit_urb(struct urb * urb);
436 static int rh_submit_urb(struct urb * urb);
437 static int rh_unlink_urb(struct urb * urb);
438 static int rh_init_int_timer(struct urb * urb);
440 /*-------------------------------------------------------------------------*/
442 #define ALLOC_FLAGS (in_interrupt () || current->state != TASK_RUNNING ? GFP_ATOMIC : GFP_NOIO)
445 # define OHCI_MEM_FLAGS SLAB_POISON
447 # define OHCI_MEM_FLAGS 0
451 # error "usb-ohci currently requires PCI-based controllers"
452 /* to support non-PCI OHCIs, you need custom bus/mem/... glue */
456 /* Recover a TD/ED using its collision chain */
458 dma_to_ed_td (struct hash_list_t * entry, dma_addr_t dma)
460 struct hash_t * scan = entry->head;
461 while (scan && scan->dma != dma)
468 static inline struct ed *
469 dma_to_ed (struct ohci * hc, dma_addr_t ed_dma)
471 return (struct ed *) dma_to_ed_td(&(hc->ed_hash[ED_HASH_FUNC(ed_dma)]),
475 static inline struct td *
476 dma_to_td (struct ohci * hc, dma_addr_t td_dma)
478 return (struct td *) dma_to_ed_td(&(hc->td_hash[TD_HASH_FUNC(td_dma)]),
482 /* Add a hash entry for a TD/ED; return true on success */
484 hash_add_ed_td(struct hash_list_t * entry, void * virt, dma_addr_t dma)
486 struct hash_t * scan;
488 scan = (struct hash_t *)kmalloc(sizeof(struct hash_t), ALLOC_FLAGS);
493 entry->head = entry->tail = scan;
495 entry->tail->next = scan;
506 hash_add_ed (struct ohci * hc, struct ed * ed)
508 return hash_add_ed_td (&(hc->ed_hash[ED_HASH_FUNC(ed->dma)]),
513 hash_add_td (struct ohci * hc, struct td * td)
515 return hash_add_ed_td (&(hc->td_hash[TD_HASH_FUNC(td->td_dma)]),
521 hash_free_ed_td (struct hash_list_t * entry, void * virt)
523 struct hash_t *scan, *prev;
524 scan = prev = entry->head;
526 // Find and unlink hash entry
527 while (scan && scan->virt != virt) {
532 if (scan == entry->head) {
533 if (entry->head == entry->tail)
534 entry->head = entry->tail = NULL;
536 entry->head = scan->next;
537 } else if (scan == entry->tail) {
541 prev->next = scan->next;
547 hash_free_ed (struct ohci * hc, struct ed * ed)
549 hash_free_ed_td (&(hc->ed_hash[ED_HASH_FUNC(ed->dma)]), ed);
553 hash_free_td (struct ohci * hc, struct td * td)
555 hash_free_ed_td (&(hc->td_hash[TD_HASH_FUNC(td->td_dma)]), td);
559 static int ohci_mem_init (struct ohci *ohci)
561 ohci->td_cache = pci_pool_create ("ohci_td", ohci->ohci_dev,
563 32 /* byte alignment */,
564 0 /* no page-crossing issues */,
565 GFP_KERNEL | OHCI_MEM_FLAGS);
568 ohci->dev_cache = pci_pool_create ("ohci_dev", ohci->ohci_dev,
569 sizeof (struct ohci_device),
570 16 /* byte alignment */,
571 0 /* no page-crossing issues */,
572 GFP_KERNEL | OHCI_MEM_FLAGS);
573 if (!ohci->dev_cache)
578 static void ohci_mem_cleanup (struct ohci *ohci)
580 if (ohci->td_cache) {
581 pci_pool_destroy (ohci->td_cache);
584 if (ohci->dev_cache) {
585 pci_pool_destroy (ohci->dev_cache);
591 static inline struct td *
592 td_alloc (struct ohci *hc, int mem_flags)
597 td = pci_pool_alloc (hc->td_cache, mem_flags, &dma);
601 /* hash it for later reverse mapping */
602 if (!hash_add_td (hc, td)) {
603 pci_pool_free (hc->td_cache, td, dma);
611 td_free (struct ohci *hc, struct td *td)
613 hash_free_td (hc, td);
614 pci_pool_free (hc->td_cache, td, td->td_dma);
618 /* DEV + EDs ... only the EDs need to be consistent */
619 static inline struct ohci_device *
620 dev_alloc (struct ohci *hc, int mem_flags)
623 struct ohci_device *dev;
626 dev = pci_pool_alloc (hc->dev_cache, mem_flags, &dma);
628 memset (dev, 0, sizeof (*dev));
629 init_waitqueue_head (&dev->wait);
631 offset = ((char *)&dev->ed) - ((char *)dev);
632 for (i = 0; i < NUM_EDS; i++, offset += sizeof dev->ed [0])
633 dev->ed [i].dma = dma + offset;
634 /* add to hashtable if used */
640 dev_free (struct ohci *hc, struct ohci_device *dev)
642 pci_pool_free (hc->dev_cache, dev, dev->dma);