1 /* $Id: aty128fb.c,v 1.1.1.1 2005/04/11 02:50:41 jack Exp $
2 * linux/drivers/video/aty128fb.c -- Frame buffer device for ATI Rage128
4 * Copyright (C) 1999-2000, Brad Douglas <brad@neruo.com>
5 * Copyright (C) 1999, Anthony Tong <atong@uiuc.edu>
7 * Ani Joshi / Jeff Garzik
10 * Michel Dänzer <michdaen@iiic.ethz.ch>
14 * Benjamin Herrenschmidt
15 * - pmac-specific PM stuff
17 * Andreas Hundt <andi@convergence.de>
20 * Based off of Geert's atyfb.c and vfb.c.
23 * - monitor sensing (DDC)
25 * - other platform support (only ppc/x86 supported)
26 * - hardware cursor support
29 * Please cc: your patches to brad@neruo.com.
33 * A special note of gratitude to ATI's devrel for providing documentation,
34 * example code and hardware. Thanks Nitya. -atong and brad
38 #include <linux/config.h>
39 #include <linux/module.h>
40 #include <linux/kernel.h>
41 #include <linux/errno.h>
42 #include <linux/string.h>
44 #include <linux/tty.h>
45 #include <linux/slab.h>
46 #include <linux/vmalloc.h>
47 #include <linux/delay.h>
48 #include <linux/interrupt.h>
49 #include <asm/uaccess.h>
51 #include <linux/init.h>
52 #include <linux/selection.h>
53 #include <linux/console.h>
54 #include <linux/pci.h>
55 #include <linux/ioport.h>
60 #include <asm/pci-bridge.h>
61 #include <video/macmodes.h>
63 #include <linux/nvram.h>
68 #include <linux/adb.h>
69 #include <linux/pmu.h>
72 #ifdef CONFIG_PMAC_BACKLIGHT
73 #include <asm/backlight.h>
76 #ifdef CONFIG_FB_COMPAT_XPMAC
77 #include <asm/vc_ioctl.h>
79 #ifdef CONFIG_BOOTX_TEXT
80 #include <asm/btext.h>
81 #endif /* CONFIG_BOOTX_TEXT */
83 #include <video/fbcon.h>
84 #include <video/fbcon-cfb8.h>
85 #include <video/fbcon-cfb16.h>
86 #include <video/fbcon-cfb24.h>
87 #include <video/fbcon-cfb32.h>
99 #define DBG(fmt, args...) printk(KERN_DEBUG "aty128fb: %s " fmt, __FUNCTION__, ##args);
101 #define DBG(fmt, args...)
106 static struct fb_var_screeninfo default_var __initdata = {
107 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
108 640, 480, 640, 480, 0, 0, 8, 0,
109 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
110 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
111 0, FB_VMODE_NONINTERLACED
114 #else /* CONFIG_PPC */
115 /* default to 1024x768 at 75Hz on PPC - this will work
116 * on the iMac, the usual 640x480 @ 60Hz doesn't. */
117 static struct fb_var_screeninfo default_var = {
118 /* 1024x768, 75 Hz, Non-Interlaced (78.75 MHz dotclock) */
119 1024, 768, 1024, 768, 0, 0, 8, 0,
120 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
121 0, 0, -1, -1, 0, 12699, 160, 32, 28, 1, 96, 3,
122 FB_SYNC_HOR_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
124 #endif /* CONFIG_PPC */
126 /* default modedb mode */
127 /* 640x480, 60 Hz, Non-Interlaced (25.172 MHz dotclock) */
128 static struct fb_videomode defaultmode __initdata = {
140 vmode: FB_VMODE_NONINTERLACED
143 /* struct to hold chip description information */
144 struct aty128_chip_info {
146 unsigned short device;
150 /* Chip generations */
157 /* supported Rage128 chipsets */
158 static struct aty128_chip_info aty128_pci_probe_list[] __initdata =
160 {"Rage128 RE (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RE, rage_128},
161 {"Rage128 RF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RF, rage_128},
162 {"Rage128 RK (PCI)", PCI_DEVICE_ID_ATI_RAGE128_RK, rage_128},
163 {"Rage128 RL (AGP)", PCI_DEVICE_ID_ATI_RAGE128_RL, rage_128},
164 {"Rage128 Pro PF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_PF, rage_128_pro},
165 {"Rage128 Pro PR (PCI)", PCI_DEVICE_ID_ATI_RAGE128_PR, rage_128_pro},
166 {"Rage128 Pro TR (AGP)", PCI_DEVICE_ID_ATI_RAGE128_U3, rage_128_pro},
167 {"Rage128 Pro TF (AGP)", PCI_DEVICE_ID_ATI_RAGE128_U1, rage_128_pro},
168 {"Rage Mobility M3 (PCI)", PCI_DEVICE_ID_ATI_RAGE128_LE, rage_M3},
169 {"Rage Mobility M3 (AGP)", PCI_DEVICE_ID_ATI_RAGE128_LF, rage_M3},
173 /* packed BIOS settings */
178 u8 accelerator_entry;
180 u16 VGA_table_offset;
181 u16 POST_table_offset;
187 u16 PCLK_ref_divider;
191 u16 MCLK_ref_divider;
195 u16 XCLK_ref_divider;
198 } __attribute__ ((packed)) PLL_BLOCK;
199 #endif /* !CONFIG_PPC */
201 /* onboard memory information */
202 struct aty128_meminfo {
216 /* various memory configurations */
217 static const struct aty128_meminfo sdr_128 =
218 { 4, 4, 3, 3, 1, 3, 1, 16, 30, 16, "128-bit SDR SGRAM (1:1)" };
219 static const struct aty128_meminfo sdr_64 =
220 { 4, 8, 3, 3, 1, 3, 1, 17, 46, 17, "64-bit SDR SGRAM (1:1)" };
221 static const struct aty128_meminfo sdr_sgram =
222 { 4, 4, 1, 2, 1, 2, 1, 16, 24, 16, "64-bit SDR SGRAM (2:1)" };
223 static const struct aty128_meminfo ddr_sgram =
224 { 4, 4, 3, 3, 2, 3, 1, 16, 31, 16, "64-bit DDR SGRAM" };
226 static const char *aty128fb_name = "ATY Rage128";
227 static char fontname[40] __initdata = { 0 };
229 static int noaccel __initdata = 0;
230 static char *font __initdata = NULL;
231 static char *mode __initdata = NULL;
232 static int nomtrr __initdata = 0;
234 static char *mode_option __initdata = NULL;
237 static int default_vmode __initdata = VMODE_1024_768_60;
238 static int default_cmode __initdata = CMODE_8;
241 #ifdef CONFIG_PMAC_PBOOK
242 static int default_crt_on __initdata = 0;
243 static int default_lcd_on __initdata = 1;
251 struct aty128_constants {
264 u32 h_total, h_sync_strt_wid;
265 u32 v_total, v_sync_strt_wid;
267 u32 offset, offset_cntl;
268 u32 xoffset, yoffset;
275 u32 feedback_divider;
279 struct aty128_ddafifo {
284 /* register values for a specific mode */
285 struct aty128fb_par {
286 struct aty128_crtc crtc;
287 struct aty128_pll pll;
288 struct aty128_ddafifo fifo_reg;
292 struct fb_info_aty128 {
293 struct fb_info fb_info;
294 struct fb_info_aty128 *next;
295 struct aty128_constants constants; /* PLL and others */
296 unsigned long regbase_phys; /* physical mmio */
297 void *regbase; /* remapped mmio */
298 unsigned long frame_buffer_phys; /* physical fb memory */
299 void *frame_buffer; /* remaped framebuffer */
300 u32 vram_size; /* onboard video ram */
302 const struct aty128_meminfo *mem; /* onboard mem info */
303 struct aty128fb_par default_par, current_par;
305 struct { u8 red, green, blue, pad; } palette[256];
307 #ifdef FBCON_HAS_CFB16
310 #ifdef FBCON_HAS_CFB24
313 #ifdef FBCON_HAS_CFB32
318 struct pci_dev *pdev;
321 struct { int vram; int vram_valid; } mtrr;
324 int blitter_may_be_busy;
325 int fifo_slots; /* free slots in FIFO (64 max) */
326 #ifdef CONFIG_PMAC_PBOOK
327 unsigned char *save_framebuffer;
330 u32 save_lcd_gen_cntl;
334 static struct fb_info_aty128 *board_list = NULL;
336 #ifdef CONFIG_PMAC_PBOOK
337 int aty128_sleep_notify(struct pmu_sleep_notifier *self, int when);
338 static struct pmu_sleep_notifier aty128_sleep_notifier = {
339 aty128_sleep_notify, SLEEP_LEVEL_VIDEO,
343 #define round_div(n, d) ((n+(d/2))/d)
346 * Interface used by the world
349 int aty128fb_setup(char *options);
351 static int aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con,
352 struct fb_info *info);
353 static int aty128fb_get_var(struct fb_var_screeninfo *var, int con,
354 struct fb_info *info);
355 static int aty128fb_set_var(struct fb_var_screeninfo *var, int con,
356 struct fb_info *info);
357 static int aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
358 struct fb_info *info);
359 static int aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
360 struct fb_info *info);
361 static int aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
363 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
364 u_long arg, int con, struct fb_info *info);
365 static int aty128fb_rasterimg(struct fb_info *info, int start);
369 * Interface to the low level console driver
372 int aty128fb_init(void);
373 static int aty128fbcon_switch(int con, struct fb_info *fb);
374 static void aty128fbcon_blank(int blank, struct fb_info *fb);
380 static void aty128_encode_fix(struct fb_fix_screeninfo *fix,
381 struct aty128fb_par *par,
382 const struct fb_info_aty128 *info);
383 static void aty128_set_dispsw(struct display *disp,
384 struct fb_info_aty128 *info, int bpp, int accel);
385 static int aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
386 u_int *transp, struct fb_info *info);
387 static int aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
388 u_int transp, struct fb_info *info);
389 static void do_install_cmap(int con, struct fb_info *info);
390 static int aty128_encode_var(struct fb_var_screeninfo *var,
391 const struct aty128fb_par *par,
392 const struct fb_info_aty128 *info);
393 static int aty128_decode_var(struct fb_var_screeninfo *var,
394 struct aty128fb_par *par,
395 const struct fb_info_aty128 *info);
396 static int aty128_pci_register(struct pci_dev *pdev,
397 const struct aty128_chip_info *aci);
398 static struct fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128
399 *board_list, struct fb_info_aty128 *new_node);
400 #if !defined(CONFIG_PPC) && !defined(__sparc__)
401 static void __init aty128_get_pllinfo(struct fb_info_aty128 *info,
403 static char __init *aty128find_ROM(struct fb_info_aty128 *info);
405 static void aty128_timings(struct fb_info_aty128 *info);
406 static void aty128_init_engine(const struct aty128fb_par *par,
407 struct fb_info_aty128 *info);
408 static void aty128_reset_engine(const struct fb_info_aty128 *info);
409 static void aty128_flush_pixel_cache(const struct fb_info_aty128 *info);
410 static void do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
411 static void wait_for_fifo(u16 entries, struct fb_info_aty128 *info);
412 static void wait_for_idle(struct fb_info_aty128 *info);
413 static u32 depth_to_dst(u32 depth);
415 #ifdef FBCON_HAS_CFB8
416 static struct display_switch fbcon_aty128_8;
417 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
418 int c, int yy, int xx);
419 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
420 const unsigned short *s, int count,
423 #ifdef FBCON_HAS_CFB16
424 static struct display_switch fbcon_aty128_16;
425 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
426 int c, int yy, int xx);
427 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
428 const unsigned short *s, int count,
431 #ifdef FBCON_HAS_CFB24
432 static struct display_switch fbcon_aty128_24;
433 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
434 int c, int yy, int xx);
435 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
436 const unsigned short *s, int count,
439 #ifdef FBCON_HAS_CFB32
440 static struct display_switch fbcon_aty128_32;
441 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
442 int c, int yy, int xx);
443 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
444 const unsigned short *s, int count,
448 static struct fb_ops aty128fb_ops = {
450 fb_get_fix: aty128fb_get_fix,
451 fb_get_var: aty128fb_get_var,
452 fb_set_var: aty128fb_set_var,
453 fb_get_cmap: aty128fb_get_cmap,
454 fb_set_cmap: aty128fb_set_cmap,
455 fb_pan_display: aty128fb_pan_display,
456 fb_ioctl: aty128fb_ioctl,
457 fb_rasterimg: aty128fb_rasterimg,
460 #ifdef CONFIG_PMAC_BACKLIGHT
461 static int aty128_set_backlight_enable(int on, int level, void* data);
462 static int aty128_set_backlight_level(int level, void* data);
464 static struct backlight_controller aty128_backlight_controller = {
465 aty128_set_backlight_enable,
466 aty128_set_backlight_level
468 #endif /* CONFIG_PMAC_BACKLIGHT */
471 * Functions to read from/write to the mmio registers
472 * - endian conversions may possibly be avoided by
473 * using the other register aperture. TODO.
476 _aty_ld_le32(volatile unsigned int regindex,
477 const struct fb_info_aty128 *info)
481 #if defined(__powerpc__)
482 asm("lwbrx %0,%1,%2;eieio" : "=r"(val) : "b"(regindex), "r"(info->regbase));
484 val = readl (info->regbase + regindex);
491 _aty_st_le32(volatile unsigned int regindex, u32 val,
492 const struct fb_info_aty128 *info)
494 #if defined(__powerpc__)
495 asm("stwbrx %0,%1,%2;eieio" : : "r"(val), "b"(regindex),
496 "r"(info->regbase) : "memory");
498 writel (val, info->regbase + regindex);
503 _aty_ld_8(unsigned int regindex, const struct fb_info_aty128 *info)
505 return readb (info->regbase + regindex);
509 _aty_st_8(unsigned int regindex, u8 val, const struct fb_info_aty128 *info)
511 writeb (val, info->regbase + regindex);
514 #define aty_ld_le32(regindex) _aty_ld_le32(regindex, info)
515 #define aty_st_le32(regindex, val) _aty_st_le32(regindex, val, info)
516 #define aty_ld_8(regindex) _aty_ld_8(regindex, info)
517 #define aty_st_8(regindex, val) _aty_st_8(regindex, val, info)
520 * Functions to read from/write to the pll registers
523 #define aty_ld_pll(pll_index) _aty_ld_pll(pll_index, info)
524 #define aty_st_pll(pll_index, val) _aty_st_pll(pll_index, val, info)
528 _aty_ld_pll(unsigned int pll_index,
529 const struct fb_info_aty128 *info)
531 aty_st_8(CLOCK_CNTL_INDEX, pll_index & 0x3F);
532 return aty_ld_le32(CLOCK_CNTL_DATA);
537 _aty_st_pll(unsigned int pll_index, u32 val,
538 const struct fb_info_aty128 *info)
540 aty_st_8(CLOCK_CNTL_INDEX, (pll_index & 0x3F) | PLL_WR_EN);
541 aty_st_le32(CLOCK_CNTL_DATA, val);
545 /* return true when the PLL has completed an atomic update */
547 aty_pll_readupdate(const struct fb_info_aty128 *info)
549 return !(aty_ld_pll(PPLL_REF_DIV) & PPLL_ATOMIC_UPDATE_R);
554 aty_pll_wait_readupdate(const struct fb_info_aty128 *info)
556 unsigned long timeout = jiffies + HZ/100; // should be more than enough
559 while (time_before(jiffies, timeout))
560 if (aty_pll_readupdate(info)) {
565 if (reset) /* reset engine?? */
566 printk(KERN_DEBUG "aty128fb: PLL write timeout!\n");
570 /* tell PLL to update */
572 aty_pll_writeupdate(const struct fb_info_aty128 *info)
574 aty_pll_wait_readupdate(info);
576 aty_st_pll(PPLL_REF_DIV,
577 aty_ld_pll(PPLL_REF_DIV) | PPLL_ATOMIC_UPDATE_W);
581 /* write to the scratch register to test r/w functionality */
583 register_test(const struct fb_info_aty128 *info)
588 val = aty_ld_le32(BIOS_0_SCRATCH);
590 aty_st_le32(BIOS_0_SCRATCH, 0x55555555);
591 if (aty_ld_le32(BIOS_0_SCRATCH) == 0x55555555) {
592 aty_st_le32(BIOS_0_SCRATCH, 0xAAAAAAAA);
594 if (aty_ld_le32(BIOS_0_SCRATCH) == 0xAAAAAAAA)
598 aty_st_le32(BIOS_0_SCRATCH, val); // restore value
604 * Accelerator engine functions
607 do_wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
612 for (i = 0; i < 2000000; i++) {
613 info->fifo_slots = aty_ld_le32(GUI_STAT) & 0x0fff;
614 if (info->fifo_slots >= entries)
617 aty128_reset_engine(info);
623 wait_for_idle(struct fb_info_aty128 *info)
627 do_wait_for_fifo(64, info);
630 for (i = 0; i < 2000000; i++) {
631 if (!(aty_ld_le32(GUI_STAT) & (1 << 31))) {
632 aty128_flush_pixel_cache(info);
633 info->blitter_may_be_busy = 0;
637 aty128_reset_engine(info);
643 wait_for_fifo(u16 entries, struct fb_info_aty128 *info)
645 if (info->fifo_slots < entries)
646 do_wait_for_fifo(64, info);
647 info->fifo_slots -= entries;
652 aty128_flush_pixel_cache(const struct fb_info_aty128 *info)
657 tmp = aty_ld_le32(PC_NGUI_CTLSTAT);
660 aty_st_le32(PC_NGUI_CTLSTAT, tmp);
662 for (i = 0; i < 2000000; i++)
663 if (!(aty_ld_le32(PC_NGUI_CTLSTAT) & PC_BUSY))
669 aty128_reset_engine(const struct fb_info_aty128 *info)
671 u32 gen_reset_cntl, clock_cntl_index, mclk_cntl;
673 aty128_flush_pixel_cache(info);
675 clock_cntl_index = aty_ld_le32(CLOCK_CNTL_INDEX);
676 mclk_cntl = aty_ld_pll(MCLK_CNTL);
678 aty_st_pll(MCLK_CNTL, mclk_cntl | 0x00030000);
680 gen_reset_cntl = aty_ld_le32(GEN_RESET_CNTL);
681 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl | SOFT_RESET_GUI);
682 aty_ld_le32(GEN_RESET_CNTL);
683 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl & ~(SOFT_RESET_GUI));
684 aty_ld_le32(GEN_RESET_CNTL);
686 aty_st_pll(MCLK_CNTL, mclk_cntl);
687 aty_st_le32(CLOCK_CNTL_INDEX, clock_cntl_index);
688 aty_st_le32(GEN_RESET_CNTL, gen_reset_cntl);
690 /* use old pio mode */
691 aty_st_le32(PM4_BUFFER_CNTL, PM4_BUFFER_CNTL_NONPM4);
698 aty128_init_engine(const struct aty128fb_par *par,
699 struct fb_info_aty128 *info)
705 /* 3D scaler not spoken here */
706 wait_for_fifo(1, info);
707 aty_st_le32(SCALE_3D_CNTL, 0x00000000);
709 aty128_reset_engine(info);
711 pitch_value = par->crtc.pitch;
712 if (par->crtc.bpp == 24) {
713 pitch_value = pitch_value * 3;
716 wait_for_fifo(4, info);
717 /* setup engine offset registers */
718 aty_st_le32(DEFAULT_OFFSET, 0x00000000);
720 /* setup engine pitch registers */
721 aty_st_le32(DEFAULT_PITCH, pitch_value);
723 /* set the default scissor register to max dimensions */
724 aty_st_le32(DEFAULT_SC_BOTTOM_RIGHT, (0x1FFF << 16) | 0x1FFF);
726 /* set the drawing controls registers */
727 aty_st_le32(DP_GUI_MASTER_CNTL,
728 GMC_SRC_PITCH_OFFSET_DEFAULT |
729 GMC_DST_PITCH_OFFSET_DEFAULT |
730 GMC_SRC_CLIP_DEFAULT |
731 GMC_DST_CLIP_DEFAULT |
732 GMC_BRUSH_SOLIDCOLOR |
733 (depth_to_dst(par->crtc.depth) << 8) |
735 GMC_BYTE_ORDER_MSB_TO_LSB |
736 GMC_DP_CONVERSION_TEMP_6500 |
740 GMC_DST_CLR_CMP_FCN_CLEAR |
744 wait_for_fifo(8, info);
745 /* clear the line drawing registers */
746 aty_st_le32(DST_BRES_ERR, 0);
747 aty_st_le32(DST_BRES_INC, 0);
748 aty_st_le32(DST_BRES_DEC, 0);
750 /* set brush color registers */
751 aty_st_le32(DP_BRUSH_FRGD_CLR, 0xFFFFFFFF); /* white */
752 aty_st_le32(DP_BRUSH_BKGD_CLR, 0x00000000); /* black */
754 /* set source color registers */
755 aty_st_le32(DP_SRC_FRGD_CLR, 0xFFFFFFFF); /* white */
756 aty_st_le32(DP_SRC_BKGD_CLR, 0x00000000); /* black */
758 /* default write mask */
759 aty_st_le32(DP_WRITE_MASK, 0xFFFFFFFF);
761 /* Wait for all the writes to be completed before returning */
766 /* convert depth values to their register representation */
768 depth_to_dst(u32 depth)
772 else if (depth <= 15)
774 else if (depth == 16)
776 else if (depth <= 24)
778 else if (depth <= 32)
789 /* Program the CRTC registers */
791 aty128_set_crtc(const struct aty128_crtc *crtc,
792 const struct fb_info_aty128 *info)
794 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl);
795 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_total);
796 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid);
797 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_total);
798 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid);
799 aty_st_le32(CRTC_PITCH, crtc->pitch);
800 aty_st_le32(CRTC_OFFSET, crtc->offset);
801 aty_st_le32(CRTC_OFFSET_CNTL, crtc->offset_cntl);
802 /* Disable ATOMIC updating. Is this the right place? */
803 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~(0x00030000));
808 aty128_var_to_crtc(const struct fb_var_screeninfo *var,
809 struct aty128_crtc *crtc,
810 const struct fb_info_aty128 *info)
812 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp, dst;
813 u32 left, right, upper, lower, hslen, vslen, sync, vmode;
814 u32 h_total, h_disp, h_sync_strt, h_sync_wid, h_sync_pol;
815 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
817 u8 hsync_strt_pix[5] = { 0, 0x12, 9, 6, 5 };
818 u8 mode_bytpp[7] = { 0, 0, 1, 2, 2, 3, 4 };
823 vxres = var->xres_virtual;
824 vyres = var->yres_virtual;
825 xoffset = var->xoffset;
826 yoffset = var->yoffset;
827 bpp = var->bits_per_pixel;
828 left = var->left_margin;
829 right = var->right_margin;
830 upper = var->upper_margin;
831 lower = var->lower_margin;
832 hslen = var->hsync_len;
833 vslen = var->vsync_len;
840 depth = (var->green.length == 6) ? 16 : 15;
842 /* check for mode eligibility
843 * accept only non interlaced modes */
844 if ((vmode & FB_VMODE_MASK) != FB_VMODE_NONINTERLACED)
847 /* convert (and round up) and validate */
848 xres = (xres + 7) & ~7;
849 xoffset = (xoffset + 7) & ~7;
851 if (vxres < xres + xoffset)
852 vxres = xres + xoffset;
854 if (vyres < yres + yoffset)
855 vyres = yres + yoffset;
857 /* convert depth into ATI register depth */
858 dst = depth_to_dst(depth);
860 if (dst == -EINVAL) {
861 printk(KERN_ERR "aty128fb: Invalid depth or RGBA\n");
865 /* convert register depth to bytes per pixel */
866 bytpp = mode_bytpp[dst];
868 /* make sure there is enough video ram for the mode */
869 if ((u32)(vxres * vyres * bytpp) > info->vram_size) {
870 printk(KERN_ERR "aty128fb: Not enough memory for mode\n");
874 h_disp = (xres >> 3) - 1;
875 h_total = (((xres + right + hslen + left) >> 3) - 1) & 0xFFFFL;
878 v_total = (yres + upper + vslen + lower - 1) & 0xFFFFL;
880 /* check to make sure h_total and v_total are in range */
881 if (((h_total >> 3) - 1) > 0x1ff || (v_total - 1) > 0x7FF) {
882 printk(KERN_ERR "aty128fb: invalid width ranges\n");
886 h_sync_wid = (hslen + 7) >> 3;
889 else if (h_sync_wid > 0x3f) /* 0x3f = max hwidth */
892 h_sync_strt = h_disp + (right >> 3);
897 else if (v_sync_wid > 0x1f) /* 0x1f = max vwidth */
900 v_sync_strt = v_disp + lower;
902 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
903 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
905 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
907 crtc->gen_cntl = 0x3000000L | c_sync | (dst << 8);
909 crtc->h_total = h_total | (h_disp << 16);
910 crtc->v_total = v_total | (v_disp << 16);
912 crtc->h_sync_strt_wid = hsync_strt_pix[bytpp] | (h_sync_strt << 3) |
913 (h_sync_wid << 16) | (h_sync_pol << 23);
914 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid << 16) |
917 crtc->pitch = vxres >> 3;
921 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
922 crtc->offset_cntl = 0x00010000;
924 crtc->offset_cntl = 0;
928 crtc->xoffset = xoffset;
929 crtc->yoffset = yoffset;
938 aty128_pix_width_to_var(int pix_width, struct fb_var_screeninfo *var)
941 /* fill in pixel info */
943 case CRTC_PIX_WIDTH_8BPP:
944 var->bits_per_pixel = 8;
947 var->green.offset = 0;
948 var->green.length = 8;
949 var->blue.offset = 0;
950 var->blue.length = 8;
951 var->transp.offset = 0;
952 var->transp.length = 0;
954 case CRTC_PIX_WIDTH_15BPP:
955 var->bits_per_pixel = 16;
956 var->red.offset = 10;
958 var->green.offset = 5;
959 var->green.length = 5;
960 var->blue.offset = 0;
961 var->blue.length = 5;
962 var->transp.offset = 0;
963 var->transp.length = 0;
965 case CRTC_PIX_WIDTH_16BPP:
966 var->bits_per_pixel = 16;
967 var->red.offset = 11;
969 var->green.offset = 5;
970 var->green.length = 6;
971 var->blue.offset = 0;
972 var->blue.length = 5;
973 var->transp.offset = 0;
974 var->transp.length = 0;
976 case CRTC_PIX_WIDTH_24BPP:
977 var->bits_per_pixel = 24;
978 var->red.offset = 16;
980 var->green.offset = 8;
981 var->green.length = 8;
982 var->blue.offset = 0;
983 var->blue.length = 8;
984 var->transp.offset = 0;
985 var->transp.length = 0;
987 case CRTC_PIX_WIDTH_32BPP:
988 var->bits_per_pixel = 32;
989 var->red.offset = 16;
991 var->green.offset = 8;
992 var->green.length = 8;
993 var->blue.offset = 0;
994 var->blue.length = 8;
995 var->transp.offset = 24;
996 var->transp.length = 8;
999 printk(KERN_ERR "aty128fb: Invalid pixel width\n");
1008 aty128_crtc_to_var(const struct aty128_crtc *crtc,
1009 struct fb_var_screeninfo *var)
1011 u32 xres, yres, left, right, upper, lower, hslen, vslen, sync;
1012 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid, h_sync_pol;
1013 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1016 /* fun with masking */
1017 h_total = crtc->h_total & 0x1ff;
1018 h_disp = (crtc->h_total >> 16) & 0xff;
1019 h_sync_strt = (crtc->h_sync_strt_wid >> 3) & 0x1ff;
1020 h_sync_dly = crtc->h_sync_strt_wid & 0x7;
1021 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x3f;
1022 h_sync_pol = (crtc->h_sync_strt_wid >> 23) & 0x1;
1023 v_total = crtc->v_total & 0x7ff;
1024 v_disp = (crtc->v_total >> 16) & 0x7ff;
1025 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1026 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1027 v_sync_pol = (crtc->v_sync_strt_wid >> 23) & 0x1;
1028 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1029 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1031 /* do conversions */
1032 xres = (h_disp + 1) << 3;
1034 left = ((h_total - h_sync_strt - h_sync_wid) << 3) - h_sync_dly;
1035 right = ((h_sync_strt - h_disp) << 3) + h_sync_dly;
1036 hslen = h_sync_wid << 3;
1037 upper = v_total - v_sync_strt - v_sync_wid;
1038 lower = v_sync_strt - v_disp;
1040 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1041 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1042 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1044 aty128_pix_width_to_var(pix_width, var);
1048 var->xres_virtual = crtc->vxres;
1049 var->yres_virtual = crtc->vyres;
1050 var->xoffset = crtc->xoffset;
1051 var->yoffset = crtc->yoffset;
1052 var->left_margin = left;
1053 var->right_margin = right;
1054 var->upper_margin = upper;
1055 var->lower_margin = lower;
1056 var->hsync_len = hslen;
1057 var->vsync_len = vslen;
1059 var->vmode = FB_VMODE_NONINTERLACED;
1065 aty128_set_crt_enable(struct fb_info_aty128 *info, int on)
1068 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) | CRT_CRTC_ON);
1069 aty_st_le32(DAC_CNTL, (aty_ld_le32(DAC_CNTL) | DAC_PALETTE2_SNOOP_EN));
1071 aty_st_le32(CRTC_EXT_CNTL, aty_ld_le32(CRTC_EXT_CNTL) & ~CRT_CRTC_ON);
1075 aty128_set_lcd_enable(struct fb_info_aty128 *info, int on)
1080 reg = aty_ld_le32(LVDS_GEN_CNTL);
1081 reg |= LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION;
1082 reg &= ~LVDS_DISPLAY_DIS;
1083 aty_st_le32(LVDS_GEN_CNTL, reg);
1084 #ifdef CONFIG_PMAC_BACKLIGHT
1085 aty128_set_backlight_enable(get_backlight_enable(), get_backlight_level(), info);
1088 #ifdef CONFIG_PMAC_BACKLIGHT
1089 aty128_set_backlight_enable(0, 0, info);
1091 reg = aty_ld_le32(LVDS_GEN_CNTL);
1092 reg |= LVDS_DISPLAY_DIS;
1093 aty_st_le32(LVDS_GEN_CNTL, reg);
1095 reg &= ~(LVDS_ON /*| LVDS_EN*/);
1096 aty_st_le32(LVDS_GEN_CNTL, reg);
1101 aty128_set_pll(struct aty128_pll *pll, const struct fb_info_aty128 *info)
1105 unsigned char post_conv[] = /* register values for post dividers */
1106 { 2, 0, 1, 4, 2, 2, 6, 2, 3, 2, 2, 2, 7 };
1108 /* select PPLL_DIV_3 */
1109 aty_st_le32(CLOCK_CNTL_INDEX, aty_ld_le32(CLOCK_CNTL_INDEX) | (3 << 8));
1112 aty_st_pll(PPLL_CNTL,
1113 aty_ld_pll(PPLL_CNTL) | PPLL_RESET | PPLL_ATOMIC_UPDATE_EN);
1115 /* write the reference divider */
1116 aty_pll_wait_readupdate(info);
1117 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider & 0x3ff);
1118 aty_pll_writeupdate(info);
1120 div3 = aty_ld_pll(PPLL_DIV_3);
1121 div3 &= ~PPLL_FB3_DIV_MASK;
1122 div3 |= pll->feedback_divider;
1123 div3 &= ~PPLL_POST3_DIV_MASK;
1124 div3 |= post_conv[pll->post_divider] << 16;
1126 /* write feedback and post dividers */
1127 aty_pll_wait_readupdate(info);
1128 aty_st_pll(PPLL_DIV_3, div3);
1129 aty_pll_writeupdate(info);
1131 aty_pll_wait_readupdate(info);
1132 aty_st_pll(HTOTAL_CNTL, 0); /* no horiz crtc adjustment */
1133 aty_pll_writeupdate(info);
1135 /* clear the reset, just in case */
1136 aty_st_pll(PPLL_CNTL, aty_ld_pll(PPLL_CNTL) & ~PPLL_RESET);
1139 if (info->chip_gen == rage_M3) {
1140 /* XXX energy saving, disable VCLK during blanking */
1141 aty_pll_wait_readupdate(info);
1142 aty_st_pll(VCLK_ECP_CNTL, aty_ld_pll(VCLK_ECP_CNTL) | 0xc0);
1143 aty_pll_writeupdate(info);
1146 aty_pll_wait_readupdate(info);
1147 aty_st_pll(XCLK_CNTL, aty_ld_pll(XCLK_CNTL) | 0x00330000);
1148 aty_pll_writeupdate(info);
1149 aty_pll_wait_readupdate(info);
1150 aty_st_pll(MCLK_CNTL, aty_ld_pll(MCLK_CNTL) | 0x00000700);
1151 aty_pll_writeupdate(info);
1158 aty128_var_to_pll(u32 period_in_ps, struct aty128_pll *pll,
1159 const struct fb_info_aty128 *info)
1161 const struct aty128_constants c = info->constants;
1162 unsigned char post_dividers[] = {1,2,4,8,3,6,12};
1164 u32 vclk; /* in .01 MHz */
1168 vclk = 100000000 / period_in_ps; /* convert units to 10 kHz */
1170 /* adjust pixel clock if necessary */
1171 if (vclk > c.ppll_max)
1173 if (vclk * 12 < c.ppll_min)
1174 vclk = c.ppll_min/12;
1176 /* now, find an acceptable divider */
1177 for (i = 0; i < sizeof(post_dividers); i++) {
1178 output_freq = post_dividers[i] * vclk;
1179 if (output_freq >= c.ppll_min && output_freq <= c.ppll_max)
1183 /* calculate feedback divider */
1184 n = c.ref_divider * output_freq;
1187 pll->post_divider = post_dividers[i];
1188 pll->feedback_divider = round_div(n, d);
1191 DBG("post %d feedback %d vlck %d output %d ref_divider %d "
1192 "vclk_per: %d\n", pll->post_divider,
1193 pll->feedback_divider, vclk, output_freq,
1194 c.ref_divider, period_in_ps);
1201 aty128_pll_to_var(const struct aty128_pll *pll, struct fb_var_screeninfo *var,
1202 const struct fb_info_aty128 *info)
1204 var->pixclock = 100000000 / pll->vclk;
1211 aty128_set_fifo(const struct aty128_ddafifo *dsp,
1212 const struct fb_info_aty128 *info)
1214 aty_st_le32(DDA_CONFIG, dsp->dda_config);
1215 aty_st_le32(DDA_ON_OFF, dsp->dda_on_off);
1220 aty128_ddafifo(struct aty128_ddafifo *dsp,
1221 const struct aty128_pll *pll,
1223 const struct fb_info_aty128 *info)
1225 const struct aty128_meminfo *m = info->mem;
1226 u32 xclk = info->constants.xclk;
1227 u32 fifo_width = info->constants.fifo_width;
1228 u32 fifo_depth = info->constants.fifo_depth;
1229 s32 x, b, p, ron, roff;
1232 /* round up to multiple of 8 */
1233 bpp = (depth+7) & ~7;
1235 n = xclk * fifo_width;
1236 d = pll->vclk * bpp;
1237 x = round_div(n, d);
1240 3 * ((m->Trcd - 2 > 0) ? m->Trcd - 2 : 0) +
1259 x = round_div(n, d);
1260 roff = x * (fifo_depth - 4);
1262 if ((ron + m->Rloop) >= roff) {
1263 printk(KERN_ERR "aty128fb: Mode out of range!\n");
1267 DBG("p: %x rloop: %x x: %x ron: %x roff: %x\n",
1268 p, m->Rloop, x, ron, roff);
1270 dsp->dda_config = p << 16 | m->Rloop << 20 | x;
1271 dsp->dda_on_off = ron << 16 | roff;
1278 * This actually sets the video mode.
1281 aty128_set_par(struct aty128fb_par *par,
1282 struct fb_info_aty128 *info)
1286 info->current_par = *par;
1288 if (info->blitter_may_be_busy)
1289 wait_for_idle(info);
1291 /* clear all registers that may interfere with mode setting */
1292 aty_st_le32(OVR_CLR, 0);
1293 aty_st_le32(OVR_WID_LEFT_RIGHT, 0);
1294 aty_st_le32(OVR_WID_TOP_BOTTOM, 0);
1295 aty_st_le32(OV0_SCALE_CNTL, 0);
1296 aty_st_le32(MPP_TB_CONFIG, 0);
1297 aty_st_le32(MPP_GP_CONFIG, 0);
1298 aty_st_le32(SUBPIC_CNTL, 0);
1299 aty_st_le32(VIPH_CONTROL, 0);
1300 aty_st_le32(I2C_CNTL_1, 0); /* turn off i2c */
1301 aty_st_le32(GEN_INT_CNTL, 0); /* turn off interrupts */
1302 aty_st_le32(CAP0_TRIG_CNTL, 0);
1303 aty_st_le32(CAP1_TRIG_CNTL, 0);
1305 aty_st_8(CRTC_EXT_CNTL + 1, 4); /* turn video off */
1307 aty128_set_crtc(&par->crtc, info);
1308 aty128_set_pll(&par->pll, info);
1309 aty128_set_fifo(&par->fifo_reg, info);
1311 config = aty_ld_le32(CONFIG_CNTL) & ~3;
1313 #if defined(__BIG_ENDIAN)
1314 if (par->crtc.bpp == 32)
1315 config |= 2; /* make aperture do 32 bit swapping */
1316 else if (par->crtc.bpp == 16)
1317 config |= 1; /* make aperture do 16 bit swapping */
1320 aty_st_le32(CONFIG_CNTL, config);
1321 aty_st_8(CRTC_EXT_CNTL + 1, 0); /* turn the video back on */
1323 #ifdef CONFIG_PMAC_PBOOK
1324 if (info->chip_gen == rage_M3) {
1325 aty128_set_crt_enable(info, info->crt_on);
1326 aty128_set_lcd_enable(info, info->lcd_on);
1329 if (par->accel_flags & FB_ACCELF_TEXT)
1330 aty128_init_engine(par, info);
1332 #ifdef CONFIG_FB_COMPAT_XPMAC
1333 if (!console_fb_info || console_fb_info == &info->fb_info) {
1334 struct fb_var_screeninfo var;
1337 display_info.height = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1338 display_info.width = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1339 display_info.depth = par->crtc.bpp;
1340 display_info.pitch = (par->crtc.vxres * par->crtc.bpp) >> 3;
1341 aty128_encode_var(&var, par, info);
1342 if (mac_var_to_vmode(&var, &vmode, &cmode))
1343 display_info.mode = 0;
1345 display_info.mode = vmode;
1346 strcpy(display_info.name, aty128fb_name);
1347 display_info.fb_address = info->frame_buffer_phys;
1348 display_info.cmap_adr_address = 0;
1349 display_info.cmap_data_address = 0;
1350 display_info.disp_reg_address = info->regbase_phys;
1352 #endif /* CONFIG_FB_COMPAT_XPMAC */
1353 #if defined(CONFIG_BOOTX_TEXT)
1354 btext_update_display(info->frame_buffer_phys,
1355 (((par->crtc.h_total>>16) & 0xff)+1)*8,
1356 ((par->crtc.v_total>>16) & 0x7ff)+1,
1358 par->crtc.vxres*par->crtc.bpp/8);
1359 #endif /* CONFIG_BOOTX_TEXT */
1363 * encode/decode the User Defined Part of the Display
1367 aty128_decode_var(struct fb_var_screeninfo *var, struct aty128fb_par *par,
1368 const struct fb_info_aty128 *info)
1372 if ((err = aty128_var_to_crtc(var, &par->crtc, info)))
1375 if ((err = aty128_var_to_pll(var->pixclock, &par->pll, info)))
1378 if ((err = aty128_ddafifo(&par->fifo_reg, &par->pll, par->crtc.depth, info)))
1381 if (var->accel_flags & FB_ACCELF_TEXT)
1382 par->accel_flags = FB_ACCELF_TEXT;
1384 par->accel_flags = 0;
1391 aty128_encode_var(struct fb_var_screeninfo *var,
1392 const struct aty128fb_par *par,
1393 const struct fb_info_aty128 *info)
1397 if ((err = aty128_crtc_to_var(&par->crtc, var)))
1400 if ((err = aty128_pll_to_var(&par->pll, var, info)))
1403 var->red.msb_right = 0;
1404 var->green.msb_right = 0;
1405 var->blue.msb_right = 0;
1406 var->transp.msb_right = 0;
1413 var->accel_flags = par->accel_flags;
1420 * Get the User Defined Part of the Display
1424 aty128fb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1426 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1429 aty128_encode_var(var, &info->default_par, info);
1431 *var = fb_display[con].var;
1437 * Set the User Defined Part of the Display
1441 aty128fb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *fb)
1443 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1444 struct aty128fb_par par;
1445 struct display *display;
1446 int oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldgreen, oldaccel;
1449 display = (con >= 0) ? &fb_display[con] : fb->disp;
1451 /* basic (in)sanity checks */
1456 if (var->xres > var->xres_virtual)
1457 var->xres_virtual = var->xres;
1458 if (var->yres > var->yres_virtual)
1459 var->yres_virtual = var->yres;
1461 switch (var->bits_per_pixel) {
1463 var->bits_per_pixel = 8;
1466 var->bits_per_pixel = 16;
1469 var->bits_per_pixel = 24;
1472 var->bits_per_pixel = 32;
1478 if ((err = aty128_decode_var(var, &par, info)))
1481 aty128_encode_var(var, &par, info);
1483 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_TEST)
1486 oldxres = display->var.xres;
1487 oldyres = display->var.yres;
1488 oldvxres = display->var.xres_virtual;
1489 oldvyres = display->var.yres_virtual;
1490 oldbpp = display->var.bits_per_pixel;
1491 oldgreen = display->var.green.length;
1492 oldaccel = display->var.accel_flags;
1493 display->var = *var;
1494 if (oldxres != var->xres || oldyres != var->yres ||
1495 oldvxres != var->xres_virtual || oldvyres != var->yres_virtual ||
1496 oldgreen != var->green.length || oldbpp != var->bits_per_pixel ||
1497 oldaccel != var->accel_flags) {
1499 struct fb_fix_screeninfo fix;
1501 aty128_encode_fix(&fix, &par, info);
1502 display->screen_base = info->frame_buffer;
1503 display->visual = fix.visual;
1504 display->type = fix.type;
1505 display->type_aux = fix.type_aux;
1506 display->ypanstep = fix.ypanstep;
1507 display->ywrapstep = fix.ywrapstep;
1508 display->line_length = fix.line_length;
1509 display->can_soft_blank = 1;
1510 display->inverse = 0;
1512 accel = var->accel_flags & FB_ACCELF_TEXT;
1513 aty128_set_dispsw(display, info, par.crtc.bpp, accel);
1516 display->scrollmode = SCROLL_YNOMOVE;
1518 display->scrollmode = SCROLL_YREDRAW;
1520 if (info->fb_info.changevar)
1521 (*info->fb_info.changevar)(con);
1524 if (!info->fb_info.display_fg || info->fb_info.display_fg->vc_num == con)
1525 aty128_set_par(&par, info);
1527 if (oldbpp != var->bits_per_pixel || oldgreen != var->green.length) {
1528 if ((err = fb_alloc_cmap(&display->cmap, 0, 0)))
1530 do_install_cmap(con, &info->fb_info);
1538 aty128_set_dispsw(struct display *disp,
1539 struct fb_info_aty128 *info, int bpp, int accel)
1542 #ifdef FBCON_HAS_CFB8
1544 disp->dispsw = accel ? &fbcon_aty128_8 : &fbcon_cfb8;
1547 #ifdef FBCON_HAS_CFB16
1549 disp->dispsw = accel ? &fbcon_aty128_16 : &fbcon_cfb16;
1550 disp->dispsw_data = info->fbcon_cmap.cfb16;
1553 #ifdef FBCON_HAS_CFB24
1555 disp->dispsw = accel ? &fbcon_aty128_24 : &fbcon_cfb24;
1556 disp->dispsw_data = info->fbcon_cmap.cfb24;
1559 #ifdef FBCON_HAS_CFB32
1561 disp->dispsw = accel ? &fbcon_aty128_32 : &fbcon_cfb32;
1562 disp->dispsw_data = info->fbcon_cmap.cfb32;
1566 disp->dispsw = &fbcon_dummy;
1572 aty128_encode_fix(struct fb_fix_screeninfo *fix,
1573 struct aty128fb_par *par,
1574 const struct fb_info_aty128 *info)
1576 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
1578 strcpy(fix->id, aty128fb_name);
1580 fix->smem_start = (unsigned long)info->frame_buffer_phys;
1581 fix->mmio_start = (unsigned long)info->regbase_phys;
1583 fix->smem_len = info->vram_size;
1584 fix->mmio_len = 0x1fff;
1586 fix->type = FB_TYPE_PACKED_PIXELS;
1588 fix->line_length = (par->crtc.vxres * par->crtc.bpp) >> 3;
1589 fix->visual = par->crtc.bpp == 8 ? FB_VISUAL_PSEUDOCOLOR
1590 : FB_VISUAL_DIRECTCOLOR;
1595 fix->accel = FB_ACCEL_ATI_RAGE128;
1602 * Get the Fixed Part of the Display
1605 aty128fb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *fb)
1607 const struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1608 struct aty128fb_par par;
1611 par = info->default_par;
1613 aty128_decode_var(&fb_display[con].var, &par, info);
1615 aty128_encode_fix(fix, &par, info);
1622 * Pan or Wrap the Display
1625 aty128fb_pan_display(struct fb_var_screeninfo *var, int con,
1628 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
1629 struct aty128fb_par *par = &info->current_par;
1630 u32 xoffset, yoffset;
1634 xres = (((par->crtc.h_total >> 16) & 0xff) + 1) << 3;
1635 yres = ((par->crtc.v_total >> 16) & 0x7ff) + 1;
1637 xoffset = (var->xoffset +7) & ~7;
1638 yoffset = var->yoffset;
1640 if (xoffset+xres > par->crtc.vxres || yoffset+yres > par->crtc.vyres)
1643 par->crtc.xoffset = xoffset;
1644 par->crtc.yoffset = yoffset;
1646 offset = ((yoffset * par->crtc.vxres + xoffset)*(par->crtc.bpp >> 3)) & ~7;
1648 if (par->crtc.bpp == 24)
1649 offset += 8 * (offset % 3); /* Must be multiple of 8 and 3 */
1651 aty_st_le32(CRTC_OFFSET, offset);
1662 aty128fb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1663 struct fb_info *info)
1665 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1666 struct display *disp = (con < 0) ? info->disp : (fb_display + con);
1668 if (con == fb->currcon) /* current console? */
1669 return fb_get_cmap(cmap, kspc, aty128_getcolreg, info);
1670 else if (disp->cmap.len) /* non default colormap? */
1671 fb_copy_cmap(&disp->cmap, cmap, kspc ? 0 : 2);
1673 fb_copy_cmap(fb_default_cmap((disp->var.bits_per_pixel==8) ? 256 : 32),
1674 cmap, kspc ? 0 : 2);
1684 aty128fb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
1685 struct fb_info *info)
1687 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1688 struct display *disp = (con < 0) ? info->disp : (fb_display + con);
1689 unsigned int cmap_len = (disp->var.bits_per_pixel==8) ? 256 : 32;
1691 if (disp->cmap.len != cmap_len) {
1692 int err = fb_alloc_cmap(&disp->cmap, cmap_len, 0);
1694 if (!disp->cmap.len) { /* no colormap allocated? */
1695 int size = (disp->var.bits_per_pixel <= 8) ? 256 : 32;
1696 if ((err = fb_alloc_cmap(&disp->cmap, size, 0)))
1699 if (err) return err;
1702 if (con == fb->currcon) /* current console? */
1703 return fb_set_cmap(cmap, kspc, aty128_setcolreg, info);
1705 fb_copy_cmap(cmap, &disp->cmap, kspc ? 0 : 1);
1711 * Helper function to store a single palette register
1713 static __inline__ void
1714 aty128_st_pal(u_int regno, u_int red, u_int green, u_int blue,
1715 struct fb_info_aty128 *info)
1717 /* Note: For now, on M3, we set palette on both heads, which may
1718 * be useless. Can someone with a M3 check this ?
1720 * This code would still be useful if using the second CRTC to
1724 if (info->chip_gen == rage_M3) {
1726 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PALETTE_ACCESS_CNTL);
1727 aty_st_8(PALETTE_INDEX, regno);
1728 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1730 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & ~DAC_PALETTE_ACCESS_CNTL);
1732 aty_st_8(PALETTE_INDEX, regno);
1733 aty_st_le32(PALETTE_DATA, (red<<16)|(green<<8)|blue);
1737 aty128fb_rasterimg(struct fb_info *info, int start)
1739 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
1741 if (fb->blitter_may_be_busy)
1749 aty128fb_setup(char *options)
1753 if (!options || !*options)
1756 while ((this_opt = strsep(&options, ",")) != 0) {
1757 if (!strncmp(this_opt, "font:", 5)) {
1762 for (i = 0; i < sizeof(fontname) - 1; i++)
1763 if (!*p || *p == ' ' || *p == ',')
1765 memcpy(fontname, this_opt + 5, i);
1767 } else if (!strncmp(this_opt, "noaccel", 7)) {
1769 #ifdef CONFIG_PMAC_PBOOK
1770 } else if (!strncmp(this_opt, "lcd:", 4)) {
1771 default_lcd_on = simple_strtoul(this_opt+4, NULL, 0);
1772 } else if (!strncmp(this_opt, "crt:", 4)) {
1773 default_crt_on = simple_strtoul(this_opt+4, NULL, 0);
1777 else if(!strncmp(this_opt, "nomtrr", 6)) {
1782 /* vmode and cmode depreciated */
1783 else if (!strncmp(this_opt, "vmode:", 6)) {
1784 unsigned int vmode = simple_strtoul(this_opt+6, NULL, 0);
1785 if (vmode > 0 && vmode <= VMODE_MAX)
1786 default_vmode = vmode;
1787 } else if (!strncmp(this_opt, "cmode:", 6)) {
1788 unsigned int cmode = simple_strtoul(this_opt+6, NULL, 0);
1792 default_cmode = CMODE_8;
1796 default_cmode = CMODE_16;
1800 default_cmode = CMODE_32;
1804 #endif /* CONFIG_PPC */
1806 mode_option = this_opt;
1817 aty128_init(struct fb_info_aty128 *info, const char *name)
1819 struct fb_var_screeninfo var;
1823 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1824 char *video_card = "Rage128";
1826 if (!info->vram_size) /* may have already been probed */
1827 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
1829 /* Get the chip revision */
1830 chip_rev = (aty_ld_le32(CONFIG_CNTL) >> 16) & 0x1F;
1832 /* put a name with the face */
1833 while (aci->name && info->pdev->device != aci->device) { aci++; }
1834 video_card = (char *)aci->name;
1835 info->chip_gen = aci->chip_gen;
1837 printk(KERN_INFO "aty128fb: %s [chip rev 0x%x] ", video_card, chip_rev);
1839 if (info->vram_size % (1024 * 1024) == 0)
1840 printk("%dM %s\n", info->vram_size / (1024*1024), info->mem->name);
1842 printk("%dk %s\n", info->vram_size / 1024, info->mem->name);
1845 strcpy(info->fb_info.modename, aty128fb_name);
1846 info->fb_info.node = -1;
1847 info->fb_info.fbops = &aty128fb_ops;
1848 info->fb_info.disp = &info->disp;
1849 strcpy(info->fb_info.fontname, fontname);
1850 info->fb_info.changevar = NULL;
1851 info->fb_info.switch_con = &aty128fbcon_switch;
1852 info->fb_info.updatevar = NULL;
1853 info->fb_info.blank = &aty128fbcon_blank;
1854 info->fb_info.flags = FBINFO_FLAG_DEFAULT;
1855 #ifdef CONFIG_PMAC_PBOOK
1856 info->lcd_on = default_lcd_on;
1857 info->crt_on = default_crt_on;
1862 if (_machine == _MACH_Pmac) {
1864 if (!mac_find_mode(&var, &info->fb_info, mode_option, 8))
1867 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
1868 default_vmode = VMODE_1024_768_60;
1870 /* iMacs need that resolution
1871 * PowerMac2,1 first r128 iMacs
1872 * PowerMac2,2 summer 2000 iMacs
1873 * PowerMac4,1 january 2001 iMacs "flower power"
1875 if (machine_is_compatible("PowerMac2,1") ||
1876 machine_is_compatible("PowerMac2,2") ||
1877 machine_is_compatible("PowerMac4,1"))
1878 default_vmode = VMODE_1024_768_75;
1881 if (machine_is_compatible("PowerBook2,2"))
1882 default_vmode = VMODE_800_600_60;
1884 /* PowerBook Firewire (Pismo), iBook Dual USB */
1885 if (machine_is_compatible("PowerBook3,1") ||
1886 machine_is_compatible("PowerBook4,1"))
1887 default_vmode = VMODE_1024_768_60;
1889 /* PowerBook Titanium */
1890 if (machine_is_compatible("PowerBook3,2"))
1891 default_vmode = VMODE_1152_768_60;
1893 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
1894 default_cmode = CMODE_8;
1896 if (mac_vmode_to_var(default_vmode, default_cmode, &var))
1900 #endif /* CONFIG_PPC */
1902 if (fb_find_mode(&var, &info->fb_info, mode_option, NULL, 0,
1903 &defaultmode, 8) == 0)
1908 var.accel_flags &= ~FB_ACCELF_TEXT;
1910 var.accel_flags |= FB_ACCELF_TEXT;
1912 if (aty128_decode_var(&var, &info->default_par, info)) {
1913 printk(KERN_ERR "aty128fb: Cannot set default mode.\n");
1917 /* load up the palette with default colors */
1918 for (j = 0; j < 16; j++) {
1920 info->palette[j].red = default_red[k];
1921 info->palette[j].green = default_grn[k];
1922 info->palette[j].blue = default_blu[k];
1925 /* setup the DAC the way we like it */
1926 dac = aty_ld_le32(DAC_CNTL);
1927 dac |= (DAC_8BIT_EN | DAC_RANGE_CNTL);
1929 if (info->chip_gen == rage_M3)
1930 dac |= DAC_PALETTE2_SNOOP_EN;
1931 aty_st_le32(DAC_CNTL, dac);
1933 /* turn off bus mastering, just in case */
1934 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL) | BUS_MASTER_DIS);
1936 aty128fb_set_var(&var, -1, &info->fb_info);
1937 aty128_init_engine(&info->default_par, info);
1939 board_list = aty128_board_list_add(board_list, info);
1941 if (register_framebuffer(&info->fb_info) < 0)
1944 #ifdef CONFIG_PMAC_BACKLIGHT
1945 /* Could be extended to Rage128Pro LVDS output too */
1946 if (info->chip_gen == rage_M3)
1947 register_backlight_controller(&aty128_backlight_controller, info, "ati");
1948 #endif /* CONFIG_PMAC_BACKLIGHT */
1949 #ifdef CONFIG_PMAC_PBOOK
1951 printk(KERN_WARNING "aty128fb: Not a PCI card, can't enable power management\n");
1953 info->pm_reg = pci_find_capability(info->pdev, PCI_CAP_ID_PM);
1954 pmu_register_sleep_notifier(&aty128_sleep_notifier);
1958 printk(KERN_INFO "fb%d: %s frame buffer device on %s\n",
1959 GET_FB_IDX(info->fb_info.node), aty128fb_name, name);
1961 return 1; /* success! */
1965 /* add a new card to the list ++ajoshi */
1967 fb_info_aty128 *aty128_board_list_add(struct fb_info_aty128 *board_list,
1968 struct fb_info_aty128 *new_node)
1970 struct fb_info_aty128 *i_p = board_list;
1972 new_node->next = NULL;
1973 if(board_list == NULL)
1975 while(i_p->next != NULL)
1977 i_p->next = new_node;
1987 struct pci_dev *pdev = NULL;
1988 const struct aty128_chip_info *aci = &aty128_pci_probe_list[0];
1990 while (aci->name != NULL) {
1991 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
1992 while (pdev != NULL) {
1993 if (aty128_pci_register(pdev, aci) == 0)
1995 pdev = pci_find_device(PCI_VENDOR_ID_ATI, aci->device, pdev);
2006 /* register a card ++ajoshi */
2008 aty128_pci_register(struct pci_dev *pdev,
2009 const struct aty128_chip_info *aci)
2011 struct fb_info_aty128 *info = NULL;
2012 unsigned long fb_addr, reg_addr;
2014 #if !defined(CONFIG_PPC) && !defined(__sparc__)
2015 char *bios_seg = NULL;
2018 /* Enable device in PCI config */
2019 if ((err = pci_enable_device(pdev))) {
2020 printk(KERN_ERR "aty128fb: Cannot enable PCI device: %d\n",
2025 fb_addr = pci_resource_start(pdev, 0);
2026 if (!request_mem_region(fb_addr, pci_resource_len(pdev, 0),
2028 printk(KERN_ERR "aty128fb: cannot reserve frame "
2033 reg_addr = pci_resource_start(pdev, 2);
2034 if (!request_mem_region(reg_addr, pci_resource_len(pdev, 2),
2036 printk(KERN_ERR "aty128fb: cannot reserve MMIO region\n");
2040 /* We have the resources. Now virtualize them */
2041 if (!(info = kmalloc(sizeof(struct fb_info_aty128), GFP_ATOMIC))) {
2042 printk(KERN_ERR "aty128fb: can't alloc fb_info_aty128\n");
2045 memset(info, 0, sizeof(struct fb_info_aty128));
2047 /* Copy PCI device info into info->pdev */
2052 /* Virtualize mmio region */
2053 info->regbase_phys = reg_addr;
2054 info->regbase = ioremap(reg_addr, 0x1FFF);
2059 /* Grab memory size from the card */
2060 info->vram_size = aty_ld_le32(CONFIG_MEMSIZE) & 0x03FFFFFF;
2062 /* Virtualize the framebuffer */
2063 info->frame_buffer_phys = fb_addr;
2064 info->frame_buffer = ioremap(fb_addr, info->vram_size);
2066 if (!info->frame_buffer) {
2067 iounmap((void *)info->regbase);
2071 /* If we can't test scratch registers, something is seriously wrong */
2072 if (!register_test(info)) {
2073 printk(KERN_ERR "aty128fb: Can't write to video register!\n");
2077 #if !defined(CONFIG_PPC) && !defined(__sparc__)
2078 if (!(bios_seg = aty128find_ROM(info)))
2079 printk(KERN_INFO "aty128fb: Rage128 BIOS not located. "
2082 printk(KERN_INFO "aty128fb: Rage128 BIOS located at "
2083 "segment %4.4lX\n", (unsigned long)bios_seg);
2084 aty128_get_pllinfo(info, bios_seg);
2087 aty128_timings(info);
2089 if (!aty128_init(info, "PCI"))
2094 info->mtrr.vram = mtrr_add(info->frame_buffer_phys,
2095 info->vram_size, MTRR_TYPE_WRCOMB, 1);
2096 info->mtrr.vram_valid = 1;
2097 /* let there be speed */
2098 printk(KERN_INFO "aty128fb: Rage128 MTRR set to ON\n");
2100 #endif /* CONFIG_MTRR */
2102 #ifdef CONFIG_FB_COMPAT_XPMAC
2103 if (!console_fb_info)
2104 console_fb_info = &info->fb_info;
2110 iounmap(info->frame_buffer);
2111 iounmap(info->regbase);
2115 release_mem_region(pci_resource_start(pdev, 2),
2116 pci_resource_len(pdev, 2));
2118 release_mem_region(pci_resource_start(pdev, 0),
2119 pci_resource_len(pdev, 0));
2121 release_mem_region(pci_resource_start(pdev, 1),
2122 pci_resource_len(pdev, 1));
2125 #endif /* CONFIG_PCI */
2128 /* PPC and Sparc cannot read video ROM */
2129 #if !defined(CONFIG_PPC) && !defined(__sparc__)
2131 *aty128find_ROM(struct fb_info_aty128 *info)
2138 char aty_rom_sig[] = "761295520"; /* ATI ROM Signature */
2139 char R128_sig[] = "R128"; /* Rage128 ROM identifier */
2141 for (segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
2144 rom_base = (char *)ioremap(segstart, 0x1000);
2146 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
2155 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
2156 if (aty_rom_sig[0] == *rom)
2157 if (strncmp(aty_rom_sig, rom,
2158 strlen(aty_rom_sig)) == 0)
2168 /* ATI signature found. Let's see if it's a Rage128 */
2169 for (i = 0; (i < 512) && (stage != 4); i++) {
2170 if (R128_sig[0] == *rom)
2171 if (strncmp(R128_sig, rom,
2172 strlen(R128_sig)) == 0)
2189 aty128_get_pllinfo(struct fb_info_aty128 *info, char *bios_seg)
2193 u16 bios_header_offset, pll_info_offset;
2196 bios_header = bios_seg + 0x48L;
2197 header_ptr = bios_header;
2199 bios_header_offset = readw(header_ptr);
2200 bios_header = bios_seg + bios_header_offset;
2201 bios_header += 0x30;
2203 header_ptr = bios_header;
2204 pll_info_offset = readw(header_ptr);
2205 header_ptr = bios_seg + pll_info_offset;
2207 memcpy_fromio(&pll, header_ptr, 50);
2209 info->constants.ppll_max = pll.PCLK_max_freq;
2210 info->constants.ppll_min = pll.PCLK_min_freq;
2211 info->constants.xclk = (u32)pll.XCLK;
2212 info->constants.ref_divider = (u32)pll.PCLK_ref_divider;
2213 info->constants.dotclock = (u32)pll.PCLK_ref_freq;
2215 DBG("ppll_max %d ppll_min %d xclk %d ref_divider %d dotclock %d\n",
2216 info->constants.ppll_max, info->constants.ppll_min,
2217 info->constants.xclk, info->constants.ref_divider,
2218 info->constants.dotclock);
2221 #endif /* !CONFIG_PPC */
2224 /* fill in known card constants if pll_block is not available */
2226 aty128_timings(struct fb_info_aty128 *info)
2229 /* instead of a table lookup, assume OF has properly
2230 * setup the PLL registers and use their values
2231 * to set the XCLK values and reference divider values */
2233 u32 x_mpll_ref_fb_div;
2236 unsigned PostDivSet[] =
2237 { 0, 1, 2, 4, 8, 3, 6, 12 };
2240 if (!info->constants.dotclock)
2241 info->constants.dotclock = 2950;
2244 x_mpll_ref_fb_div = aty_ld_pll(X_MPLL_REF_FB_DIV);
2245 xclk_cntl = aty_ld_pll(XCLK_CNTL) & 0x7;
2246 Nx = (x_mpll_ref_fb_div & 0x00ff00) >> 8;
2247 M = x_mpll_ref_fb_div & 0x0000ff;
2249 info->constants.xclk = round_div((2 * Nx *
2250 info->constants.dotclock), (M * PostDivSet[xclk_cntl]));
2252 info->constants.ref_divider =
2253 aty_ld_pll(PPLL_REF_DIV) & PPLL_REF_DIV_MASK;
2256 if (!info->constants.ref_divider) {
2257 info->constants.ref_divider = 0x3b;
2259 aty_st_pll(X_MPLL_REF_FB_DIV, 0x004c4c1e);
2260 aty_pll_writeupdate(info);
2262 aty_st_pll(PPLL_REF_DIV, info->constants.ref_divider);
2263 aty_pll_writeupdate(info);
2265 /* from documentation */
2266 if (!info->constants.ppll_min)
2267 info->constants.ppll_min = 12500;
2268 if (!info->constants.ppll_max)
2269 info->constants.ppll_max = 25000; /* 23000 on some cards? */
2270 if (!info->constants.xclk)
2271 info->constants.xclk = 0x1d4d; /* same as mclk */
2273 info->constants.fifo_width = 128;
2274 info->constants.fifo_depth = 32;
2276 switch (aty_ld_le32(MEM_CNTL) & 0x3) {
2278 info->mem = &sdr_128;
2281 info->mem = &sdr_sgram;
2284 info->mem = &ddr_sgram;
2287 info->mem = &sdr_sgram;
2293 aty128fbcon_switch(int con, struct fb_info *fb)
2295 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2296 struct aty128fb_par par;
2298 /* Do we have to save the colormap? */
2299 if (fb_display[info->currcon].cmap.len)
2300 fb_get_cmap(&fb_display[info->currcon].cmap, 1,
2301 aty128_getcolreg, fb);
2303 /* set the current console */
2304 info->currcon = con;
2306 aty128_decode_var(&fb_display[con].var, &par, info);
2307 aty128_set_par(&par, info);
2309 aty128_set_dispsw(&fb_display[con], info, par.crtc.bpp,
2310 par.accel_flags & FB_ACCELF_TEXT);
2312 do_install_cmap(con, fb);
2319 * Blank the display.
2322 aty128fbcon_blank(int blank, struct fb_info *fb)
2324 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2327 #ifdef CONFIG_PMAC_BACKLIGHT
2328 if ((_machine == _MACH_Pmac) && blank)
2329 set_backlight_enable(0);
2330 #endif /* CONFIG_PMAC_BACKLIGHT */
2332 if (blank & VESA_VSYNC_SUSPEND)
2334 if (blank & VESA_HSYNC_SUSPEND)
2336 if (blank & VESA_POWERDOWN)
2339 aty_st_8(CRTC_EXT_CNTL+1, state);
2341 #ifdef CONFIG_PMAC_PBOOK
2342 if (info->chip_gen == rage_M3) {
2343 aty128_set_crt_enable(info, info->crt_on && !blank);
2344 aty128_set_lcd_enable(info, info->lcd_on && !blank);
2347 #ifdef CONFIG_PMAC_BACKLIGHT
2348 if ((_machine == _MACH_Pmac) && !blank)
2349 set_backlight_enable(1);
2350 #endif /* CONFIG_PMAC_BACKLIGHT */
2355 * Read a single color register and split it into
2356 * colors/transparent. Return != 0 for invalid regno.
2359 aty128_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
2360 u_int *transp, struct fb_info *fb)
2362 struct fb_info_aty128 *info = (struct fb_info_aty128 *) fb;
2367 *red = (info->palette[regno].red<<8) | info->palette[regno].red;
2368 *green = (info->palette[regno].green<<8) | info->palette[regno].green;
2369 *blue = (info->palette[regno].blue<<8) | info->palette[regno].blue;
2376 * Set a single color register. The values supplied are already
2377 * rounded down to the hardware's capabilities (according to the
2378 * entries in the var structure). Return != 0 for invalid regno.
2381 aty128_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2382 u_int transp, struct fb_info *fb)
2384 struct fb_info_aty128 *info = (struct fb_info_aty128 *)fb;
2393 info->palette[regno].red = red;
2394 info->palette[regno].green = green;
2395 info->palette[regno].blue = blue;
2397 /* Note: For now, on M3, we set palette on both heads, which may
2398 * be useless. Can someone with a M3 check this ? */
2400 /* initialize gamma ramp for hi-color+ */
2402 if ((info->current_par.crtc.bpp > 8) && (regno == 0)) {
2405 for (i=0; i<256; i++)
2406 aty128_st_pal(i, i, i, i, info);
2409 /* initialize palette */
2413 if (info->current_par.crtc.bpp == 16)
2416 if (info->current_par.crtc.depth == 16) {
2417 aty128_st_pal(palreg/2, info->palette[regno/2].red, green,
2418 info->palette[regno/2].blue, info);
2419 green = info->palette[regno*2].green;
2422 if (info->current_par.crtc.bpp == 8 || regno < 32)
2423 aty128_st_pal(palreg, red, green, blue, info);
2426 switch (info->current_par.crtc.depth) {
2427 #ifdef FBCON_HAS_CFB16
2429 info->fbcon_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
2433 info->fbcon_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
2437 #ifdef FBCON_HAS_CFB24
2439 info->fbcon_cmap.cfb24[regno] = (regno << 16) | (regno << 8) |
2443 #ifdef FBCON_HAS_CFB32
2445 u32 i = (regno << 8) | regno;
2446 info->fbcon_cmap.cfb32[regno] = (i << 16) | i;
2456 do_install_cmap(int con, struct fb_info *info)
2458 struct display *disp = (con < 0) ? info->disp : (fb_display + con);
2461 fb_set_cmap(&disp->cmap, 1, aty128_setcolreg, info);
2463 fb_set_cmap(fb_default_cmap((disp->var.bits_per_pixel==8) ? 256 :32),
2464 1, aty128_setcolreg, info);
2467 #define ATY_MIRROR_LCD_ON 0x00000001
2468 #define ATY_MIRROR_CRT_ON 0x00000002
2470 /* out param: u32* backlight value: 0 to 15 */
2471 #define FBIO_ATY128_GET_MIRROR _IOR('@', 1, sizeof(__u32*))
2472 /* in param: u32* backlight value: 0 to 15 */
2473 #define FBIO_ATY128_SET_MIRROR _IOW('@', 2, sizeof(__u32*))
2475 static int aty128fb_ioctl(struct inode *inode, struct file *file, u_int cmd,
2476 u_long arg, int con, struct fb_info *info)
2478 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)info;
2483 #ifdef CONFIG_PMAC_PBOOK
2484 case FBIO_ATY128_SET_MIRROR:
2485 if (fb->chip_gen != rage_M3)
2487 rc = get_user(value, (__u32*)arg);
2490 fb->lcd_on = (value & 0x01) != 0;
2491 fb->crt_on = (value & 0x02) != 0;
2492 if (!fb->crt_on && !fb->lcd_on)
2494 aty128_set_crt_enable(fb, fb->crt_on);
2495 aty128_set_lcd_enable(fb, fb->lcd_on);
2497 case FBIO_ATY128_GET_MIRROR:
2498 if (fb->chip_gen != rage_M3)
2500 value = (fb->crt_on << 1) | fb->lcd_on;
2501 return put_user(value, (__u32*)arg);
2509 #ifdef CONFIG_PMAC_BACKLIGHT
2510 static int backlight_conv[] = {
2511 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2512 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2515 /* We turn off the LCD completely instead of just dimming the backlight.
2516 * This provides greater power saving and the display is useless without
2519 #define BACKLIGHT_LVDS_OFF
2520 /* That one prevents proper CRT output with LCD off */
2521 #undef BACKLIGHT_DAC_OFF
2524 aty128_set_backlight_enable(int on, int level, void* data)
2526 struct fb_info_aty128 *info = (struct fb_info_aty128 *)data;
2527 unsigned int reg = aty_ld_le32(LVDS_GEN_CNTL);
2531 reg |= LVDS_BL_MOD_EN | LVDS_BLON;
2532 if (on && level > BACKLIGHT_OFF) {
2534 if (!reg & LVDS_ON) {
2536 aty_st_le32(LVDS_GEN_CNTL, reg);
2537 (void)aty_ld_le32(LVDS_GEN_CNTL);
2540 aty_st_le32(LVDS_GEN_CNTL, reg);
2542 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2543 reg |= (backlight_conv[level] << LVDS_BL_MOD_LEVEL_SHIFT);
2544 #ifdef BACKLIGHT_LVDS_OFF
2545 reg |= LVDS_ON | LVDS_EN;
2546 reg &= ~LVDS_DISPLAY_DIS;
2548 aty_st_le32(LVDS_GEN_CNTL, reg);
2549 #ifdef BACKLIGHT_DAC_OFF
2550 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) & (~DAC_PDWN));
2553 reg &= ~LVDS_BL_MOD_LEVEL_MASK;
2554 reg |= (backlight_conv[0] << LVDS_BL_MOD_LEVEL_SHIFT);
2555 #ifdef BACKLIGHT_LVDS_OFF
2556 reg |= LVDS_DISPLAY_DIS;
2557 aty_st_le32(LVDS_GEN_CNTL, reg);
2558 (void)aty_ld_le32(LVDS_GEN_CNTL);
2560 reg &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGION);
2562 aty_st_le32(LVDS_GEN_CNTL, reg);
2563 #ifdef BACKLIGHT_DAC_OFF
2564 aty_st_le32(DAC_CNTL, aty_ld_le32(DAC_CNTL) | DAC_PDWN);
2572 aty128_set_backlight_level(int level, void* data)
2574 return aty128_set_backlight_enable(1, level, data);
2576 #endif /* CONFIG_PMAC_BACKLIGHT */
2579 * Accelerated functions
2583 aty128_rectcopy(int srcx, int srcy, int dstx, int dsty,
2584 u_int width, u_int height,
2585 struct fb_info_aty128 *info)
2587 u32 save_dp_datatype, save_dp_cntl, dstval;
2589 if (!width || !height)
2592 dstval = depth_to_dst(info->current_par.crtc.depth);
2593 if (dstval == DST_24BPP) {
2597 } else if (dstval == -EINVAL) {
2598 printk("aty128fb: invalid depth or RGBA\n");
2602 wait_for_fifo(2, info);
2603 save_dp_datatype = aty_ld_le32(DP_DATATYPE);
2604 save_dp_cntl = aty_ld_le32(DP_CNTL);
2606 wait_for_fifo(6, info);
2607 aty_st_le32(SRC_Y_X, (srcy << 16) | srcx);
2608 aty_st_le32(DP_MIX, ROP3_SRCCOPY | DP_SRC_RECT);
2609 aty_st_le32(DP_CNTL, DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM);
2610 aty_st_le32(DP_DATATYPE, save_dp_datatype | dstval | SRC_DSTCOLOR);
2612 aty_st_le32(DST_Y_X, (dsty << 16) | dstx);
2613 aty_st_le32(DST_HEIGHT_WIDTH, (height << 16) | width);
2615 info->blitter_may_be_busy = 1;
2617 wait_for_fifo(2, info);
2618 aty_st_le32(DP_DATATYPE, save_dp_datatype);
2619 aty_st_le32(DP_CNTL, save_dp_cntl);
2624 * Text mode accelerated functions
2628 fbcon_aty128_bmove(struct display *p, int sy, int sx, int dy, int dx,
2629 int height, int width)
2632 sy *= fontheight(p);
2634 dy *= fontheight(p);
2635 width *= fontwidth(p);
2636 height *= fontheight(p);
2638 aty128_rectcopy(sx, sy, dx, dy, width, height,
2639 (struct fb_info_aty128 *)p->fb_info);
2643 #ifdef FBCON_HAS_CFB8
2644 static void fbcon_aty8_putc(struct vc_data *conp, struct display *p,
2645 int c, int yy, int xx)
2647 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2649 if (fb->blitter_may_be_busy)
2652 fbcon_cfb8_putc(conp, p, c, yy, xx);
2656 static void fbcon_aty8_putcs(struct vc_data *conp, struct display *p,
2657 const unsigned short *s, int count,
2660 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2662 if (fb->blitter_may_be_busy)
2665 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
2669 static void fbcon_aty8_clear_margins(struct vc_data *conp,
2670 struct display *p, int bottom_only)
2672 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2674 if (fb->blitter_may_be_busy)
2677 fbcon_cfb8_clear_margins(conp, p, bottom_only);
2680 static struct display_switch fbcon_aty128_8 = {
2681 setup: fbcon_cfb8_setup,
2682 bmove: fbcon_aty128_bmove,
2683 clear: fbcon_cfb8_clear,
2684 putc: fbcon_aty8_putc,
2685 putcs: fbcon_aty8_putcs,
2686 revc: fbcon_cfb8_revc,
2687 clear_margins: fbcon_aty8_clear_margins,
2688 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2691 #ifdef FBCON_HAS_CFB16
2692 static void fbcon_aty16_putc(struct vc_data *conp, struct display *p,
2693 int c, int yy, int xx)
2695 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2697 if (fb->blitter_may_be_busy)
2700 fbcon_cfb16_putc(conp, p, c, yy, xx);
2704 static void fbcon_aty16_putcs(struct vc_data *conp, struct display *p,
2705 const unsigned short *s, int count,
2708 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2710 if (fb->blitter_may_be_busy)
2713 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
2717 static void fbcon_aty16_clear_margins(struct vc_data *conp,
2718 struct display *p, int bottom_only)
2720 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2722 if (fb->blitter_may_be_busy)
2725 fbcon_cfb16_clear_margins(conp, p, bottom_only);
2728 static struct display_switch fbcon_aty128_16 = {
2729 setup: fbcon_cfb16_setup,
2730 bmove: fbcon_aty128_bmove,
2731 clear: fbcon_cfb16_clear,
2732 putc: fbcon_aty16_putc,
2733 putcs: fbcon_aty16_putcs,
2734 revc: fbcon_cfb16_revc,
2735 clear_margins: fbcon_aty16_clear_margins,
2736 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2739 #ifdef FBCON_HAS_CFB24
2740 static void fbcon_aty24_putc(struct vc_data *conp, struct display *p,
2741 int c, int yy, int xx)
2743 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2745 if (fb->blitter_may_be_busy)
2748 fbcon_cfb24_putc(conp, p, c, yy, xx);
2752 static void fbcon_aty24_putcs(struct vc_data *conp, struct display *p,
2753 const unsigned short *s, int count,
2756 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2758 if (fb->blitter_may_be_busy)
2761 fbcon_cfb24_putcs(conp, p, s, count, yy, xx);
2765 static void fbcon_aty24_clear_margins(struct vc_data *conp,
2766 struct display *p, int bottom_only)
2768 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2770 if (fb->blitter_may_be_busy)
2773 fbcon_cfb24_clear_margins(conp, p, bottom_only);
2776 static struct display_switch fbcon_aty128_24 = {
2777 setup: fbcon_cfb24_setup,
2778 bmove: fbcon_aty128_bmove,
2779 clear: fbcon_cfb24_clear,
2780 putc: fbcon_aty24_putc,
2781 putcs: fbcon_aty24_putcs,
2782 revc: fbcon_cfb24_revc,
2783 clear_margins: fbcon_aty24_clear_margins,
2784 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2787 #ifdef FBCON_HAS_CFB32
2788 static void fbcon_aty32_putc(struct vc_data *conp, struct display *p,
2789 int c, int yy, int xx)
2791 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2793 if (fb->blitter_may_be_busy)
2796 fbcon_cfb32_putc(conp, p, c, yy, xx);
2800 static void fbcon_aty32_putcs(struct vc_data *conp, struct display *p,
2801 const unsigned short *s, int count,
2804 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2806 if (fb->blitter_may_be_busy)
2809 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2813 static void fbcon_aty32_clear_margins(struct vc_data *conp,
2814 struct display *p, int bottom_only)
2816 struct fb_info_aty128 *fb = (struct fb_info_aty128 *)(p->fb_info);
2818 if (fb->blitter_may_be_busy)
2821 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2824 static struct display_switch fbcon_aty128_32 = {
2825 setup: fbcon_cfb32_setup,
2826 bmove: fbcon_aty128_bmove,
2827 clear: fbcon_cfb32_clear,
2828 putc: fbcon_aty32_putc,
2829 putcs: fbcon_aty32_putcs,
2830 revc: fbcon_cfb32_revc,
2831 clear_margins: fbcon_aty32_clear_margins,
2832 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2836 #ifdef CONFIG_PMAC_PBOOK
2838 aty128_set_suspend(struct fb_info_aty128 *info, int suspend)
2846 /* Set the chip into the appropriate suspend mode (we use D2,
2847 * D3 would require a complete re-initialisation of the chip,
2848 * including PCI config registers, clocks, AGP configuration, ...)
2851 /* Make sure CRTC2 is reset. Remove that the day we decide to
2852 * actually use CRTC2 and replace it with real code for disabling
2853 * the CRTC2 output during sleep
2855 aty_st_le32(CRTC2_GEN_CNTL, aty_ld_le32(CRTC2_GEN_CNTL) &
2858 /* Set the power management mode to be PCI based */
2859 pmgt = aty_ld_pll(POWER_MANAGEMENT);
2861 pmgt &= ~PWR_MGT_MODE_MASK;
2862 pmgt |= PWR_MGT_MODE_PCI | PWR_MGT_ON | PWR_MGT_TRISTATE_MEM_EN | PWR_MGT_AUTO_PWR_UP_EN;
2863 #else /* Use this magic value for now */
2866 aty_st_pll(POWER_MANAGEMENT, pmgt);
2867 (void)aty_ld_pll(POWER_MANAGEMENT);
2868 aty_st_le32(BUS_CNTL1, 0x00000010);
2869 aty_st_le32(MEM_POWER_MISC, 0x0c830000);
2871 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command);
2872 /* Switch PCI power management to D2 */
2873 pci_write_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL,
2874 (pwr_command & ~PCI_PM_CTRL_STATE_MASK) | 2);
2875 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command);
2877 /* Switch back PCI power management to D0 */
2879 pci_write_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, 0);
2881 pci_read_config_word(info->pdev, info->pm_reg+PCI_PM_CTRL, &pwr_command);
2886 extern struct display_switch fbcon_dummy;
2889 * Save the contents of the frame buffer when we go to sleep,
2890 * and restore it when we wake up again.
2893 aty128_sleep_notify(struct pmu_sleep_notifier *self, int when)
2895 struct fb_info_aty128 *info;
2898 result = PBOOK_SLEEP_OK;
2900 for (info = board_list; info != NULL; info = info->next) {
2901 struct fb_fix_screeninfo fix;
2904 aty128fb_get_fix(&fix, fg_console, (struct fb_info *)info);
2905 nb = fb_display[fg_console].var.yres * fix.line_length;
2908 case PBOOK_SLEEP_REQUEST:
2909 info->save_framebuffer = vmalloc(nb);
2910 if (info->save_framebuffer == NULL)
2911 return PBOOK_SLEEP_REFUSE;
2913 case PBOOK_SLEEP_REJECT:
2914 if (info->save_framebuffer) {
2915 vfree(info->save_framebuffer);
2916 info->save_framebuffer = 0;
2919 case PBOOK_SLEEP_NOW:
2920 if (info->currcon >= 0)
2921 fb_display[info->currcon].dispsw = &fbcon_dummy;
2923 wait_for_idle(info);
2924 aty128_reset_engine(info);
2925 wait_for_idle(info);
2927 /* Backup fb content */
2928 if (info->save_framebuffer)
2929 memcpy_fromio(info->save_framebuffer,
2930 (void *)info->frame_buffer, nb);
2932 /* Blank display and LCD */
2933 aty128fbcon_blank(VESA_POWERDOWN+1, (struct fb_info *)info);
2935 /* Sleep the chip */
2936 aty128_set_suspend(info, 1);
2941 aty128_set_suspend(info, 0);
2943 aty128_reset_engine(info);
2944 wait_for_idle(info);
2946 /* Restore fb content */
2947 if (info->save_framebuffer) {
2948 memcpy_toio((void *)info->frame_buffer,
2949 info->save_framebuffer, nb);
2950 vfree(info->save_framebuffer);
2951 info->save_framebuffer = 0;
2954 if (info->currcon >= 0) {
2956 &fb_display[info->currcon],
2958 info->current_par.crtc.bpp,
2959 info->current_par.accel_flags & FB_ACCELF_TEXT);
2961 aty128fbcon_blank(0, (struct fb_info *)info);
2967 #endif /* CONFIG_PMAC_PBOOK */
2970 MODULE_AUTHOR("(c)1999-2000 Brad Douglas <brad@neruo.com>");
2971 MODULE_DESCRIPTION("FBDev driver for ATI Rage128 / Pro cards");
2972 MODULE_LICENSE("GPL");
2973 MODULE_PARM(noaccel, "i");
2974 MODULE_PARM_DESC(noaccel, "Disable hardware acceleration (0 or 1=disabled) (default=0)");
2975 MODULE_PARM(font, "s");
2976 MODULE_PARM_DESC(font, "Specify one of the compiled-in fonts (default=none)");
2977 MODULE_PARM(mode, "s");
2978 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
2980 MODULE_PARM(nomtrr, "i");
2981 MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
2989 printk(KERN_INFO "aty128fb: Parameter NOACCEL set\n");
2992 strncpy(fontname, font, sizeof(fontname)-1);
2993 printk(KERN_INFO "aty128fb: Parameter FONT set to %s\n", font);
2997 printk(KERN_INFO "aty128fb: Parameter MODE set to %s\n", mode);
3002 printk(KERN_INFO "aty128fb: Parameter NOMTRR set\n");
3011 cleanup_module(void)
3013 struct fb_info_aty128 *info = board_list;
3015 while (board_list) {
3017 board_list = board_list->next;
3019 unregister_framebuffer(&info->fb_info);
3021 if (info->mtrr.vram_valid)
3022 mtrr_del(info->mtrr.vram, info->frame_buffer_phys,
3024 #endif /* CONFIG_MTRR */
3025 iounmap(info->regbase);
3026 iounmap(info->frame_buffer);
3028 release_mem_region(pci_resource_start(info->pdev, 0),
3029 pci_resource_len(info->pdev, 0));
3030 release_mem_region(pci_resource_start(info->pdev, 1),
3031 pci_resource_len(info->pdev, 1));
3032 release_mem_region(pci_resource_start(info->pdev, 2),
3033 pci_resource_len(info->pdev, 2));