drivers/video/cyber2000fb.h

   1 /*
   2  *  linux/drivers/video/cyber2000fb.h
   3  *
   4  *  Copyright (C) 1998-2000 Russell King
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License version 2 as
   8  * published by the Free Software Foundation.
   9  *
  10  * Integraphics Cyber2000 frame buffer device
  11  */
  12 #include <linux/config.h>
  13
  14 /*
  15  * Internal CyberPro sizes and offsets.
  16  */
  17 #define MMIO_OFFSET     0x00800000
  18 #define MMIO_SIZE       0x000c0000
  19
  20 #define NR_PALETTE      256
  21
  22 #if defined(DEBUG) && defined(CONFIG_DEBUG_LL)
  23 static void debug_printf(char *fmt, ...)
  24 {
  25         extern void printascii(const char *);
  26         char buffer[128];
  27         va_list ap;
  28
  29         va_start(ap, fmt);
  30         vsprintf(buffer, fmt, ap);
  31         va_end(ap);
  32
  33         printascii(buffer);
  34 }
  35 #else
  36 #define debug_printf(x...) do { } while (0)
  37 #endif
  38
  39 #define PIXFORMAT_8BPP          0
  40 #define PIXFORMAT_16BPP         1
  41 #define PIXFORMAT_24BPP         2
  42 #define PIXFORMAT_32BPP         3
  43
  44 #define VISUALID_256            1
  45 #define VISUALID_64K            2
  46 #define VISUALID_16M_32         3
  47 #define VISUALID_16M            4
  48 #define VISUALID_32K            6
  49
  50 #define FUNC_CTL                0x3c
  51 #define FUNC_CTL_EXTREGENBL             0x80    /* enable access to 0xbcxxx             */
  52
  53 #define BIU_BM_CONTROL          0x3e
  54 #define BIU_BM_CONTROL_ENABLE           0x01    /* enable bus-master                    */
  55 #define BIU_BM_CONTROL_BURST            0x02    /* enable burst                         */
  56 #define BIU_BM_CONTROL_BACK2BACK        0x04    /* enable back to back                  */
  57
  58 #define X_V2_VID_MEM_START      0x40
  59 #define X_V2_VID_SRC_WIDTH      0x43
  60 #define X_V2_X_START            0x45
  61 #define X_V2_X_END              0x47
  62 #define X_V2_Y_START            0x49
  63 #define X_V2_Y_END              0x4b
  64 #define X_V2_VID_SRC_WIN_WIDTH  0x4d
  65
  66 #define Y_V2_DDA_X_INC          0x43
  67 #define Y_V2_DDA_Y_INC          0x47
  68 #define Y_V2_VID_FIFO_CTL       0x49
  69 #define Y_V2_VID_FMT            0x4b
  70 #define Y_V2_VID_DISP_CTL1      0x4c
  71 #define Y_V2_VID_FIFO_CTL1      0x4d
  72
  73 #define J_X2_VID_MEM_START      0x40
  74 #define J_X2_VID_SRC_WIDTH      0x43
  75 #define J_X2_X_START            0x47
  76 #define J_X2_X_END              0x49
  77 #define J_X2_Y_START            0x4b
  78 #define J_X2_Y_END              0x4d
  79 #define J_X2_VID_SRC_WIN_WIDTH  0x4f
  80
  81 #define K_X2_DDA_X_INIT         0x40
  82 #define K_X2_DDA_X_INC          0x42
  83 #define K_X2_DDA_Y_INIT         0x44
  84 #define K_X2_DDA_Y_INC          0x46
  85 #define K_X2_VID_FMT            0x48
  86 #define K_X2_VID_DISP_CTL1      0x49
  87
  88 #define K_CAP_X2_CTL1           0x49
  89
  90 #define CAP_X_START             0x60
  91 #define CAP_X_END               0x62
  92 #define CAP_Y_START             0x64
  93 #define CAP_Y_END               0x66
  94 #define CAP_DDA_X_INIT          0x68
  95 #define CAP_DDA_X_INC           0x6a
  96 #define CAP_DDA_Y_INIT          0x6c
  97 #define CAP_DDA_Y_INC           0x6e
  98
  99 #define MEM_CTL1                0x71
 100
 101 #define MEM_CTL2                0x72
 102 #define MEM_CTL2_SIZE_2MB               0x01
 103 #define MEM_CTL2_SIZE_4MB               0x02
 104 #define MEM_CTL2_SIZE_MASK              0x03
 105 #define MEM_CTL2_64BIT                  0x04
 106
 107 #define EXT_FIFO_CTL            0x74
 108
 109 #define CAP_PIP_X_START         0x80
 110 #define CAP_PIP_X_END           0x82
 111 #define CAP_PIP_Y_START         0x84
 112 #define CAP_PIP_Y_END           0x86
 113
 114 #define CAP_NEW_CTL1            0x88
 115
 116 #define CAP_NEW_CTL2            0x89
 117
 118 #define BM_CTRL0                0x9c
 119 #define BM_CTRL1                0x9d
 120
 121 #define CAP_MODE1               0xa4
 122 #define CAP_MODE1_8BIT                  0x01    /* enable 8bit capture mode             */
 123 #define CAP_MODE1_CCIR656               0x02    /* CCIR656 mode                         */
 124 #define CAP_MODE1_IGNOREVGT             0x04    /* ignore VGT                           */
 125 #define CAP_MODE1_ALTFIFO               0x10    /* use alternate FIFO for capture       */
 126 #define CAP_MODE1_SWAPUV                0x20    /* swap UV bytes                        */
 127 #define CAP_MODE1_MIRRORY               0x40    /* mirror vertically                    */
 128 #define CAP_MODE1_MIRRORX               0x80    /* mirror horizontally                  */
 129
 130 #define DCLK_MULT               0xb0
 131 #define DCLK_DIV                0xb1
 132 #define DCLK_DIV_VFSEL                  0x20
 133 #define MCLK_MULT               0xb2
 134 #define MCLK_DIV                0xb3
 135
 136 #define CAP_MODE2               0xa5
 137
 138 #define Y_TV_CTL                0xae
 139
 140 #define EXT_MEM_START           0xc0            /* ext start address 21 bits            */
 141 #define HOR_PHASE_SHIFT         0xc2            /* high 3 bits                          */
 142 #define EXT_SRC_WIDTH           0xc3            /* ext offset phase  10 bits            */
 143 #define EXT_SRC_HEIGHT          0xc4            /* high 6 bits                          */
 144 #define EXT_X_START             0xc5            /* ext->screen, 16 bits                 */
 145 #define EXT_X_END               0xc7            /* ext->screen, 16 bits                 */
 146 #define EXT_Y_START             0xc9            /* ext->screen, 16 bits                 */
 147 #define EXT_Y_END               0xcb            /* ext->screen, 16 bits                 */
 148 #define EXT_SRC_WIN_WIDTH       0xcd            /* 8 bits                               */
 149 #define EXT_COLOUR_COMPARE      0xce            /* 24 bits                              */
 150 #define EXT_DDA_X_INIT          0xd1            /* ext->screen 16 bits                  */
 151 #define EXT_DDA_X_INC           0xd3            /* ext->screen 16 bits                  */
 152 #define EXT_DDA_Y_INIT          0xd5            /* ext->screen 16 bits                  */
 153 #define EXT_DDA_Y_INC           0xd7            /* ext->screen 16 bits                  */
 154
 155 #define EXT_VID_FIFO_CTL        0xd9
 156
 157 #define EXT_VID_FMT             0xdb
 158 #define EXT_VID_FMT_YUV422              0x00    /* formats - does this cause conversion? */
 159 #define EXT_VID_FMT_RGB555              0x01
 160 #define EXT_VID_FMT_RGB565              0x02
 161 #define EXT_VID_FMT_RGB888_24           0x03
 162 #define EXT_VID_FMT_RGB888_32           0x04
 163 #define EXT_VID_FMT_DUP_PIX_ZOON        0x08    /* duplicate pixel zoom                 */
 164 #define EXT_VID_FMT_MOD_3RD_PIX         0x20    /* modify 3rd duplicated pixel          */
 165 #define EXT_VID_FMT_DBL_H_PIX           0x40    /* double horiz pixels                  */
 166 #define EXT_VID_FMT_UV128               0x80    /* UV data offset by 128                */
 167
 168 #define EXT_VID_DISP_CTL1       0xdc
 169 #define EXT_VID_DISP_CTL1_INTRAM        0x01    /* video pixels go to internal RAM      */
 170 #define EXT_VID_DISP_CTL1_IGNORE_CCOMP  0x02    /* ignore colour compare registers      */
 171 #define EXT_VID_DISP_CTL1_NOCLIP        0x04    /* do not clip to 16235,16240           */
 172 #define EXT_VID_DISP_CTL1_UV_AVG        0x08    /* U/V data is averaged                 */
 173 #define EXT_VID_DISP_CTL1_Y128          0x10    /* Y data offset by 128                 */
 174 #define EXT_VID_DISP_CTL1_VINTERPOL_OFF 0x20    /* vertical interpolation off           */
 175 #define EXT_VID_DISP_CTL1_FULL_WIN      0x40    /* video out window full                */
 176 #define EXT_VID_DISP_CTL1_ENABLE_WINDOW 0x80    /* enable video window                  */
 177
 178 #define EXT_VID_FIFO_CTL1       0xdd
 179
 180 #define VFAC_CTL1               0xe8
 181 #define VFAC_CTL1_CAPTURE               0x01    /* capture enable                       */
 182 #define VFAC_CTL1_VFAC_ENABLE           0x02    /* vfac enable                          */
 183 #define VFAC_CTL1_FREEZE_CAPTURE        0x04    /* freeze capture                       */
 184 #define VFAC_CTL1_FREEZE_CAPTURE_SYNC   0x08    /* sync freeze capture                  */
 185 #define VFAC_CTL1_VALIDFRAME_SRC        0x10    /* select valid frame source            */
 186 #define VFAC_CTL1_PHILIPS               0x40    /* select Philips mode                  */
 187 #define VFAC_CTL1_MODVINTERPOLCLK       0x80    /* modify vertical interpolation clocl  */
 188
 189 #define VFAC_CTL2               0xe9
 190 #define VFAC_CTL2_INVERT_VIDDATAVALID   0x01    /* invert video data valid              */
 191 #define VFAC_CTL2_INVERT_GRAPHREADY     0x02    /* invert graphic ready output sig      */
 192 #define VFAC_CTL2_INVERT_DATACLK        0x04    /* invert data clock signal             */
 193 #define VFAC_CTL2_INVERT_HSYNC          0x08    /* invert hsync input                   */
 194 #define VFAC_CTL2_INVERT_VSYNC          0x10    /* invert vsync input                   */
 195 #define VFAC_CTL2_INVERT_FRAME          0x20    /* invert frame odd/even input          */
 196 #define VFAC_CTL2_INVERT_BLANK          0x40    /* invert blank output                  */
 197 #define VFAC_CTL2_INVERT_OVSYNC         0x80    /* invert other vsync input             */
 198
 199 #define VFAC_CTL3               0xea
 200 #define VFAC_CTL3_CAP_IRQ               0x40    /* enable capture interrupt             */
 201
 202 #define CAP_MEM_START           0xeb            /* 18 bits                              */
 203 #define CAP_MAP_WIDTH           0xed            /* high 6 bits                          */
 204 #define CAP_PITCH               0xee            /* 8 bits                               */
 205
 206 #define CAP_CTL_MISC            0xef
 207 #define CAP_CTL_MISC_HDIV               0x01
 208 #define CAP_CTL_MISC_HDIV4              0x02
 209 #define CAP_CTL_MISC_ODDEVEN            0x04
 210 #define CAP_CTL_MISC_HSYNCDIV2          0x08
 211 #define CAP_CTL_MISC_SYNCTZHIGH         0x10
 212 #define CAP_CTL_MISC_SYNCTZOR           0x20
 213 #define CAP_CTL_MISC_DISPUSED           0x80
 214
 215 #define REG_BANK                0xfa
 216 #define REG_BANK_X                      0x00
 217 #define REG_BANK_Y                      0x01
 218 #define REG_BANK_W                      0x02
 219 #define REG_BANK_T                      0x03
 220 #define REG_BANK_J                      0x04
 221 #define REG_BANK_K                      0x05
 222
 223 /*
 224  * Bus-master
 225  */
 226 #define BM_VID_ADDR_LOW         0xbc040
 227 #define BM_VID_ADDR_HIGH        0xbc044
 228 #define BM_ADDRESS_LOW          0xbc080
 229 #define BM_ADDRESS_HIGH         0xbc084
 230 #define BM_LENGTH               0xbc088
 231 #define BM_CONTROL              0xbc08c
 232 #define BM_CONTROL_ENABLE               0x01    /* enable transfer                      */
 233 #define BM_CONTROL_IRQEN                0x02    /* enable IRQ at end of transfer        */
 234 #define BM_CONTROL_INIT                 0x04    /* initialise status & count            */
 235 #define BM_COUNT                0xbc090         /* read-only                            */
 236
 237 /*
 238  * Graphics Co-processor
 239  */
 240 #define CO_CMD_L_PATTERN_FGCOL  0x8000
 241 #define CO_CMD_L_INC_LEFT       0x0004
 242 #define CO_CMD_L_INC_UP         0x0002
 243
 244 #define CO_CMD_H_SRC_PIXMAP     0x2000
 245 #define CO_CMD_H_BLITTER        0x0800
 246
 247 #define CO_REG_CONTROL          0xbf011
 248 #define CO_REG_SRC_WIDTH        0xbf018
 249 #define CO_REG_PIX_FORMAT       0xbf01c
 250 #define CO_REG_FORE_MIX         0xbf048
 251 #define CO_REG_FOREGROUND       0xbf058
 252 #define CO_REG_WIDTH            0xbf060
 253 #define CO_REG_HEIGHT           0xbf062
 254 #define CO_REG_X_PHASE          0xbf078
 255 #define CO_REG_CMD_L            0xbf07c
 256 #define CO_REG_CMD_H            0xbf07e
 257 #define CO_REG_SRC_PTR          0xbf170
 258 #define CO_REG_DEST_PTR         0xbf178
 259 #define CO_REG_DEST_WIDTH       0xbf218
 260
 261 /*
 262  * Private structure
 263  */
 264 struct cfb_info;
 265
 266 struct cyberpro_info {
 267         struct pci_dev  *dev;
 268         unsigned char   *regs;
 269         char            *fb;
 270         char            dev_name[32];
 271         unsigned int    fb_size;
 272
 273         /*
 274          * The following is a pointer to be passed into the
 275          * functions below.  The modules outside the main
 276          * cyber2000fb.c driver have no knowledge as to what
 277          * is within this structure.
 278          */
 279         struct cfb_info *info;
 280
 281         /*
 282          * Use these to enable the BM or TV registers.  In an SMP
 283          * environment, these two function pointers should only be
 284          * called from the module_init() or module_exit()
 285          * functions.
 286          */
 287         void (*enable_extregs)(struct cfb_info *);
 288         void (*disable_extregs)(struct cfb_info *);
 289 };
 290
 291 /*
 292  * Note! Writing to the Cyber20x0 registers from an interrupt
 293  * routine is definitely a bad idea atm.
 294  */
 295 int cyber2000fb_attach(struct cyberpro_info *info, int idx);
 296 void cyber2000fb_detach(int idx);
 297