drivers/video/radeonfb.c

   1 /*
   2  *      drivers/video/radeonfb.c
   3  *      framebuffer driver for ATI Radeon chipset video boards
   4  *
   5  *      Copyright 2000  Ani Joshi <ajoshi@unixbox.com>
   6  *
   7  *
   8  *      ChangeLog:
   9  *      2000-08-03      initial version 0.0.1
  10  *      2000-09-10      more bug fixes, public release 0.0.5
  11  *      2001-02-19      mode bug fixes, 0.0.7
  12  *      2001-07-05      fixed scrolling issues, engine initialization,
  13  *                      and minor mode tweaking, 0.0.9
  14  *      2001-09-07      Radeon VE support, Nick Kurshev
  15  *                      blanking, pan_display, and cmap fixes, 0.1.0
  16  *      2001-10-10      Radeon 7500 and 8500 support, and experimental
  17  *                      flat panel support, 0.1.1
  18  *      2001-11-17      Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
  19  *      2001-11-18      DFP fixes, Kevin Hendricks, 0.1.3
  20  *      2001-11-29      more cmap, backlight fixes, Benjamin Herrenschmidt
  21  *      2002-01-18      DFP panel detection via BIOS, Michael Clark, 0.1.4
  22  *
  23  *      Special thanks to ATI DevRel team for their hardware donations.
  24  *
  25  */
  26
  27
  28 #define RADEON_VERSION  "0.1.4"
  29
  30
  31 #include <linux/config.h>
  32 #include <linux/module.h>
  33 #include <linux/kernel.h>
  34 #include <linux/errno.h>
  35 #include <linux/string.h>
  36 #include <linux/mm.h>
  37 #include <linux/tty.h>
  38 #include <linux/slab.h>
  39 #include <linux/delay.h>
  40 #include <linux/fb.h>
  41 #include <linux/console.h>
  42 #include <linux/selection.h>
  43 #include <linux/ioport.h>
  44 #include <linux/init.h>
  45 #include <linux/pci.h>
  46 #include <linux/vmalloc.h>
  47
  48 #include <asm/io.h>
  49 #if defined(__powerpc__)
  50 #include <asm/prom.h>
  51 #include <asm/pci-bridge.h>
  52 #include <video/macmodes.h>
  53
  54 #ifdef CONFIG_NVRAM
  55 #include <linux/nvram.h>
  56 #endif
  57
  58 #ifdef CONFIG_PMAC_BACKLIGHT
  59 #include <asm/backlight.h>
  60 #endif
  61
  62 #ifdef CONFIG_BOOTX_TEXT
  63 #include <asm/btext.h>
  64 #endif
  65
  66 #ifdef CONFIG_ADB_PMU
  67 #include <linux/adb.h>
  68 #include <linux/pmu.h>
  69 #endif
  70
  71 #endif /* __powerpc__ */
  72
  73 #include <video/fbcon.h>
  74 #include <video/fbcon-cfb8.h>
  75 #include <video/fbcon-cfb16.h>
  76 #include <video/fbcon-cfb24.h>
  77 #include <video/fbcon-cfb32.h>
  78
  79 #include "radeon.h"
  80
  81
  82 #define DEBUG   0
  83
  84 #if DEBUG
  85 #define RTRACE          printk
  86 #else
  87 #define RTRACE          if(0) printk
  88 #endif
  89
  90
  91
  92 enum radeon_chips {
  93         RADEON_QD,      /* Radeon R100 */
  94         RADEON_QE,      /* Radeon R100 */
  95         RADEON_QF,      /* Radeon R100 */
  96         RADEON_QG,      /* Radeon R100 */
  97         RADEON_QY,      /* Radeon RV100 (VE) */
  98         RADEON_QZ,      /* Radeon RV100 (VE) */
  99         RADEON_QL,      /* Radeon R200 (8500) */
 100         RADEON_QW,      /* Radeon RV200 (7500) */
 101         RADEON_LW,      /* Radeon Mobility M7 */
 102         RADEON_LY,      /* Radeon Mobility M6 */
 103         RADEON_LZ,      /* Radeon Mobility M6 */
 104         RADEON_PM       /* Radeon Mobility P/M */
 105 };
 106
 107
 108 enum radeon_montype
 109 {
 110         MT_NONE,
 111         MT_CRT,         /* CRT */
 112         MT_LCD,         /* LCD */
 113         MT_DFP,         /* DVI */
 114         MT_CTV,         /* composite TV */
 115         MT_STV          /* S-Video out */
 116 };
 117
 118
 119 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
 120         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
 121         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
 122         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
 123         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
 124         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
 125         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
 126         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
 127         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
 128         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
 129         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
 130         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
 131         { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_PM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_PM},
 132         { 0, }
 133 };
 134 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
 135
 136
 137 typedef struct {
 138         u16 reg;
 139         u32 val;
 140 } reg_val;
 141
 142
 143 /* these common regs are cleared before mode setting so they do not
 144  * interfere with anything
 145  */
 146 reg_val common_regs[] = {
 147         { OVR_CLR, 0 },
 148         { OVR_WID_LEFT_RIGHT, 0 },
 149         { OVR_WID_TOP_BOTTOM, 0 },
 150         { OV0_SCALE_CNTL, 0 },
 151         { SUBPIC_CNTL, 0 },
 152         { VIPH_CONTROL, 0 },
 153         { I2C_CNTL_1, 0 },
 154         { GEN_INT_CNTL, 0 },
 155         { CAP0_TRIG_CNTL, 0 },
 156 };
 157
 158 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
 159
 160 typedef struct {
 161         u8 clock_chip_type;
 162         u8 struct_size;
 163         u8 accelerator_entry;
 164         u8 VGA_entry;
 165         u16 VGA_table_offset;
 166         u16 POST_table_offset;
 167         u16 XCLK;
 168         u16 MCLK;
 169         u8 num_PLL_blocks;
 170         u8 size_PLL_blocks;
 171         u16 PCLK_ref_freq;
 172         u16 PCLK_ref_divider;
 173         u32 PCLK_min_freq;
 174         u32 PCLK_max_freq;
 175         u16 MCLK_ref_freq;
 176         u16 MCLK_ref_divider;
 177         u32 MCLK_min_freq;
 178         u32 MCLK_max_freq;
 179         u16 XCLK_ref_freq;
 180         u16 XCLK_ref_divider;
 181         u32 XCLK_min_freq;
 182         u32 XCLK_max_freq;
 183 } __attribute__ ((packed)) PLL_BLOCK;
 184
 185
 186 struct pll_info {
 187         int ppll_max;
 188         int ppll_min;
 189         int xclk;
 190         int ref_div;
 191         int ref_clk;
 192 };
 193
 194
 195 struct ram_info {
 196         int ml;
 197         int mb;
 198         int trcd;
 199         int trp;
 200         int twr;
 201         int cl;
 202         int tr2w;
 203         int loop_latency;
 204         int rloop;
 205 };
 206
 207
 208 struct radeon_regs {
 209         /* CRTC regs */
 210         u32 crtc_h_total_disp;
 211         u32 crtc_h_sync_strt_wid;
 212         u32 crtc_v_total_disp;
 213         u32 crtc_v_sync_strt_wid;
 214         u32 crtc_pitch;
 215         u32 crtc_gen_cntl;
 216         u32 crtc_ext_cntl;
 217         u32 dac_cntl;
 218
 219         u32 flags;
 220         u32 pix_clock;
 221         int xres, yres;
 222
 223         /* DDA regs */
 224         u32 dda_config;
 225         u32 dda_on_off;
 226
 227         /* PLL regs */
 228         u32 ppll_div_3;
 229         u32 ppll_ref_div;
 230         u32 vclk_ecp_cntl;
 231
 232         /* Flat panel regs */
 233         u32 fp_crtc_h_total_disp;
 234         u32 fp_crtc_v_total_disp;
 235         u32 fp_gen_cntl;
 236         u32 fp_h_sync_strt_wid;
 237         u32 fp_horz_stretch;
 238         u32 fp_panel_cntl;
 239         u32 fp_v_sync_strt_wid;
 240         u32 fp_vert_stretch;
 241         u32 lvds_gen_cntl;
 242         u32 lvds_pll_cntl;
 243         u32 tmds_crc;
 244         u32 tmds_transmitter_cntl;
 245
 246 #if defined(__BIG_ENDIAN)
 247         u32 surface_cntl;
 248 #endif
 249 };
 250
 251
 252 struct radeonfb_info {
 253         struct fb_info info;
 254
 255         struct radeon_regs state;
 256         struct radeon_regs init_state;
 257
 258         char name[17];
 259         char ram_type[12];
 260
 261         u32 mmio_base_phys;
 262         u32 fb_base_phys;
 263
 264         unsigned long mmio_base;
 265         unsigned long fb_base;
 266
 267         struct pci_dev *pdev;
 268
 269         unsigned char *EDID;
 270         unsigned char *bios_seg;
 271
 272         struct display disp;
 273         int currcon;
 274         struct display *currcon_display;
 275
 276         struct { u8 red, green, blue, pad; } palette[256];
 277
 278         int chipset;
 279         int video_ram;
 280         u8 rev;
 281         int pitch, bpp, depth;
 282         int xres, yres, pixclock;
 283
 284         int use_default_var;
 285         int got_dfpinfo;
 286
 287         int hasCRTC2;
 288         int crtDisp_type;
 289         int dviDisp_type;
 290
 291         int panel_xres, panel_yres;
 292         int clock;
 293         int hOver_plus, hSync_width, hblank;
 294         int vOver_plus, vSync_width, vblank;
 295         int hAct_high, vAct_high, interlaced;
 296         int synct, misc;
 297
 298         u32 dp_gui_master_cntl;
 299
 300         struct pll_info pll;
 301         int pll_output_freq, post_div, fb_div;
 302
 303         struct ram_info ram;
 304
 305         u32 hack_crtc_ext_cntl;
 306         u32 hack_crtc_v_sync_strt_wid;
 307
 308 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
 309         union {
 310 #if defined(FBCON_HAS_CFB16)
 311                 u_int16_t cfb16[16];
 312 #endif
 313 #if defined(FBCON_HAS_CFB24)
 314                 u_int32_t cfb24[16];
 315 #endif
 316 #if defined(FBCON_HAS_CFB32)
 317                 u_int32_t cfb32[16];
 318 #endif
 319         } con_cmap;
 320 #endif
 321
 322 #ifdef CONFIG_PMAC_PBOOK
 323         int pm_reg;
 324         u32 save_regs[16]; /* Add more later */
 325 #endif
 326         int asleep;
 327
 328         struct radeonfb_info *next;
 329 };
 330
 331
 332 static struct fb_var_screeninfo radeonfb_default_var = {
 333         640, 480, 640, 480, 0, 0, 8, 0,
 334         {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
 335         0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
 336         0, FB_VMODE_NONINTERLACED
 337 };
 338
 339
 340 /*
 341  * IO macros
 342  */
 343
 344 #define INREG8(addr)            readb((rinfo->mmio_base)+addr)
 345 #define OUTREG8(addr,val)       writeb(val, (rinfo->mmio_base)+addr)
 346 #define INREG(addr)             readl((rinfo->mmio_base)+addr)
 347 #define OUTREG(addr,val)        writel(val, (rinfo->mmio_base)+addr)
 348
 349 #define OUTPLL(addr,val)        OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
 350                                 OUTREG(CLOCK_CNTL_DATA, val)
 351 #define OUTPLLP(addr,val,mask)                                          \
 352         do {                                                            \
 353                 unsigned int _tmp = INPLL(addr);                        \
 354                 _tmp &= (mask);                                         \
 355                 _tmp |= (val);                                          \
 356                 OUTPLL(addr, _tmp);                                     \
 357         } while (0)
 358
 359 #define OUTREGP(addr,val,mask)                                          \
 360         do {                                                            \
 361                 unsigned int _tmp = INREG(addr);                        \
 362                 _tmp &= (mask);                                         \
 363                 _tmp |= (val);                                          \
 364                 OUTREG(addr, _tmp);                                     \
 365         } while (0)
 366
 367
 368 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, unsigned long addr)
 369 {
 370         OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
 371         return (INREG(CLOCK_CNTL_DATA));
 372 }
 373
 374 #define INPLL(addr)             _INPLL(rinfo, addr)
 375
 376 #define PRIMARY_MONITOR(rinfo)  ((rinfo->dviDisp_type != MT_NONE) &&    \
 377                                  (rinfo->dviDisp_type != MT_STV) &&     \
 378                                  (rinfo->dviDisp_type != MT_CTV) ?      \
 379                                  rinfo->dviDisp_type : rinfo->crtDisp_type)
 380
 381 static char *GET_MON_NAME(int type)
 382 {
 383         char *pret = NULL;
 384
 385         switch (type) {
 386                 case MT_NONE:
 387                         pret = "no";
 388                         break;
 389                 case MT_CRT:
 390                         pret = "CRT";
 391                         break;
 392                 case MT_DFP:
 393                         pret = "DFP";
 394                         break;
 395                 case MT_LCD:
 396                         pret = "LCD";
 397                         break;
 398                 case MT_CTV:
 399                         pret = "CTV";
 400                         break;
 401                 case MT_STV:
 402                         pret = "STV";
 403                         break;
 404         }
 405
 406         return pret;
 407 }
 408
 409
 410 /*
 411  * 2D engine routines
 412  */
 413
 414 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
 415 {
 416         int i;
 417
 418         /* initiate flush */
 419         OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
 420                 ~RB2D_DC_FLUSH_ALL);
 421
 422         for (i=0; i < 2000000; i++) {
 423                 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
 424                         break;
 425         }
 426 }
 427
 428
 429 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
 430 {
 431         int i;
 432
 433         for (i=0; i<2000000; i++)
 434                 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
 435                         return;
 436 }
 437
 438
 439 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
 440 {
 441         int i;
 442
 443         /* ensure FIFO is empty before waiting for idle */
 444         _radeon_fifo_wait (rinfo, 64);
 445
 446         for (i=0; i<2000000; i++) {
 447                 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
 448                         radeon_engine_flush (rinfo);
 449                         return;
 450                 }
 451         }
 452 }
 453
 454
 455 #define radeon_engine_idle()            _radeon_engine_idle(rinfo)
 456 #define radeon_fifo_wait(entries)       _radeon_fifo_wait(rinfo,entries)
 457
 458
 459
 460 /*
 461  * helper routines
 462  */
 463
 464 static __inline__ u32 radeon_get_dstbpp(u16 depth)
 465 {
 466         switch (depth) {
 467                 case 8:
 468                         return DST_8BPP;
 469                 case 15:
 470                         return DST_15BPP;
 471                 case 16:
 472                         return DST_16BPP;
 473                 case 32:
 474                         return DST_32BPP;
 475                 default:
 476                         return 0;
 477         }
 478 }
 479
 480
 481 static inline int var_to_depth(const struct fb_var_screeninfo *var)
 482 {
 483         if (var->bits_per_pixel != 16)
 484                 return var->bits_per_pixel;
 485         return (var->green.length == 6) ? 16 : 15;
 486 }
 487
 488
 489 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
 490 {
 491         u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
 492
 493         radeon_engine_flush (rinfo);
 494
 495         clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
 496         mclk_cntl = INPLL(MCLK_CNTL);
 497
 498         OUTPLL(MCLK_CNTL, (mclk_cntl |
 499                            FORCEON_MCLKA |
 500                            FORCEON_MCLKB |
 501                            FORCEON_YCLKA |
 502                            FORCEON_YCLKB |
 503                            FORCEON_MC |
 504                            FORCEON_AIC));
 505         rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
 506
 507         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
 508                                 SOFT_RESET_CP |
 509                                 SOFT_RESET_HI |
 510                                 SOFT_RESET_SE |
 511                                 SOFT_RESET_RE |
 512                                 SOFT_RESET_PP |
 513                                 SOFT_RESET_E2 |
 514                                 SOFT_RESET_RB |
 515                                 SOFT_RESET_HDP);
 516         INREG(RBBM_SOFT_RESET);
 517         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
 518                                 ~(SOFT_RESET_CP |
 519                                   SOFT_RESET_HI |
 520                                   SOFT_RESET_SE |
 521                                   SOFT_RESET_RE |
 522                                   SOFT_RESET_PP |
 523                                   SOFT_RESET_E2 |
 524                                   SOFT_RESET_RB |
 525                                   SOFT_RESET_HDP));
 526         INREG(RBBM_SOFT_RESET);
 527
 528         OUTPLL(MCLK_CNTL, mclk_cntl);
 529         OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
 530         OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
 531
 532         return;
 533 }
 534
 535 #define radeon_engine_reset()           _radeon_engine_reset(rinfo)
 536
 537
 538 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
 539 {
 540         switch (post_div) {
 541                 case 1:
 542                         return 0x00;
 543                 case 2:
 544                         return 0x01;
 545                 case 3:
 546                         return 0x04;
 547                 case 4:
 548                         return 0x02;
 549                 case 6:
 550                         return 0x06;
 551                 case 8:
 552                         return 0x03;
 553                 case 12:
 554                         return 0x07;
 555                 default:
 556                         return 0x02;
 557         }
 558 }
 559
 560
 561
 562 static __inline__ int round_div(int num, int den)
 563 {
 564         return (num + (den / 2)) / den;
 565 }
 566
 567
 568
 569 static __inline__ int min_bits_req(int val)
 570 {
 571         int bits_req = 0;
 572
 573         if (val == 0)
 574                 bits_req = 1;
 575
 576         while (val) {
 577                 val >>= 1;
 578                 bits_req++;
 579         }
 580
 581         return (bits_req);
 582 }
 583
 584
 585 static __inline__ int _max(int val1, int val2)
 586 {
 587         if (val1 >= val2)
 588                 return val1;
 589         else
 590                 return val2;
 591 }
 592
 593
 594
 595 /*
 596  * globals
 597  */
 598
 599 static char fontname[40] __initdata;
 600 static char *mode_option __initdata;
 601 static char noaccel __initdata = 0;
 602 static int panel_yres __initdata = 0;
 603 static char force_dfp __initdata = 0;
 604 static struct radeonfb_info *board_list = NULL;
 605
 606 #ifdef FBCON_HAS_CFB8
 607 static struct display_switch fbcon_radeon8;
 608 #endif
 609
 610
 611 /*
 612  * prototypes
 613  */
 614
 615 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
 616                              struct fb_info *info);
 617 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
 618                              struct fb_info *info);
 619 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
 620                              struct fb_info *info);
 621 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
 622                               struct fb_info *info);
 623 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
 624                               struct fb_info *info);
 625 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
 626                                  struct fb_info *info);
 627 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
 628                            unsigned long arg, int con, struct fb_info *info);
 629 static int radeonfb_switch (int con, struct fb_info *info);
 630 static int radeonfb_updatevar (int con, struct fb_info *info);
 631 static void radeonfb_blank (int blank, struct fb_info *info);
 632 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
 633 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
 634                              unsigned *blue, unsigned *transp,
 635                              struct fb_info *info);
 636 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
 637                              unsigned blue, unsigned transp, struct fb_info *info);
 638 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
 639 static void radeon_save_state (struct radeonfb_info *rinfo,
 640                                struct radeon_regs *save);
 641 static void radeon_engine_init (struct radeonfb_info *rinfo);
 642 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
 643                                     struct fb_var_screeninfo *mode);
 644 static void radeon_write_mode (struct radeonfb_info *rinfo,
 645                                struct radeon_regs *mode);
 646 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
 647 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
 648 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
 649 static int radeonfb_pci_register (struct pci_dev *pdev,
 650                                  const struct pci_device_id *ent);
 651 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
 652 static char *radeon_find_rom(struct radeonfb_info *rinfo);
 653 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
 654 static void radeon_get_moninfo (struct radeonfb_info *rinfo);
 655 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
 656 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
 657 static void radeon_get_EDID(struct radeonfb_info *rinfo);
 658 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
 659 static void radeon_update_default_var(struct radeonfb_info *rinfo);
 660
 661
 662 #ifdef CONFIG_ALL_PPC
 663 static int radeon_read_OF (struct radeonfb_info *rinfo);
 664 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
 665 extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
 666
 667 #ifdef CONFIG_PMAC_PBOOK
 668 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
 669 static struct pmu_sleep_notifier radeon_sleep_notifier = {
 670         radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
 671 };
 672 static int radeon_set_backlight_enable(int on, int level, void *data);
 673 static int radeon_set_backlight_level(int level, void *data);
 674 static struct backlight_controller radeon_backlight_controller = {
 675         radeon_set_backlight_enable,
 676         radeon_set_backlight_level
 677 };
 678 #endif /* CONFIG_PMAC_PBOOK */
 679
 680 #endif /* CONFIG_ALL_PPC */
 681
 682 static struct fb_ops radeon_fb_ops = {
 683         fb_get_fix:             radeonfb_get_fix,
 684         fb_get_var:             radeonfb_get_var,
 685         fb_set_var:             radeonfb_set_var,
 686         fb_get_cmap:            radeonfb_get_cmap,
 687         fb_set_cmap:            radeonfb_set_cmap,
 688         fb_pan_display:         radeonfb_pan_display,
 689         fb_ioctl:               radeonfb_ioctl,
 690 };
 691
 692
 693 static struct pci_driver radeonfb_driver = {
 694         name:           "radeonfb",
 695         id_table:       radeonfb_pci_table,
 696         probe:          radeonfb_pci_register,
 697         remove:         __devexit_p(radeonfb_pci_unregister),
 698 };
 699
 700
 701 int __init radeonfb_init (void)
 702 {
 703         return pci_module_init (&radeonfb_driver);
 704 }
 705
 706
 707 void __exit radeonfb_exit (void)
 708 {
 709         pci_unregister_driver (&radeonfb_driver);
 710 }
 711
 712
 713 int __init radeonfb_setup (char *options)
 714 {
 715         char *this_opt;
 716
 717         if (!options || !*options)
 718                 return 0;
 719
 720         while ((this_opt = strsep (&options, ",")) != NULL) {
 721                 if (!*this_opt)
 722                         continue;
 723                 if (!strncmp (this_opt, "font:", 5)) {
 724                         char *p;
 725                         int i;
 726
 727                         p = this_opt + 5;
 728                         for (i=0; i<sizeof (fontname) - 1; i++)
 729                                 if (!*p || *p == ' ' || *p == ',')
 730                                         break;
 731                         memcpy(fontname, this_opt + 5, i);
 732                 } else if (!strncmp(this_opt, "noaccel", 7)) {
 733                         noaccel = 1;
 734                 } else if (!strncmp(this_opt, "dfp", 3)) {
 735                         force_dfp = 1;
 736                 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
 737                         panel_yres = simple_strtoul((this_opt+11), NULL, 0);
 738                 } else
 739                         mode_option = this_opt;
 740         }
 741
 742         return 0;
 743 }
 744
 745 #ifdef MODULE
 746 module_init(radeonfb_init);
 747 module_exit(radeonfb_exit);
 748 #endif
 749
 750
 751 MODULE_AUTHOR("Ani Joshi");
 752 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
 753 MODULE_LICENSE("GPL");
 754
 755 static int radeonfb_pci_register (struct pci_dev *pdev,
 756                                   const struct pci_device_id *ent)
 757 {
 758         struct radeonfb_info *rinfo;
 759         u32 tmp;
 760         int i, j;
 761
 762         RTRACE("radeonfb_pci_register BEGIN\n");
 763
 764         rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
 765         if (!rinfo) {
 766                 printk ("radeonfb: could not allocate memory\n");
 767                 return -ENODEV;
 768         }
 769
 770         memset (rinfo, 0, sizeof (struct radeonfb_info));
 771
 772         rinfo->pdev = pdev;
 773
 774         /* enable device */
 775         {
 776                 int err;
 777
 778                 if ((err = pci_enable_device(pdev))) {
 779                         printk("radeonfb: cannot enable device\n");
 780                         kfree (rinfo);
 781                         return -ENODEV;
 782                 }
 783         }
 784
 785         /* set base addrs */
 786         rinfo->fb_base_phys = pci_resource_start (pdev, 0);
 787         rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
 788
 789         /* request the mem regions */
 790         if (!request_mem_region (rinfo->fb_base_phys,
 791                                  pci_resource_len(pdev, 0), "radeonfb")) {
 792                 printk ("radeonfb: cannot reserve FB region\n");
 793                 kfree (rinfo);
 794                 return -ENODEV;
 795         }
 796
 797         if (!request_mem_region (rinfo->mmio_base_phys,
 798                                  pci_resource_len(pdev, 2), "radeonfb")) {
 799                 printk ("radeonfb: cannot reserve MMIO region\n");
 800                 release_mem_region (rinfo->fb_base_phys,
 801                                     pci_resource_len(pdev, 0));
 802                 kfree (rinfo);
 803                 return -ENODEV;
 804         }
 805
 806         /* map the regions */
 807         rinfo->mmio_base = (unsigned long)ioremap (rinfo->mmio_base_phys,
 808                                                     RADEON_REGSIZE);
 809         if (!rinfo->mmio_base) {
 810                 printk ("radeonfb: cannot map MMIO\n");
 811                 release_mem_region (rinfo->mmio_base_phys,
 812                                     pci_resource_len(pdev, 2));
 813                 release_mem_region (rinfo->fb_base_phys,
 814                                     pci_resource_len(pdev, 0));
 815                 kfree (rinfo);
 816                 return -ENODEV;
 817         }
 818
 819         rinfo->chipset = pdev->device;
 820
 821         /* chipset */
 822         switch (pdev->device) {
 823                 case PCI_DEVICE_ID_RADEON_QD:
 824                         strcpy(rinfo->name, "Radeon QD ");
 825                         break;
 826                 case PCI_DEVICE_ID_RADEON_QE:
 827                         strcpy(rinfo->name, "Radeon QE ");
 828                         break;
 829                 case PCI_DEVICE_ID_RADEON_QF:
 830                         strcpy(rinfo->name, "Radeon QF ");
 831                         break;
 832                 case PCI_DEVICE_ID_RADEON_QG:
 833                         strcpy(rinfo->name, "Radeon QG ");
 834                         break;
 835                 case PCI_DEVICE_ID_RADEON_QY:
 836                         strcpy(rinfo->name, "Radeon QY VE ");
 837                         rinfo->hasCRTC2 = 1;
 838                         break;
 839                 case PCI_DEVICE_ID_RADEON_QZ:
 840                         strcpy(rinfo->name, "Radeon QZ VE ");
 841                         rinfo->hasCRTC2 = 1;
 842                         break;
 843                 case PCI_DEVICE_ID_RADEON_QW:
 844                         strcpy(rinfo->name, "Radeon 7500 QW ");
 845                         rinfo->hasCRTC2 = 1;
 846                         break;
 847                 case PCI_DEVICE_ID_RADEON_QL:
 848                         strcpy(rinfo->name, "Radeon 8500 QL ");
 849                         rinfo->hasCRTC2 = 1;
 850                         break;
 851                 case PCI_DEVICE_ID_RADEON_LW:
 852                         strcpy(rinfo->name, "Radeon M7 LW ");
 853                         rinfo->hasCRTC2 = 1;
 854                         break;
 855                 case PCI_DEVICE_ID_RADEON_LY:
 856                         strcpy(rinfo->name, "Radeon M6 LY ");
 857                         rinfo->hasCRTC2 = 1;
 858                         break;
 859                 case PCI_DEVICE_ID_RADEON_LZ:
 860                         strcpy(rinfo->name, "Radeon M6 LZ ");
 861                         rinfo->hasCRTC2 = 1;
 862                         break;
 863                 case PCI_DEVICE_ID_RADEON_PM:
 864                         strcpy(rinfo->name, "Radeon P/M ");
 865                         rinfo->hasCRTC2 = 1;
 866                 default:
 867                         return -ENODEV;
 868         }
 869
 870         /* framebuffer size */
 871         tmp = INREG(CONFIG_MEMSIZE);
 872
 873         /* mem size is bits [28:0], mask off the rest */
 874         rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
 875
 876         /* ram type */
 877         tmp = INREG(MEM_SDRAM_MODE_REG);
 878         switch ((MEM_CFG_TYPE & tmp) >> 30) {
 879                 case 0:
 880                         /* SDR SGRAM (2:1) */
 881                         strcpy(rinfo->ram_type, "SDR SGRAM");
 882                         rinfo->ram.ml = 4;
 883                         rinfo->ram.mb = 4;
 884                         rinfo->ram.trcd = 1;
 885                         rinfo->ram.trp = 2;
 886                         rinfo->ram.twr = 1;
 887                         rinfo->ram.cl = 2;
 888                         rinfo->ram.loop_latency = 16;
 889                         rinfo->ram.rloop = 16;
 890
 891                         break;
 892                 case 1:
 893                         /* DDR SGRAM */
 894                         strcpy(rinfo->ram_type, "DDR SGRAM");
 895                         rinfo->ram.ml = 4;
 896                         rinfo->ram.mb = 4;
 897                         rinfo->ram.trcd = 3;
 898                         rinfo->ram.trp = 3;
 899                         rinfo->ram.twr = 2;
 900                         rinfo->ram.cl = 3;
 901                         rinfo->ram.tr2w = 1;
 902                         rinfo->ram.loop_latency = 16;
 903                         rinfo->ram.rloop = 16;
 904
 905                         break;
 906                 default:
 907                         /* 64-bit SDR SGRAM */
 908                         strcpy(rinfo->ram_type, "SDR SGRAM 64");
 909                         rinfo->ram.ml = 4;
 910                         rinfo->ram.mb = 8;
 911                         rinfo->ram.trcd = 3;
 912                         rinfo->ram.trp = 3;
 913                         rinfo->ram.twr = 1;
 914                         rinfo->ram.cl = 3;
 915                         rinfo->ram.tr2w = 1;
 916                         rinfo->ram.loop_latency = 17;
 917                         rinfo->ram.rloop = 17;
 918
 919                         break;
 920         }
 921
 922         rinfo->bios_seg = radeon_find_rom(rinfo);
 923         radeon_get_pllinfo(rinfo, rinfo->bios_seg);
 924
 925         RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
 926
 927 #if !defined(__powerpc__)
 928         radeon_get_moninfo(rinfo);
 929 #else
 930         switch (pdev->device) {
 931                 case PCI_DEVICE_ID_RADEON_LW:
 932                 case PCI_DEVICE_ID_RADEON_LY:
 933                 case PCI_DEVICE_ID_RADEON_LZ:
 934                 case PCI_DEVICE_ID_RADEON_PM:
 935                         rinfo->dviDisp_type = MT_LCD;
 936                         break;
 937                 default:
 938                         radeon_get_moninfo(rinfo);
 939                         break;
 940         }
 941 #endif
 942
 943         radeon_get_EDID(rinfo);
 944
 945         if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
 946             (rinfo->crtDisp_type == MT_DFP)) {
 947                 if (!radeon_get_dfpinfo(rinfo)) {
 948                         iounmap ((void*)rinfo->mmio_base);
 949                         release_mem_region (rinfo->mmio_base_phys,
 950                                             pci_resource_len(pdev, 2));
 951                         release_mem_region (rinfo->fb_base_phys,
 952                                             pci_resource_len(pdev, 0));
 953                         kfree (rinfo);
 954                         return -ENODEV;
 955                 }
 956         }
 957
 958         rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys,
 959                                                   rinfo->video_ram);
 960         if (!rinfo->fb_base) {
 961                 printk ("radeonfb: cannot map FB\n");
 962                 iounmap ((void*)rinfo->mmio_base);
 963                 release_mem_region (rinfo->mmio_base_phys,
 964                                     pci_resource_len(pdev, 2));
 965                 release_mem_region (rinfo->fb_base_phys,
 966                                     pci_resource_len(pdev, 0));
 967                 kfree (rinfo);
 968                 return -ENODEV;
 969         }
 970
 971         /* XXX turn off accel for now, blts aren't working right */
 972         noaccel = 1;
 973
 974         /* currcon not yet configured, will be set by first switch */
 975         rinfo->currcon = -1;
 976
 977         /* One PPC, OF based cards setup the internal memory
 978          * mapping in strange ways. We change it so that the
 979          * framebuffer is mapped at 0 and given half of the card's
 980          * address space (2Gb). AGP is mapped high (0xe0000000) and
 981          * can use up to 512Mb. Once DRI is fully implemented, we
 982          * will have to setup the PCI remapper to remap the agp_special_page
 983          * memory page somewhere between those regions so that the card
 984          * use a normal PCI bus master cycle to access the ring read ptr.
 985          * --BenH.
 986          */
 987 #ifdef CONFIG_ALL_PPC
 988         if (rinfo->hasCRTC2)
 989                 OUTREG(CRTC2_GEN_CNTL,
 990                         (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
 991         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
 992         OUTREG(MC_FB_LOCATION, 0x7fff0000);
 993         OUTREG(MC_AGP_LOCATION, 0xffffe000);
 994         OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
 995         if (rinfo->hasCRTC2)
 996                 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
 997         OUTREG(SRC_OFFSET, 0x00000000);
 998         OUTREG(DST_OFFSET, 0x00000000);
 999         mdelay(10);
1000         OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
1001 #endif /* CONFIG_ALL_PPC */
1002
1003         /* set all the vital stuff */
1004         radeon_set_fbinfo (rinfo);
1005
1006         /* save current mode regs before we switch into the new one
1007          * so we can restore this upon __exit
1008          */
1009         radeon_save_state (rinfo, &rinfo->init_state);
1010
1011         /* init palette */
1012         for (i=0; i<16; i++) {
1013                 j = color_table[i];
1014                 rinfo->palette[i].red = default_red[j];
1015                 rinfo->palette[i].green = default_grn[j];
1016                 rinfo->palette[i].blue = default_blu[j];
1017         }
1018
1019         pci_set_drvdata(pdev, rinfo);
1020         rinfo->next = board_list;
1021         board_list = rinfo;
1022
1023         if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
1024                 printk ("radeonfb: could not register framebuffer\n");
1025                 iounmap ((void*)rinfo->fb_base);
1026                 iounmap ((void*)rinfo->mmio_base);
1027                 release_mem_region (rinfo->mmio_base_phys,
1028                                     pci_resource_len(pdev, 2));
1029                 release_mem_region (rinfo->fb_base_phys,
1030                                     pci_resource_len(pdev, 0));
1031                 kfree (rinfo);
1032                 return -ENODEV;
1033         }
1034
1035
1036         if (!noaccel) {
1037                 /* initialize the engine */
1038                 radeon_engine_init (rinfo);
1039         }
1040
1041 #ifdef CONFIG_PMAC_BACKLIGHT
1042         if (rinfo->dviDisp_type == MT_LCD)
1043                 register_backlight_controller(&radeon_backlight_controller,
1044                                               rinfo, "ati");
1045 #endif
1046
1047 #ifdef CONFIG_PMAC_PBOOK
1048         if (rinfo->dviDisp_type == MT_LCD) {
1049                 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1050                 if (rinfo->pm_reg) {
1051                         printk("radeonfb: pm reg @%x, clk_pwrmgt: %x, pll_pwrmgt: %x"
1052                                 ", mdll_cko: %x\n", rinfo->pm_reg, INPLL(CLK_PWRMGT_CNTL),
1053                                 INPLL(PLL_PWRMGT_CNTL), INPLL(MDLL_CKO));
1054                         /* Fixup some PLL reg values for proper power management */
1055                         OUTPLL(PLL_PWRMGT_CNTL, 0xc01f);
1056                         OUTPLL(MDLL_CKO, 0x043c);
1057                         pmu_register_sleep_notifier(&radeon_sleep_notifier);
1058                 }
1059         }
1060 #endif
1061
1062         printk ("radeonfb: ATI %s %s %d MB\n", rinfo->name, rinfo->ram_type,
1063                 (rinfo->video_ram/(1024*1024)));
1064
1065         if (rinfo->hasCRTC2) {
1066                 printk("radeonfb: DVI port %s monitor connected\n",
1067                         GET_MON_NAME(rinfo->dviDisp_type));
1068                 printk("radeonfb: CRT port %s monitor connected\n",
1069                         GET_MON_NAME(rinfo->crtDisp_type));
1070         } else {
1071                 printk("radeonfb: CRT port %s monitor connected\n",
1072                         GET_MON_NAME(rinfo->crtDisp_type));
1073         }
1074
1075         RTRACE("radeonfb_pci_register END\n");
1076
1077         return 0;
1078 }
1079
1080
1081
1082 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
1083 {
1084         struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
1085
1086         if (!rinfo)
1087                 return;
1088
1089         /* restore original state */
1090         radeon_write_mode (rinfo, &rinfo->init_state);
1091
1092         unregister_framebuffer ((struct fb_info *) rinfo);
1093
1094         iounmap ((void*)rinfo->mmio_base);
1095         iounmap ((void*)rinfo->fb_base);
1096
1097         release_mem_region (rinfo->mmio_base_phys,
1098                             pci_resource_len(pdev, 2));
1099         release_mem_region (rinfo->fb_base_phys,
1100                             pci_resource_len(pdev, 0));
1101
1102         kfree (rinfo);
1103 }
1104
1105
1106
1107 static char *radeon_find_rom(struct radeonfb_info *rinfo)
1108 {
1109 #if defined(__i386__)
1110         u32  segstart;
1111         char *rom_base;
1112         char *rom;
1113         int  stage;
1114         int  i,j;
1115         char aty_rom_sig[] = "761295520";
1116         char *radeon_sig[] = {
1117           "RG6",
1118           "RADEON"
1119         };
1120
1121         for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
1122
1123                 stage = 1;
1124
1125                 rom_base = (char *)ioremap(segstart, 0x1000);
1126
1127                 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
1128                         stage = 2;
1129
1130
1131                 if (stage != 2) {
1132                         iounmap(rom_base);
1133                         continue;
1134                 }
1135
1136                 rom = rom_base;
1137
1138                 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
1139                         if (aty_rom_sig[0] == *rom)
1140                                 if (strncmp(aty_rom_sig, rom,
1141                                                 strlen(aty_rom_sig)) == 0)
1142                                         stage = 3;
1143                         rom++;
1144                 }
1145                 if (stage != 3) {
1146                         iounmap(rom_base);
1147                         continue;
1148                 }
1149                 rom = rom_base;
1150
1151                 for (i = 0; (i < 512) && (stage != 4); i++) {
1152                     for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
1153                         if (radeon_sig[j][0] == *rom)
1154                                 if (strncmp(radeon_sig[j], rom,
1155                                             strlen(radeon_sig[j])) == 0) {
1156                                               stage = 4;
1157                                               break;
1158                                             }
1159                     }
1160                         rom++;
1161                 }
1162                 if (stage != 4) {
1163                         iounmap(rom_base);
1164                         continue;
1165                 }
1166
1167                 return rom_base;
1168         }
1169 #endif
1170         return NULL;
1171 }
1172
1173
1174
1175
1176 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
1177 {
1178         void *bios_header;
1179         void *header_ptr;
1180         u16 bios_header_offset, pll_info_offset;
1181         PLL_BLOCK pll;
1182
1183         if (bios_seg) {
1184                 bios_header = bios_seg + 0x48L;
1185                 header_ptr  = bios_header;
1186
1187                 bios_header_offset = readw(header_ptr);
1188                 bios_header = bios_seg + bios_header_offset;
1189                 bios_header += 0x30;
1190
1191                 header_ptr = bios_header;
1192                 pll_info_offset = readw(header_ptr);
1193                 header_ptr = bios_seg + pll_info_offset;
1194
1195                 memcpy_fromio(&pll, header_ptr, 50);
1196
1197                 rinfo->pll.xclk = (u32)pll.XCLK;
1198                 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
1199                 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
1200                 rinfo->pll.ppll_min = pll.PCLK_min_freq;
1201                 rinfo->pll.ppll_max = pll.PCLK_max_freq;
1202
1203                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
1204                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
1205         } else {
1206 #ifdef CONFIG_ALL_PPC
1207                 if (radeon_read_OF(rinfo)) {
1208                         unsigned int tmp, Nx, M, ref_div, xclk;
1209
1210                         tmp = INPLL(M_SPLL_REF_FB_DIV);
1211                         ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
1212
1213                         Nx = (tmp & 0xff00) >> 8;
1214                         M = (tmp & 0xff);
1215                         xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
1216                                 (2 * M)));
1217
1218                         rinfo->pll.xclk = xclk;
1219                         rinfo->pll.ref_div = ref_div;
1220                         rinfo->pll.ppll_min = 12000;
1221                         rinfo->pll.ppll_max = 35000;
1222
1223                         printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
1224                                 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
1225
1226                         return;
1227                 }
1228 #endif
1229                 /* no BIOS or BIOS not found, use defaults */
1230                 switch (rinfo->chipset) {
1231                         case PCI_DEVICE_ID_RADEON_QW:
1232                                 rinfo->pll.ppll_max = 35000;
1233                                 rinfo->pll.ppll_min = 12000;
1234                                 rinfo->pll.xclk = 23000;
1235                                 rinfo->pll.ref_div = 12;
1236                                 rinfo->pll.ref_clk = 2700;
1237                                 break;
1238                         case PCI_DEVICE_ID_RADEON_QL:
1239                                 rinfo->pll.ppll_max = 35000;
1240                                 rinfo->pll.ppll_min = 12000;
1241                                 rinfo->pll.xclk = 27500;
1242                                 rinfo->pll.ref_div = 12;
1243                                 rinfo->pll.ref_clk = 2700;
1244                                 break;
1245                         case PCI_DEVICE_ID_RADEON_QD:
1246                         case PCI_DEVICE_ID_RADEON_QE:
1247                         case PCI_DEVICE_ID_RADEON_QF:
1248                         case PCI_DEVICE_ID_RADEON_QG:
1249                         default:
1250                                 rinfo->pll.ppll_max = 35000;
1251                                 rinfo->pll.ppll_min = 12000;
1252                                 rinfo->pll.xclk = 16600;
1253                                 rinfo->pll.ref_div = 67;
1254                                 rinfo->pll.ref_clk = 2700;
1255                                 break;
1256                 }
1257
1258                 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
1259                         rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
1260         }
1261 }
1262
1263
1264 static void radeon_get_moninfo (struct radeonfb_info *rinfo)
1265 {
1266         unsigned int tmp;
1267
1268         if (force_dfp) {
1269                 rinfo->dviDisp_type = MT_DFP;
1270                 return;
1271         }
1272
1273         tmp = INREG(RADEON_BIOS_4_SCRATCH);
1274
1275         if (rinfo->hasCRTC2) {
1276                 /* primary DVI port */
1277                 if (tmp & 0x08)
1278                         rinfo->dviDisp_type = MT_DFP;
1279                 else if (tmp & 0x4)
1280                         rinfo->dviDisp_type = MT_LCD;
1281                 else if (tmp & 0x200)
1282                         rinfo->dviDisp_type = MT_CRT;
1283                 else if (tmp & 0x10)
1284                         rinfo->dviDisp_type = MT_CTV;
1285                 else if (tmp & 0x20)
1286                         rinfo->dviDisp_type = MT_STV;
1287
1288                 /* secondary CRT port */
1289                 if (tmp & 0x2)
1290                         rinfo->crtDisp_type = MT_CRT;
1291                 else if (tmp & 0x800)
1292                         rinfo->crtDisp_type = MT_DFP;
1293                 else if (tmp & 0x400)
1294                         rinfo->crtDisp_type = MT_LCD;
1295                 else if (tmp & 0x1000)
1296                         rinfo->crtDisp_type = MT_CTV;
1297                 else if (tmp & 0x2000)
1298                         rinfo->crtDisp_type = MT_STV;
1299         } else {
1300                 rinfo->dviDisp_type = MT_NONE;
1301
1302                 tmp = INREG(FP_GEN_CNTL);
1303
1304                 if (tmp & FP_EN_TMDS)
1305                         rinfo->crtDisp_type = MT_DFP;
1306                 else
1307                         rinfo->crtDisp_type = MT_CRT;
1308         }
1309 }
1310
1311
1312
1313 static void radeon_get_EDID(struct radeonfb_info *rinfo)
1314 {
1315 #ifdef CONFIG_ALL_PPC
1316         if (!radeon_get_EDID_OF(rinfo))
1317                 RTRACE("radeonfb: could not retrieve EDID from OF\n");
1318 #else
1319         /* XXX use other methods later */
1320 #endif
1321 }
1322
1323
1324 #ifdef CONFIG_ALL_PPC
1325 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
1326 {
1327         struct device_node *dp;
1328         unsigned char *pedid = NULL;
1329
1330         dp = pci_device_to_OF_node(rinfo->pdev);
1331         pedid = (unsigned char *) get_property(dp, "DFP,EDID", 0);
1332         if (!pedid)
1333                 pedid = (unsigned char *) get_property(dp, "LCD,EDID", 0);
1334         if (!pedid)
1335                 pedid = (unsigned char *) get_property(dp, "EDID", 0);
1336
1337         if (pedid) {
1338                 rinfo->EDID = pedid;
1339                 return 1;
1340         } else
1341                 return 0;
1342 }
1343 #endif /* CONFIG_ALL_PPC */
1344
1345
1346 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
1347 {
1348         unsigned char *block = rinfo->EDID;
1349
1350         if (!block)
1351                 return 0;
1352
1353         /* jump to the detailed timing block section */
1354         block += 54;
1355
1356         rinfo->clock = (block[0] + (block[1] << 8));
1357         rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
1358         rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
1359         rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
1360         rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1361         rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1362         rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1363         rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1364         rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1365         rinfo->interlaced = ((block[17] & 0x80) >> 7);
1366         rinfo->synct = ((block[17] & 0x18) >> 3);
1367         rinfo->misc = ((block[17] & 0x06) >> 1);
1368         rinfo->hAct_high = rinfo->vAct_high = 0;
1369         if (rinfo->synct == 3) {
1370                 if (rinfo->misc & 2)
1371                         rinfo->hAct_high = 1;
1372                 if (rinfo->misc & 1)
1373                         rinfo->vAct_high = 1;
1374         }
1375
1376         printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1377                 rinfo->panel_xres, rinfo->panel_yres);
1378
1379         rinfo->got_dfpinfo = 1;
1380
1381         return 1;
1382 }
1383
1384
1385 static void radeon_update_default_var(struct radeonfb_info *rinfo)
1386 {
1387         struct fb_var_screeninfo *var = &radeonfb_default_var;
1388
1389         var->xres = rinfo->panel_xres;
1390         var->yres = rinfo->panel_yres;
1391         var->xres_virtual = rinfo->panel_xres;
1392         var->yres_virtual = rinfo->panel_yres;
1393         var->xoffset = var->yoffset = 0;
1394         var->bits_per_pixel = 8;
1395         var->pixclock = 100000000 / rinfo->clock;
1396         var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1397         var->right_margin = rinfo->hOver_plus;
1398         var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1399         var->lower_margin = rinfo->vOver_plus;
1400         var->hsync_len = rinfo->hSync_width;
1401         var->vsync_len = rinfo->vSync_width;
1402         var->sync = 0;
1403         if (rinfo->synct == 3) {
1404                 if (rinfo->hAct_high)
1405                         var->sync |= FB_SYNC_HOR_HIGH_ACT;
1406                 if (rinfo->vAct_high)
1407                         var->sync |= FB_SYNC_VERT_HIGH_ACT;
1408         }
1409
1410         var->vmode = 0;
1411         if (rinfo->interlaced)
1412                 var->vmode |= FB_VMODE_INTERLACED;
1413
1414         rinfo->use_default_var = 1;
1415 }
1416
1417
1418 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1419 {
1420         char *fpbiosstart, *tmp, *tmp0;
1421         char stmp[30];
1422         int i;
1423
1424         if (!rinfo->bios_seg)
1425                 return 0;
1426
1427         if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1428                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1429                 return 0;
1430         }
1431
1432         if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1433                 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1434                 return 0;
1435         }
1436
1437         for(i=0; i<24; i++)
1438                 stmp[i] = readb(tmp+i+1);
1439         stmp[24] = 0;
1440         printk("radeonfb: panel ID string: %s\n", stmp);
1441         rinfo->panel_xres = readw(tmp + 25);
1442         rinfo->panel_yres = readw(tmp + 27);
1443         printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1444                 rinfo->panel_xres, rinfo->panel_yres);
1445
1446         for(i=0; i<20; i++) {
1447                 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1448                 if (tmp0 == 0)
1449                         break;
1450                 if ((readw(tmp0) == rinfo->panel_xres) &&
1451                     (readw(tmp0+2) == rinfo->panel_yres)) {
1452                         rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1453                         rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1454                         rinfo->hSync_width = readb(tmp0+23) * 8;
1455                         rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1456                         rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1457                         rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1458                         rinfo->clock = readw(tmp0+9);
1459
1460                         rinfo->got_dfpinfo = 1;
1461                         return 1;
1462                 }
1463         }
1464
1465         return 0;
1466 }
1467
1468
1469
1470 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1471 {
1472         unsigned int tmp;
1473         unsigned short a, b;
1474
1475         if (radeon_get_dfpinfo_BIOS(rinfo))
1476                 radeon_update_default_var(rinfo);
1477
1478         if (radeon_dfp_parse_EDID(rinfo))
1479                 radeon_update_default_var(rinfo);
1480
1481         if (!rinfo->got_dfpinfo) {
1482                 /*
1483                  * it seems all else has failed now and we
1484                  * resort to probing registers for our DFP info
1485                  */
1486                 if (panel_yres) {
1487                         rinfo->panel_yres = panel_yres;
1488                 } else {
1489                         tmp = INREG(FP_VERT_STRETCH);
1490                         tmp &= 0x00fff000;
1491                         rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1492                 }
1493
1494                 switch (rinfo->panel_yres) {
1495                         case 480:
1496                                 rinfo->panel_xres = 640;
1497                                 break;
1498                         case 600:
1499                                 rinfo->panel_xres = 800;
1500                                 break;
1501                         case 768:
1502 #if defined(__powerpc__)
1503                                 if (rinfo->dviDisp_type == MT_LCD)
1504                                         rinfo->panel_xres = 1152;
1505                                 else
1506 #endif
1507                                 rinfo->panel_xres = 1024;
1508                                 break;
1509                         case 1024:
1510                                 rinfo->panel_xres = 1280;
1511                                 break;
1512                         case 1050:
1513                                 rinfo->panel_xres = 1400;
1514                                 break;
1515                         case 1200:
1516                                 rinfo->panel_xres = 1600;
1517                                 break;
1518                         default:
1519                                 printk("radeonfb: Failed to detect DFP panel size\n");
1520                                 return 0;
1521                 }
1522
1523                 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1524                         rinfo->panel_xres, rinfo->panel_yres);
1525
1526                 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1527                 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1528                 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1529                 rinfo->hblank = (a - b + 1) * 8;
1530
1531                 tmp = INREG(FP_H_SYNC_STRT_WID);
1532                 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1533                                         FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1534                 rinfo->hOver_plus *= 8;
1535                 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1536                                         FP_H_SYNC_WID_SHIFT);
1537                 rinfo->hSync_width *= 8;
1538                 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1539                 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1540                 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1541                 rinfo->vblank = a - b /* + 24 */ ;
1542
1543                 tmp = INREG(FP_V_SYNC_STRT_WID);
1544                 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1545                                         - b + 1;
1546                 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1547                                         FP_V_SYNC_WID_SHIFT);
1548
1549                 return 1;
1550         }
1551
1552         return 1;
1553 }
1554
1555
1556 #ifdef CONFIG_ALL_PPC
1557 static int radeon_read_OF (struct radeonfb_info *rinfo)
1558 {
1559         struct device_node *dp;
1560         unsigned int *xtal;
1561
1562         dp = pci_device_to_OF_node(rinfo->pdev);
1563
1564         xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0);
1565
1566         rinfo->pll.ref_clk = *xtal / 10;
1567
1568         if (*xtal)
1569                 return 1;
1570         else
1571                 return 0;
1572 }
1573 #endif
1574
1575
1576 static void radeon_engine_init (struct radeonfb_info *rinfo)
1577 {
1578         u32 temp;
1579
1580         /* disable 3D engine */
1581         OUTREG(RB3D_CNTL, 0);
1582
1583         radeon_engine_reset ();
1584
1585         radeon_fifo_wait (1);
1586         OUTREG(DSTCACHE_MODE, 0);
1587
1588         /* XXX */
1589         rinfo->pitch = ((rinfo->xres * (rinfo->bpp / 8) + 0x3f)) >> 6;
1590
1591         radeon_fifo_wait (1);
1592         temp = INREG(DEFAULT_PITCH_OFFSET);
1593         OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1594                                       (rinfo->pitch << 0x16)));
1595
1596         radeon_fifo_wait (1);
1597         OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1598
1599         radeon_fifo_wait (1);
1600         OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1601                                          DEFAULT_SC_BOTTOM_MAX));
1602
1603         temp = radeon_get_dstbpp(rinfo->depth);
1604         rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1605         radeon_fifo_wait (1);
1606         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1607                                     GMC_BRUSH_SOLID_COLOR |
1608                                     GMC_SRC_DATATYPE_COLOR));
1609
1610         radeon_fifo_wait (7);
1611
1612         /* clear line drawing regs */
1613         OUTREG(DST_LINE_START, 0);
1614         OUTREG(DST_LINE_END, 0);
1615
1616         /* set brush color regs */
1617         OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1618         OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1619
1620         /* set source color regs */
1621         OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1622         OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1623
1624         /* default write mask */
1625         OUTREG(DP_WRITE_MSK, 0xffffffff);
1626
1627         radeon_engine_idle ();
1628 }
1629
1630
1631
1632 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1633 {
1634         struct fb_info *info;
1635
1636         info = &rinfo->info;
1637
1638         strcpy (info->modename, rinfo->name);
1639         info->node = -1;
1640         info->flags = FBINFO_FLAG_DEFAULT;
1641         info->fbops = &radeon_fb_ops;
1642         info->display_fg = NULL;
1643         strncpy (info->fontname, fontname, sizeof (info->fontname));
1644         info->fontname[sizeof (info->fontname) - 1] = 0;
1645         info->changevar = NULL;
1646         info->switch_con = radeonfb_switch;
1647         info->updatevar = radeonfb_updatevar;
1648         info->blank = radeonfb_blank;
1649
1650         if (radeon_init_disp (rinfo) < 0)
1651                 return -1;
1652
1653         return 0;
1654 }
1655
1656
1657
1658 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1659 {
1660         struct fb_info *info;
1661         struct display *disp;
1662
1663         info = &rinfo->info;
1664         disp = &rinfo->disp;
1665
1666         disp->var = radeonfb_default_var;
1667 #if defined(__powerpc__)
1668         if (rinfo->dviDisp_type == MT_LCD) {
1669                 if (mac_vmode_to_var(VMODE_1152_768_60, CMODE_8, &disp->var))
1670                         disp->var = radeonfb_default_var;
1671         }
1672 #endif
1673
1674         rinfo->depth = var_to_depth(&disp->var);
1675         rinfo->bpp = disp->var.bits_per_pixel;
1676
1677         info->disp = disp;
1678
1679         radeon_set_dispsw (rinfo, disp);
1680
1681         if (noaccel)
1682                 disp->scrollmode = SCROLL_YREDRAW;
1683         else
1684                 disp->scrollmode = 0;
1685
1686         rinfo->currcon_display = disp;
1687
1688         if ((radeon_init_disp_var (rinfo)) < 0)
1689                 return -1;
1690
1691         return 0;
1692 }
1693
1694
1695
1696 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
1697 {
1698 #ifndef MODULE
1699         if (mode_option)
1700                 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
1701                               NULL, 0, NULL, 8);
1702         else
1703 #endif
1704 #if defined(__powerpc__)
1705         if (rinfo->dviDisp_type == MT_LCD) {
1706                 if (mac_vmode_to_var(VMODE_1152_768_60, CMODE_8, &rinfo->disp.var))
1707                         rinfo->disp.var = radeonfb_default_var;
1708         }
1709         else
1710 #endif
1711         if (rinfo->use_default_var)
1712                 /* We will use the modified default far */
1713                 rinfo->disp.var = radeonfb_default_var;
1714         else
1715
1716                 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
1717                               NULL, 0, NULL, 0);
1718
1719         if (noaccel)
1720                 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
1721         else
1722                 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
1723
1724         return 0;
1725 }
1726
1727
1728
1729 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
1730
1731 {
1732         int accel;
1733
1734         accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1735
1736         disp->dispsw_data = NULL;
1737
1738         disp->screen_base = (char*)rinfo->fb_base;
1739         disp->type = FB_TYPE_PACKED_PIXELS;
1740         disp->type_aux = 0;
1741         disp->ypanstep = 1;
1742         disp->ywrapstep = 0;
1743         disp->can_soft_blank = 1;
1744         disp->inverse = 0;
1745
1746         switch (disp->var.bits_per_pixel) {
1747 #ifdef FBCON_HAS_CFB8
1748                 case 8:
1749                         disp->dispsw = &fbcon_cfb8;
1750                         disp->visual = FB_VISUAL_PSEUDOCOLOR;
1751                         disp->line_length = disp->var.xres_virtual;
1752                         break;
1753 #endif
1754 #ifdef FBCON_HAS_CFB16
1755                 case 16:
1756                         disp->dispsw = &fbcon_cfb16;
1757                         disp->dispsw_data = &rinfo->con_cmap.cfb16;
1758                         disp->visual = FB_VISUAL_DIRECTCOLOR;
1759                         disp->line_length = disp->var.xres_virtual * 2;
1760                         break;
1761 #endif
1762 #ifdef FBCON_HAS_CFB32
1763                 case 24:
1764                         disp->dispsw = &fbcon_cfb24;
1765                         disp->dispsw_data = &rinfo->con_cmap.cfb24;
1766                         disp->visual = FB_VISUAL_DIRECTCOLOR;
1767                         disp->line_length = disp->var.xres_virtual * 4;
1768                         break;
1769 #endif
1770 #ifdef FBCON_HAS_CFB32
1771                 case 32:
1772                         disp->dispsw = &fbcon_cfb32;
1773                         disp->dispsw_data = &rinfo->con_cmap.cfb32;
1774                         disp->visual = FB_VISUAL_DIRECTCOLOR;
1775                         disp->line_length = disp->var.xres_virtual * 4;
1776                         break;
1777 #endif
1778                 default:
1779                         printk ("radeonfb: setting fbcon_dummy renderer\n");
1780                         disp->dispsw = &fbcon_dummy;
1781         }
1782
1783         return;
1784 }
1785
1786
1787
1788 static void do_install_cmap(int con, struct fb_info *info)
1789 {
1790         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1791
1792         if (con != rinfo->currcon)
1793                 return;
1794
1795         if (fb_display[con].cmap.len)
1796                 fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
1797         else {
1798                 int size = radeon_get_cmap_len(&fb_display[con].var);
1799                 fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
1800         }
1801 }
1802
1803
1804
1805 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
1806                                 struct fb_var_screeninfo *var,
1807                                 struct fb_var_screeninfo *v,
1808                                 int nom, int den)
1809 {
1810         static struct {
1811                 int xres, yres;
1812         } modes[] = {
1813                 {1600, 1280},
1814                 {1280, 1024},
1815                 {1024, 768},
1816                 {800, 600},
1817                 {640, 480},
1818                 {-1, -1}
1819         };
1820         int i;
1821
1822         /* use highest possible virtual resolution */
1823         if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1824                 printk("radeonfb: using max available virtual resolution\n");
1825                 for (i=0; modes[i].xres != -1; i++) {
1826                         if (modes[i].xres * nom / den * modes[i].yres <
1827                             rinfo->video_ram / 2)
1828                                 break;
1829                 }
1830                 if (modes[i].xres == -1) {
1831                         printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1832                         return -EINVAL;
1833                 }
1834                 v->xres_virtual = modes[i].xres;
1835                 v->yres_virtual = modes[i].yres;
1836
1837                 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1838                         v->xres_virtual, v->yres_virtual);
1839         } else if (v->xres_virtual == -1) {
1840                 v->xres_virtual = (rinfo->video_ram * den /
1841                                 (nom * v->yres_virtual * 2)) & ~15;
1842         } else if (v->yres_virtual == -1) {
1843                 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1844                 v->yres_virtual = rinfo->video_ram * den /
1845                         (nom * v->xres_virtual *2);
1846         } else {
1847                 if (v->xres_virtual * nom / den * v->yres_virtual >
1848                         rinfo->video_ram) {
1849                         return -EINVAL;
1850                 }
1851         }
1852
1853         if (v->xres_virtual * nom / den >= 8192) {
1854                 v->xres_virtual = 8192 * den / nom - 16;
1855         }
1856
1857         if (v->xres_virtual < v->xres)
1858                 return -EINVAL;
1859
1860         if (v->yres_virtual < v->yres)
1861                 return -EINVAL;
1862
1863         return 0;
1864 }
1865
1866
1867
1868 /*
1869  * fb ops
1870  */
1871
1872 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
1873                              struct fb_info *info)
1874 {
1875         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1876         struct display *disp;
1877
1878         disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
1879
1880         memset (fix, 0, sizeof (struct fb_fix_screeninfo));
1881         strcpy (fix->id, rinfo->name);
1882
1883         fix->smem_start = rinfo->fb_base_phys;
1884         fix->smem_len = rinfo->video_ram;
1885
1886         fix->type = disp->type;
1887         fix->type_aux = disp->type_aux;
1888         fix->visual = disp->visual;
1889
1890         fix->xpanstep = 8;
1891         fix->ypanstep = 1;
1892         fix->ywrapstep = 0;
1893
1894         fix->line_length = disp->line_length;
1895
1896         fix->mmio_start = rinfo->mmio_base_phys;
1897         fix->mmio_len = RADEON_REGSIZE;
1898         if (noaccel)
1899                 fix->accel = FB_ACCEL_NONE;
1900         else
1901                 fix->accel = FB_ACCEL_ATI_RADEON;
1902
1903         return 0;
1904 }
1905
1906
1907
1908 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
1909                              struct fb_info *info)
1910 {
1911         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1912
1913         *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
1914
1915         return 0;
1916 }
1917
1918
1919
1920 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
1921                              struct fb_info *info)
1922 {
1923         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1924         struct display *disp;
1925         struct fb_var_screeninfo v;
1926         int nom, den, accel;
1927         unsigned chgvar = 0;
1928
1929         disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
1930
1931         accel = var->accel_flags & FB_ACCELF_TEXT;
1932
1933         if (con >= 0) {
1934                 chgvar = ((disp->var.xres != var->xres) ||
1935                           (disp->var.yres != var->yres) ||
1936                           (disp->var.xres_virtual != var->xres_virtual) ||
1937                           (disp->var.yres_virtual != var->yres_virtual) ||
1938                           (disp->var.bits_per_pixel != var->bits_per_pixel) ||
1939                           memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
1940                           memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
1941                           memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
1942         }
1943
1944         memcpy (&v, var, sizeof (v));
1945
1946         switch (v.bits_per_pixel) {
1947                 case 0 ... 8:
1948                         v.bits_per_pixel = 8;
1949                         break;
1950                 case 9 ... 16:
1951                         v.bits_per_pixel = 16;
1952                         break;
1953                 case 17 ... 24:
1954                         v.bits_per_pixel = 24;
1955                         break;
1956                 case 25 ... 32:
1957                         v.bits_per_pixel = 32;
1958                         break;
1959                 default:
1960                         return -EINVAL;
1961         }
1962
1963         switch (var_to_depth(&v)) {
1964 #ifdef FBCON_HAS_CFB8
1965                 case 8:
1966                         nom = den = 1;
1967                         disp->line_length = v.xres_virtual;
1968                         disp->visual = FB_VISUAL_PSEUDOCOLOR;
1969                         v.red.offset = v.green.offset = v.blue.offset = 0;
1970                         v.red.length = v.green.length = v.blue.length = 8;
1971                         v.transp.offset = v.transp.length = 0;
1972                         break;
1973 #endif
1974
1975 #ifdef FBCON_HAS_CFB16
1976                 case 15:
1977                         nom = 2;
1978                         den = 1;
1979                         disp->line_length = v.xres_virtual * 2;
1980                         disp->visual = FB_VISUAL_DIRECTCOLOR;
1981                         v.red.offset = 10;
1982                         v.green.offset = 5;
1983                         v.red.offset = 0;
1984                         v.red.length = v.green.length = v.blue.length = 5;
1985                         v.transp.offset = v.transp.length = 0;
1986                         break;
1987                 case 16:
1988                         nom = 2;
1989                         den = 1;
1990                         disp->line_length = v.xres_virtual * 2;
1991                         disp->visual = FB_VISUAL_DIRECTCOLOR;
1992                         v.red.offset = 11;
1993                         v.green.offset = 5;
1994                         v.blue.offset = 0;
1995                         v.red.length = 5;
1996                         v.green.length = 6;
1997                         v.blue.length = 5;
1998                         v.transp.offset = v.transp.length = 0;
1999                         break;
2000 #endif
2001
2002 #ifdef FBCON_HAS_CFB24
2003                 case 24:
2004                         nom = 4;
2005                         den = 1;
2006                         disp->line_length = v.xres_virtual * 3;
2007                         disp->visual = FB_VISUAL_DIRECTCOLOR;
2008                         v.red.offset = 16;
2009                         v.green.offset = 8;
2010                         v.blue.offset = 0;
2011                         v.red.length = v.blue.length = v.green.length = 8;
2012                         v.transp.offset = v.transp.length = 0;
2013                         break;
2014 #endif
2015 #ifdef FBCON_HAS_CFB32
2016                 case 32:
2017                         nom = 4;
2018                         den = 1;
2019                         disp->line_length = v.xres_virtual * 4;
2020                         disp->visual = FB_VISUAL_DIRECTCOLOR;
2021                         v.red.offset = 16;
2022                         v.green.offset = 8;
2023                         v.blue.offset = 0;
2024                         v.red.length = v.blue.length = v.green.length = 8;
2025                         v.transp.offset = 24;
2026                         v.transp.length = 8;
2027                         break;
2028 #endif
2029                 default:
2030                         printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
2031                                 var->xres, var->yres, var->bits_per_pixel);
2032                         return -EINVAL;
2033         }
2034
2035         if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
2036                 return -EINVAL;
2037
2038         if (v.xoffset < 0)
2039                 v.xoffset = 0;
2040         if (v.yoffset < 0)
2041                 v.yoffset = 0;
2042
2043         if (v.xoffset > v.xres_virtual - v.xres)
2044                 v.xoffset = v.xres_virtual - v.xres - 1;
2045
2046         if (v.yoffset > v.yres_virtual - v.yres)
2047                 v.yoffset = v.yres_virtual - v.yres - 1;
2048
2049         v.red.msb_right = v.green.msb_right = v.blue.msb_right =
2050                           v.transp.offset = v.transp.length =
2051                           v.transp.msb_right = 0;
2052
2053         switch (v.activate & FB_ACTIVATE_MASK) {
2054                 case FB_ACTIVATE_TEST:
2055                         return 0;
2056                 case FB_ACTIVATE_NXTOPEN:
2057                 case FB_ACTIVATE_NOW:
2058                         break;
2059                 default:
2060                         return -EINVAL;
2061         }
2062
2063         memcpy (&disp->var, &v, sizeof (v));
2064
2065         if (chgvar) {
2066                 radeon_set_dispsw(rinfo, disp);
2067
2068                 if (noaccel)
2069                         disp->scrollmode = SCROLL_YREDRAW;
2070                 else
2071                         disp->scrollmode = 0;
2072
2073                 if (info && info->changevar)
2074                         info->changevar(con);
2075         }
2076
2077         radeon_load_video_mode (rinfo, &v);
2078
2079         do_install_cmap(con, info);
2080
2081         return 0;
2082 }
2083
2084
2085
2086 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
2087                               struct fb_info *info)
2088 {
2089         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2090         struct display *disp;
2091
2092         disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
2093
2094         if (con == rinfo->currcon) {
2095                 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
2096                 return rc;
2097         } else if (disp->cmap.len)
2098                 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
2099         else
2100                 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
2101                               cmap, kspc ? 0 : 2);
2102
2103         return 0;
2104 }
2105
2106
2107
2108 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
2109                               struct fb_info *info)
2110 {
2111         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2112         struct display *disp;
2113         unsigned int cmap_len;
2114
2115         disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
2116
2117         cmap_len = radeon_get_cmap_len (&disp->var);
2118         if (disp->cmap.len != cmap_len) {
2119                 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
2120                 if (err)
2121                         return err;
2122         }
2123
2124         if (con == rinfo->currcon) {
2125                 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
2126                 return rc;
2127         } else
2128                 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
2129
2130         return 0;
2131 }
2132
2133
2134
2135 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
2136                                  struct fb_info *info)
2137 {
2138         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2139         u32 offset, xoffset, yoffset;
2140
2141         xoffset = (var->xoffset + 7) & ~7;
2142         yoffset = var->yoffset;
2143
2144         if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
2145                 var->yres_virtual))
2146                 return -EINVAL;
2147
2148         if (rinfo->asleep)
2149                 return 0;
2150         offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
2151
2152         OUTREG(CRTC_OFFSET, offset);
2153
2154         return 0;
2155 }
2156
2157
2158 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
2159                            unsigned long arg, int con, struct fb_info *info)
2160 {
2161         return -EINVAL;
2162 }
2163
2164
2165 static int radeonfb_switch (int con, struct fb_info *info)
2166 {
2167         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2168         struct display *disp;
2169         struct fb_cmap *cmap;
2170         int switchmode = 0;
2171
2172         disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
2173
2174         if (rinfo->currcon >= 0) {
2175                 cmap = &(rinfo->currcon_display->cmap);
2176                 if (cmap->len)
2177                         fb_get_cmap (cmap, 1, radeon_getcolreg, info);
2178         }
2179
2180         switchmode = (con != rinfo->currcon);
2181
2182         rinfo->currcon = con;
2183         rinfo->currcon_display = disp;
2184         disp->var.activate = FB_ACTIVATE_NOW;
2185
2186         if (switchmode) {
2187                 radeonfb_set_var (&disp->var, con, info);
2188                 radeon_set_dispsw (rinfo, disp);
2189                 do_install_cmap(con, info);
2190         }
2191
2192         /* XXX absurd hack for X to restore console */
2193         {
2194                 OUTREGP(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl,
2195                         CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2196                 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
2197         }
2198
2199         return 0;
2200 }
2201
2202
2203
2204 static int radeonfb_updatevar (int con, struct fb_info *info)
2205 {
2206         int rc;
2207
2208         rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
2209                                                          con, info);
2210
2211         return rc;
2212 }
2213
2214 static void radeonfb_blank (int blank, struct fb_info *info)
2215 {
2216         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2217         u32 val = INREG(CRTC_EXT_CNTL);
2218         u32 val2 = INREG(LVDS_GEN_CNTL);
2219
2220         if (rinfo->asleep)
2221                 return;
2222
2223 #ifdef CONFIG_PMAC_BACKLIGHT
2224         if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
2225                 set_backlight_enable(!blank);
2226                 return;
2227         }
2228 #endif
2229
2230         /* reset it */
2231         val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
2232                  CRTC_VSYNC_DIS);
2233         val2 &= ~(LVDS_DISPLAY_DIS);
2234
2235         switch (blank) {
2236                 case VESA_NO_BLANKING:
2237                         break;
2238                 case VESA_VSYNC_SUSPEND:
2239                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
2240                         break;
2241                 case VESA_HSYNC_SUSPEND:
2242                         val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
2243                         break;
2244                 case VESA_POWERDOWN:
2245                         val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
2246                                 CRTC_HSYNC_DIS);
2247                         val2 |= (LVDS_DISPLAY_DIS);
2248                         break;
2249         }
2250
2251         switch (rinfo->dviDisp_type) {
2252                 case MT_LCD:
2253                         OUTREG(LVDS_GEN_CNTL, val2);
2254                         break;
2255                 case MT_CRT:
2256                 default:
2257                         OUTREG(CRTC_EXT_CNTL, val);
2258                         break;
2259         }
2260 }
2261
2262
2263 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
2264 {
2265         int rc = 256;            /* reasonable default */
2266
2267         switch (var_to_depth(var)) {
2268                 case 15:
2269                         rc = 32;
2270                         break;
2271                 case 16:
2272                         rc = 64;
2273                         break;
2274         }
2275
2276         return rc;
2277 }
2278
2279
2280
2281 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
2282                              unsigned *blue, unsigned *transp,
2283                              struct fb_info *info)
2284 {
2285         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2286
2287         if (regno > 255)
2288                 return 1;
2289
2290         *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
2291         *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
2292         *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
2293         *transp = 0;
2294
2295         return 0;
2296 }
2297
2298
2299
2300 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
2301                              unsigned blue, unsigned transp, struct fb_info *info)
2302 {
2303         struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2304         u32 pindex, vclk_cntl;
2305
2306         if (regno > 255)
2307                 return 1;
2308
2309         red >>= 8;
2310         green >>= 8;
2311         blue >>= 8;
2312         rinfo->palette[regno].red = red;
2313         rinfo->palette[regno].green = green;
2314         rinfo->palette[regno].blue = blue;
2315
2316         /* default */
2317         pindex = regno;
2318
2319         if (!rinfo->asleep) {
2320                 vclk_cntl = INPLL(VCLK_ECP_CNTL);
2321                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
2322
2323                 if (rinfo->bpp == 16) {
2324                         pindex = regno * 8;
2325
2326                         if (rinfo->depth == 16 && regno > 63)
2327                                 return 1;
2328                         if (rinfo->depth == 15 && regno > 31)
2329                                 return 1;
2330
2331                         /* For 565, the green component is mixed one order below */
2332                         if (rinfo->depth == 16) {
2333                                 OUTREG(PALETTE_INDEX, pindex>>1);
2334                                 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
2335                                         (green << 8) | (rinfo->palette[regno>>1].blue));
2336                                 green = rinfo->palette[regno<<1].green;
2337                         }
2338                 }
2339
2340                 if (rinfo->depth != 16 || regno < 32) {
2341                         OUTREG(PALETTE_INDEX, pindex);
2342                         OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
2343                 }
2344
2345                 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
2346         }
2347         if (regno < 16) {
2348                 switch (rinfo->depth) {
2349 #ifdef FBCON_HAS_CFB16
2350                         case 15:
2351                                 rinfo->con_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
2352                                                                   regno;
2353                                 break;
2354                         case 16:
2355                                 rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
2356                                                                   regno;
2357                                 break;
2358 #endif
2359 #ifdef FBCON_HAS_CFB24
2360                         case 24:
2361                                 rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
2362                                 break;
2363 #endif
2364 #ifdef FBCON_HAS_CFB32
2365                         case 32: {
2366                                 u32 i;
2367
2368                                 i = (regno << 8) | regno;
2369                                 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
2370                                 break;
2371                         }
2372 #endif
2373                 }
2374         }
2375         return 0;
2376 }
2377
2378
2379
2380 static void radeon_save_state (struct radeonfb_info *rinfo,
2381                                struct radeon_regs *save)
2382 {
2383         /* CRTC regs */
2384         save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2385         save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2386         save->dac_cntl = INREG(DAC_CNTL);
2387         save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
2388         save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
2389         save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
2390         save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
2391         save->crtc_pitch = INREG(CRTC_PITCH);
2392 #if defined(__BIG_ENDIAN)
2393         save->surface_cntl = INREG(SURFACE_CNTL);
2394 #endif
2395
2396         /* FP regs */
2397         save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
2398         save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
2399         save->fp_gen_cntl = INREG(FP_GEN_CNTL);
2400         save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
2401         save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
2402         save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
2403         save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
2404         save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2405         save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
2406         save->tmds_crc = INREG(TMDS_CRC);
2407         save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
2408         save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
2409 }
2410
2411
2412
2413 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
2414                                     struct fb_var_screeninfo *mode)
2415 {
2416         struct radeon_regs newmode;
2417         int hTotal, vTotal, hSyncStart, hSyncEnd,
2418             hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
2419         u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
2420         u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
2421         u32 dotClock = 1000000000 / mode->pixclock,
2422             sync, h_sync_pol, v_sync_pol;
2423         int freq = dotClock / 10;  /* x 100 */
2424         int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
2425         int useable_precision, roff, ron;
2426         int min_bits, format = 0;
2427         int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
2428         int primary_mon = PRIMARY_MONITOR(rinfo);
2429         int depth = var_to_depth(mode);
2430
2431         rinfo->xres = mode->xres;
2432         rinfo->yres = mode->yres;
2433         rinfo->pixclock = mode->pixclock;
2434
2435         hSyncStart = mode->xres + mode->right_margin;
2436         hSyncEnd = hSyncStart + mode->hsync_len;
2437         hTotal = hSyncEnd + mode->left_margin;
2438
2439         vSyncStart = mode->yres + mode->lower_margin;
2440         vSyncEnd = vSyncStart + mode->vsync_len;
2441         vTotal = vSyncEnd + mode->upper_margin;
2442
2443         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2444                 if (rinfo->panel_xres < mode->xres)
2445                         rinfo->xres = mode->xres = rinfo->panel_xres;
2446                 if (rinfo->panel_yres < mode->yres)
2447                         rinfo->yres = mode->yres = rinfo->panel_yres;
2448
2449                 hTotal = mode->xres + rinfo->hblank;
2450                 hSyncStart = mode->xres + rinfo->hOver_plus;
2451                 hSyncEnd = hSyncStart + rinfo->hSync_width;
2452
2453                 vTotal = mode->yres + rinfo->vblank;
2454                 vSyncStart = mode->yres + rinfo->vOver_plus;
2455                 vSyncEnd = vSyncStart + rinfo->vSync_width;
2456         }
2457
2458         sync = mode->sync;
2459         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
2460         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
2461
2462         RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
2463                 hSyncStart, hSyncEnd, hTotal);
2464         RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
2465                 vSyncStart, vSyncEnd, vTotal);
2466
2467         hsync_wid = (hSyncEnd - hSyncStart) / 8;
2468         vsync_wid = vSyncEnd - vSyncStart;
2469         if (hsync_wid == 0)
2470                 hsync_wid = 1;
2471         else if (hsync_wid > 0x3f)      /* max */
2472                 hsync_wid = 0x3f;
2473
2474         if (vsync_wid == 0)
2475                 vsync_wid = 1;
2476         else if (vsync_wid > 0x1f)      /* max */
2477                 vsync_wid = 0x1f;
2478
2479         hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
2480         vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
2481
2482         cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
2483
2484         format = radeon_get_dstbpp(depth);
2485         bytpp = mode->bits_per_pixel >> 3;
2486
2487         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
2488                 hsync_fudge = hsync_fudge_fp[format-1];
2489         else
2490                 hsync_fudge = hsync_adj_tab[format-1];
2491
2492         hsync_start = hSyncStart - 8 + hsync_fudge;
2493
2494         newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
2495                                 (format << 8);
2496
2497         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2498                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
2499                 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
2500                                            CRTC_INTERLACE_EN);
2501         } else {
2502                 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
2503                                         CRTC_CRT_ON;
2504         }
2505
2506         newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
2507                            DAC_8BIT_EN;
2508
2509         newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
2510                                      (((mode->xres / 8) - 1) << 16));
2511
2512         newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
2513                                         (hsync_wid << 16) | (h_sync_pol << 23));
2514
2515         newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
2516                                     ((mode->yres - 1) << 16);
2517
2518         newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
2519                                          (vsync_wid << 16) | (v_sync_pol  << 23));
2520
2521         newmode.crtc_pitch = (mode->xres >> 3);
2522         newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
2523
2524 #if defined(__BIG_ENDIAN)
2525         newmode.surface_cntl = SURF_TRANSLATION_DIS;
2526         switch (mode->bits_per_pixel) {
2527                 case 16:
2528                         newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
2529                         break;
2530                 case 24:
2531                 case 32:
2532                         newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
2533                         break;
2534         }
2535 #endif
2536
2537         rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
2538                         & ~(0x3f)) / 64;
2539
2540         RTRACE("h_total_disp = 0x%x\t   hsync_strt_wid = 0x%x\n",
2541                 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
2542         RTRACE("v_total_disp = 0x%x\t   vsync_strt_wid = 0x%x\n",
2543                 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
2544
2545         newmode.xres = mode->xres;
2546         newmode.yres = mode->yres;
2547
2548         rinfo->bpp = mode->bits_per_pixel;
2549         rinfo->depth = depth;
2550
2551         rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
2552         rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
2553
2554         if (freq > rinfo->pll.ppll_max)
2555                 freq = rinfo->pll.ppll_max;
2556         if (freq*12 < rinfo->pll.ppll_min)
2557                 freq = rinfo->pll.ppll_min / 12;
2558
2559         {
2560                 struct {
2561                         int divider;
2562                         int bitvalue;
2563                 } *post_div,
2564                   post_divs[] = {
2565                         { 1,  0 },
2566                         { 2,  1 },
2567                         { 4,  2 },
2568                         { 8,  3 },
2569                         { 3,  4 },
2570                         { 16, 5 },
2571                         { 6,  6 },
2572                         { 12, 7 },
2573                         { 0,  0 },
2574                 };
2575
2576                 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
2577                         rinfo->pll_output_freq = post_div->divider * freq;
2578                         if (rinfo->pll_output_freq >= rinfo->pll.ppll_min  &&
2579                             rinfo->pll_output_freq <= rinfo->pll.ppll_max)
2580                                 break;
2581                 }
2582
2583                 rinfo->post_div = post_div->divider;
2584                 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
2585                                           rinfo->pll.ref_clk);
2586                 newmode.ppll_ref_div = rinfo->pll.ref_div;
2587                 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
2588         }
2589         newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
2590
2591
2592         RTRACE("post div = 0x%x\n", rinfo->post_div);
2593         RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
2594         RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
2595
2596         /* DDA */
2597         vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
2598                               rinfo->pll.ref_div * rinfo->post_div);
2599         xclk_freq = rinfo->pll.xclk;
2600
2601         xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
2602
2603         min_bits = min_bits_req(xclk_per_trans);
2604         useable_precision = min_bits + 1;
2605
2606         xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
2607                                            vclk_freq * mode->bits_per_pixel);
2608
2609         ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
2610                2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
2611                xclk_per_trans) << (11 - useable_precision);
2612         roff = xclk_per_trans_precise * (32 - 4);
2613
2614         RTRACE("ron = %d, roff = %d\n", ron, roff);
2615         RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
2616
2617         if ((ron + rinfo->ram.rloop) >= roff) {
2618                 printk("radeonfb: error ron out of range\n");
2619                 return;
2620         }
2621
2622         newmode.dda_config = (xclk_per_trans_precise |
2623                               (useable_precision << 16) |
2624                               (rinfo->ram.rloop << 20));
2625         newmode.dda_on_off = (ron << 16) | roff;
2626
2627         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2628                 unsigned int hRatio, vRatio;
2629
2630                 /* We force the pixel clock to be always enabled. Allowing it
2631                  * to be power managed during blanking would save power, but has
2632                  * nasty interactions with the 2D engine & sleep code that haven't
2633                  * been solved yet. --BenH
2634                  */
2635                 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
2636
2637                 if (mode->xres > rinfo->panel_xres)
2638                         mode->xres = rinfo->panel_xres;
2639                 if (mode->yres > rinfo->panel_yres)
2640                         mode->yres = rinfo->panel_yres;
2641
2642                 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2643                                            << HORZ_PANEL_SHIFT);
2644                 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2645                                            << VERT_PANEL_SHIFT);
2646
2647                 if (mode->xres != rinfo->panel_xres) {
2648                         hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2649                                            rinfo->panel_xres);
2650                         newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2651                                                    (newmode.fp_horz_stretch &
2652                                                     (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2653                                                      HORZ_AUTO_RATIO_INC)));
2654                         newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2655                                                     HORZ_STRETCH_ENABLE);
2656                 }
2657                 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2658
2659                 if (mode->yres != rinfo->panel_yres) {
2660                                 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2661                                                    rinfo->panel_yres);
2662                                 newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2663                                                            (newmode.fp_vert_stretch &
2664                                                            (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2665                                 newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2666                                                             VERT_STRETCH_ENABLE);
2667                 }
2668                 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2669
2670                 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2671                                        ~(FP_SEL_CRTC2 |
2672                                          FP_RMX_HVSYNC_CONTROL_EN |
2673                                          FP_DFP_SYNC_SEL |
2674                                          FP_CRT_SYNC_SEL |
2675                                          FP_CRTC_LOCK_8DOT |
2676                                          FP_USE_SHADOW_EN |
2677                                          FP_CRTC_USE_SHADOW_VEND |
2678                                          FP_CRT_SYNC_ALT));
2679
2680                 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2681                                         FP_CRTC_DONT_SHADOW_HEND);
2682
2683                 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2684                 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2685                 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2686                 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2687
2688                 if (primary_mon == MT_LCD) {
2689                         newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2690                         newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2691                 } else {
2692                         /* DFP */
2693                         newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2694                         newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2695                                                          ICHCSEL) & ~(TMDS_PLLRST);
2696                         newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2697                 }
2698
2699                 newmode.fp_crtc_h_total_disp = newmode.crtc_h_total_disp;
2700                 newmode.fp_crtc_v_total_disp = newmode.crtc_v_total_disp;
2701                 newmode.fp_h_sync_strt_wid = newmode.crtc_h_sync_strt_wid;
2702                 newmode.fp_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
2703         }
2704
2705         /* do it! */
2706         if (!rinfo->asleep)
2707                 radeon_write_mode (rinfo, &newmode);
2708
2709 #if defined(CONFIG_BOOTX_TEXT)
2710         btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2711                              rinfo->depth, rinfo->pitch*64);
2712 #endif
2713
2714         return;
2715 }
2716
2717
2718 static void radeon_write_mode (struct radeonfb_info *rinfo,
2719                                struct radeon_regs *mode)
2720 {
2721         int i;
2722         int primary_mon = PRIMARY_MONITOR(rinfo);
2723
2724         /* blank screen */
2725         OUTREGP(CRTC_EXT_CNTL, CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS,
2726                 ~(CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS));
2727
2728         for (i=0; i<9; i++)
2729                 OUTREG(common_regs[i].reg, common_regs[i].val);
2730
2731         OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2732         OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2733                 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2734         OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2735         OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2736         OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2737         OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2738         OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2739         OUTREG(CRTC_OFFSET, 0);
2740         OUTREG(CRTC_OFFSET_CNTL, 0);
2741         OUTREG(CRTC_PITCH, mode->crtc_pitch);
2742
2743 #if defined(__BIG_ENDIAN)
2744         OUTREG(SURFACE_CNTL, mode->surface_cntl);
2745 #endif
2746
2747         while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2748                PPLL_DIV_SEL_MASK) {
2749                 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2750         }
2751
2752         OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2753
2754         while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2755                (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2756                 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2757         }
2758
2759         while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2760                (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2761                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2762         }
2763
2764         while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2765                (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2766                 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2767         }
2768
2769         OUTPLL(HTOTAL_CNTL, 0);
2770
2771         OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2772
2773         OUTREG(DDA_CONFIG, mode->dda_config);
2774         OUTREG(DDA_ON_OFF, mode->dda_on_off);
2775
2776         if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2777                 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2778                 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2779                 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2780                 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2781                 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2782                 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2783                 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2784                 OUTREG(TMDS_CRC, mode->tmds_crc);
2785                 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2786
2787                 if (primary_mon == MT_LCD) {
2788                         unsigned int tmp = INREG(LVDS_GEN_CNTL);
2789
2790                         mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2791                         mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2792
2793                         if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2794                             (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2795                                 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2796                         } else {
2797                                 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2798                                         udelay(1000);
2799                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2800                                 } else {
2801                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2802                                                LVDS_BLON);
2803                                         udelay(1000);
2804                                         OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2805                                 }
2806                         }
2807                 }
2808         }
2809
2810         /* unblank screen */
2811         OUTREG8(CRTC_EXT_CNTL + 1, 0);
2812
2813         OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2814
2815         return;
2816 }
2817
2818
2819 #ifdef CONFIG_PMAC_BACKLIGHT
2820
2821 static int backlight_conv[] = {
2822         0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2823         0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2824 };
2825
2826 #define BACKLIGHT_LVDS_OFF
2827 #undef BACKLIGHT_DAC_OFF
2828
2829 /* We turn off the LCD completely instead of just dimming the backlight.
2830  * This provides some greater power saving and the display is useless
2831  * without backlight anyway.
2832  */
2833
2834 static int radeon_set_backlight_enable(int on, int level, void *data)
2835 {
2836         struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2837         unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2838
2839         lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2840         if (on && (level > BACKLIGHT_OFF)) {
2841                 lvds_gen_cntl |= LVDS_DIGON;
2842                 if (!lvds_gen_cntl & LVDS_ON) {
2843                         lvds_gen_cntl &= ~LVDS_BLON;
2844                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2845                         (void)INREG(LVDS_GEN_CNTL);
2846                         mdelay(10);
2847                         lvds_gen_cntl |= LVDS_BLON;
2848                         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2849                 }
2850                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2851                 lvds_gen_cntl |= (backlight_conv[level] <<
2852                                   LVDS_BL_MOD_LEVEL_SHIFT);
2853                 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2854                 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2855         } else {
2856                 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2857                 lvds_gen_cntl |= (backlight_conv[0] <<
2858                                   LVDS_BL_MOD_LEVEL_SHIFT);
2859                 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2860                 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2861                 udelay(10);
2862                 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2863         }
2864
2865         OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2866         rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2867         rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2868
2869         return 0;
2870 }
2871
2872 static int radeon_set_backlight_level(int level, void *data)
2873 {
2874         return radeon_set_backlight_enable(1, level, data);
2875 }
2876 #endif /* CONFIG_PMAC_BACKLIGHT */
2877
2878
2879 #ifdef CONFIG_PMAC_PBOOK
2880 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2881 {
2882         u16 pwr_cmd;
2883
2884         if (!rinfo->pm_reg)
2885                 return;
2886
2887         /* Set the chip into appropriate suspend mode (we use D2,
2888          * D3 would require a compete re-initialization of the chip,
2889          * including PCI config registers, clocks, AGP conf, ...)
2890          */
2891         if (suspend) {
2892                 /* Save some registers */
2893                 rinfo->save_regs[0] = INREG(CRTC_GEN_CNTL);
2894                 rinfo->save_regs[1] = INREG(CRTC2_GEN_CNTL);
2895
2896                 /* Disable CRTCs */
2897                 OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2898                 OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2899                 (void)INREG(CRTC2_GEN_CNTL);
2900                 mdelay(10);
2901
2902                 /* Reset the MDLL */
2903                 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2904                 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2905
2906                 /* Switch PCI power managment to D2. */
2907                 for (;;) {
2908                         pci_read_config_word(
2909                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2910                                 &pwr_cmd);
2911                         if (pwr_cmd & 2)
2912                                 break;
2913                         pci_write_config_word(
2914                                 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2915                                 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2916                         mdelay(500);
2917                 }
2918         } else {
2919                 /* Switch back PCI powermanagment to D0 */
2920                 mdelay(200);
2921                 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2922                 mdelay(500);
2923
2924                 /* Restore the MDLL */
2925                 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2926
2927                 /* Restore some registers */
2928                 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[1]);
2929                 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[0]);
2930         }
2931 }
2932
2933 /*
2934  * Save the contents of the framebuffer when we go to sleep,
2935  * and restore it when we wake up again.
2936  */
2937
2938 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2939 {
2940         struct radeonfb_info *rinfo;
2941
2942         for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2943                 struct fb_fix_screeninfo fix;
2944                 int nb;
2945                 struct display *disp;
2946
2947                 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2948
2949                 switch (rinfo->chipset) {
2950                         case PCI_DEVICE_ID_RADEON_LW:
2951                         case PCI_DEVICE_ID_RADEON_LY:
2952                         case PCI_DEVICE_ID_RADEON_LZ:
2953                         case PCI_DEVICE_ID_RADEON_PM:
2954                                 break;
2955                         default:
2956                                 return PBOOK_SLEEP_REFUSE;
2957                 }
2958
2959                 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2960                 nb = fb_display[fg_console].var.yres * fix.line_length;
2961
2962                 switch (when) {
2963                         case PBOOK_SLEEP_NOW:
2964                                 acquire_console_sem();
2965                                 disp->dispsw = &fbcon_dummy;
2966
2967                                 if (!noaccel) {
2968                                         /* Make sure engine is reset */
2969                                         radeon_engine_reset();
2970                                         radeon_engine_idle();
2971                                 }
2972
2973                                 /* Blank display and LCD */
2974                                 radeonfb_blank(VESA_POWERDOWN+1,
2975                                                (struct fb_info *)rinfo);
2976
2977                                 /* Sleep */
2978                                 rinfo->asleep = 1;
2979                                 radeon_set_suspend(rinfo, 1);
2980                                 release_console_sem();
2981
2982                                 break;
2983                         case PBOOK_WAKE:
2984                                 acquire_console_sem();
2985                                 /* Wakeup */
2986                                 radeon_set_suspend(rinfo, 0);
2987
2988                                 if (!noaccel)
2989                                         radeon_engine_init(rinfo);
2990                                 rinfo->asleep = 0;
2991                                 radeon_set_dispsw(rinfo, disp);
2992                                 radeon_load_video_mode(rinfo, &disp->var);
2993                                 do_install_cmap(rinfo->currcon,
2994                                                 (struct fb_info *)rinfo);
2995
2996                                 radeonfb_blank(0, (struct fb_info *)rinfo);
2997                                 release_console_sem();
2998                                 break;
2999                 }
3000         }
3001
3002         return PBOOK_SLEEP_OK;
3003 }
3004
3005 #endif /* CONFIG_PMAC_PBOOK */
3006
3007 /*
3008  * text console acceleration
3009  */
3010
3011
3012 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
3013                                int dsty, int dstx, int height, int width)
3014 {
3015         struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
3016         u32 dp_cntl = DST_LAST_PEL;
3017
3018         srcx *= fontwidth(p);
3019         srcy *= fontheight(p);
3020         dstx *= fontwidth(p);
3021         dsty *= fontheight(p);
3022         width *= fontwidth(p);
3023         height *= fontheight(p);
3024
3025         if (srcy < dsty) {
3026                 srcy += height - 1;
3027                 dsty += height - 1;
3028         } else
3029                 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
3030
3031         if (srcx < dstx) {
3032                 srcx += width - 1;
3033                 dstx += width - 1;
3034         } else
3035                 dp_cntl |= DST_X_LEFT_TO_RIGHT;
3036
3037         radeon_fifo_wait(6);
3038         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
3039                                     GMC_BRUSH_NONE |
3040                                     GMC_SRC_DATATYPE_COLOR |
3041                                     ROP3_S |
3042                                     DP_SRC_SOURCE_MEMORY));
3043         OUTREG(DP_WRITE_MSK, 0xffffffff);
3044         OUTREG(DP_CNTL, dp_cntl);
3045         OUTREG(SRC_Y_X, (srcy << 16) | srcx);
3046         OUTREG(DST_Y_X, (dsty << 16) | dstx);
3047         OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
3048 }
3049
3050
3051
3052 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
3053                                int srcy, int srcx, int height, int width)
3054 {
3055         struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
3056         u32 clr;
3057
3058         clr = attr_bgcol_ec(p, conp);
3059         clr |= (clr << 8);
3060         clr |= (clr << 16);
3061
3062         srcx *= fontwidth(p);
3063         srcy *= fontheight(p);
3064         width *= fontwidth(p);
3065         height *= fontheight(p);
3066
3067         radeon_fifo_wait(6);
3068         OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
3069                                     GMC_BRUSH_SOLID_COLOR |
3070                                     GMC_SRC_DATATYPE_COLOR |
3071                                     ROP3_P));
3072         OUTREG(DP_BRUSH_FRGD_CLR, clr);
3073         OUTREG(DP_WRITE_MSK, 0xffffffff);
3074         OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
3075         OUTREG(DST_Y_X, (srcy << 16) | srcx);
3076         OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
3077 }
3078
3079
3080
3081 #ifdef FBCON_HAS_CFB8
3082 static struct display_switch fbcon_radeon8 = {
3083         setup:                  fbcon_cfb8_setup,
3084         bmove:                  fbcon_radeon_bmove,
3085         clear:                  fbcon_radeon_clear,
3086         putc:                   fbcon_cfb8_putc,
3087         putcs:                  fbcon_cfb8_putcs,
3088         revc:                   fbcon_cfb8_revc,
3089         clear_margins:          fbcon_cfb8_clear_margins,
3090         fontwidthmask:          FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
3091 };
3092 #endif