2 * drivers/video/radeonfb.c
3 * framebuffer driver for ATI Radeon chipset video boards
5 * Copyright 2000 Ani Joshi <ajoshi@unixbox.com>
9 * 2000-08-03 initial version 0.0.1
10 * 2000-09-10 more bug fixes, public release 0.0.5
11 * 2001-02-19 mode bug fixes, 0.0.7
12 * 2001-07-05 fixed scrolling issues, engine initialization,
13 * and minor mode tweaking, 0.0.9
14 * 2001-09-07 Radeon VE support, Nick Kurshev
15 * blanking, pan_display, and cmap fixes, 0.1.0
16 * 2001-10-10 Radeon 7500 and 8500 support, and experimental
17 * flat panel support, 0.1.1
18 * 2001-11-17 Radeon M6 (ppc) support, Daniel Berlin, 0.1.2
19 * 2001-11-18 DFP fixes, Kevin Hendricks, 0.1.3
20 * 2001-11-29 more cmap, backlight fixes, Benjamin Herrenschmidt
21 * 2002-01-18 DFP panel detection via BIOS, Michael Clark, 0.1.4
23 * Special thanks to ATI DevRel team for their hardware donations.
28 #define RADEON_VERSION "0.1.4"
31 #include <linux/config.h>
32 #include <linux/module.h>
33 #include <linux/kernel.h>
34 #include <linux/errno.h>
35 #include <linux/string.h>
37 #include <linux/tty.h>
38 #include <linux/slab.h>
39 #include <linux/delay.h>
41 #include <linux/console.h>
42 #include <linux/selection.h>
43 #include <linux/ioport.h>
44 #include <linux/init.h>
45 #include <linux/pci.h>
46 #include <linux/vmalloc.h>
49 #if defined(__powerpc__)
51 #include <asm/pci-bridge.h>
52 #include <video/macmodes.h>
55 #include <linux/nvram.h>
58 #ifdef CONFIG_PMAC_BACKLIGHT
59 #include <asm/backlight.h>
62 #ifdef CONFIG_BOOTX_TEXT
63 #include <asm/btext.h>
67 #include <linux/adb.h>
68 #include <linux/pmu.h>
71 #endif /* __powerpc__ */
73 #include <video/fbcon.h>
74 #include <video/fbcon-cfb8.h>
75 #include <video/fbcon-cfb16.h>
76 #include <video/fbcon-cfb24.h>
77 #include <video/fbcon-cfb32.h>
87 #define RTRACE if(0) printk
93 RADEON_QD, /* Radeon R100 */
94 RADEON_QE, /* Radeon R100 */
95 RADEON_QF, /* Radeon R100 */
96 RADEON_QG, /* Radeon R100 */
97 RADEON_QY, /* Radeon RV100 (VE) */
98 RADEON_QZ, /* Radeon RV100 (VE) */
99 RADEON_QL, /* Radeon R200 (8500) */
100 RADEON_QW, /* Radeon RV200 (7500) */
101 RADEON_LW, /* Radeon Mobility M7 */
102 RADEON_LY, /* Radeon Mobility M6 */
103 RADEON_LZ, /* Radeon Mobility M6 */
104 RADEON_PM /* Radeon Mobility P/M */
114 MT_CTV, /* composite TV */
115 MT_STV /* S-Video out */
119 static struct pci_device_id radeonfb_pci_table[] __devinitdata = {
120 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QD, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QD},
121 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QE, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QE},
122 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QF, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QF},
123 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QG, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QG},
124 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QY},
125 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QZ},
126 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QL, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QL},
127 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_QW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_QW},
128 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LW, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LW},
129 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LY, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LY},
130 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_LZ, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_LZ},
131 { PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_RADEON_PM, PCI_ANY_ID, PCI_ANY_ID, 0, 0, RADEON_PM},
134 MODULE_DEVICE_TABLE(pci, radeonfb_pci_table);
143 /* these common regs are cleared before mode setting so they do not
144 * interfere with anything
146 reg_val common_regs[] = {
148 { OVR_WID_LEFT_RIGHT, 0 },
149 { OVR_WID_TOP_BOTTOM, 0 },
150 { OV0_SCALE_CNTL, 0 },
155 { CAP0_TRIG_CNTL, 0 },
158 #define COMMON_REGS_SIZE = (sizeof(common_regs)/sizeof(common_regs[0]))
163 u8 accelerator_entry;
165 u16 VGA_table_offset;
166 u16 POST_table_offset;
172 u16 PCLK_ref_divider;
176 u16 MCLK_ref_divider;
180 u16 XCLK_ref_divider;
183 } __attribute__ ((packed)) PLL_BLOCK;
210 u32 crtc_h_total_disp;
211 u32 crtc_h_sync_strt_wid;
212 u32 crtc_v_total_disp;
213 u32 crtc_v_sync_strt_wid;
232 /* Flat panel regs */
233 u32 fp_crtc_h_total_disp;
234 u32 fp_crtc_v_total_disp;
236 u32 fp_h_sync_strt_wid;
239 u32 fp_v_sync_strt_wid;
244 u32 tmds_transmitter_cntl;
246 #if defined(__BIG_ENDIAN)
252 struct radeonfb_info {
255 struct radeon_regs state;
256 struct radeon_regs init_state;
264 unsigned long mmio_base;
265 unsigned long fb_base;
267 struct pci_dev *pdev;
270 unsigned char *bios_seg;
274 struct display *currcon_display;
276 struct { u8 red, green, blue, pad; } palette[256];
281 int pitch, bpp, depth;
282 int xres, yres, pixclock;
291 int panel_xres, panel_yres;
293 int hOver_plus, hSync_width, hblank;
294 int vOver_plus, vSync_width, vblank;
295 int hAct_high, vAct_high, interlaced;
298 u32 dp_gui_master_cntl;
301 int pll_output_freq, post_div, fb_div;
305 u32 hack_crtc_ext_cntl;
306 u32 hack_crtc_v_sync_strt_wid;
308 #if defined(FBCON_HAS_CFB16) || defined(FBCON_HAS_CFB32)
310 #if defined(FBCON_HAS_CFB16)
313 #if defined(FBCON_HAS_CFB24)
316 #if defined(FBCON_HAS_CFB32)
322 #ifdef CONFIG_PMAC_PBOOK
324 u32 save_regs[16]; /* Add more later */
328 struct radeonfb_info *next;
332 static struct fb_var_screeninfo radeonfb_default_var = {
333 640, 480, 640, 480, 0, 0, 8, 0,
334 {0, 6, 0}, {0, 6, 0}, {0, 6, 0}, {0, 0, 0},
335 0, 0, -1, -1, 0, 39721, 40, 24, 32, 11, 96, 2,
336 0, FB_VMODE_NONINTERLACED
344 #define INREG8(addr) readb((rinfo->mmio_base)+addr)
345 #define OUTREG8(addr,val) writeb(val, (rinfo->mmio_base)+addr)
346 #define INREG(addr) readl((rinfo->mmio_base)+addr)
347 #define OUTREG(addr,val) writel(val, (rinfo->mmio_base)+addr)
349 #define OUTPLL(addr,val) OUTREG8(CLOCK_CNTL_INDEX, (addr & 0x0000001f) | 0x00000080); \
350 OUTREG(CLOCK_CNTL_DATA, val)
351 #define OUTPLLP(addr,val,mask) \
353 unsigned int _tmp = INPLL(addr); \
356 OUTPLL(addr, _tmp); \
359 #define OUTREGP(addr,val,mask) \
361 unsigned int _tmp = INREG(addr); \
364 OUTREG(addr, _tmp); \
368 static __inline__ u32 _INPLL(struct radeonfb_info *rinfo, unsigned long addr)
370 OUTREG8(CLOCK_CNTL_INDEX, addr & 0x0000001f);
371 return (INREG(CLOCK_CNTL_DATA));
374 #define INPLL(addr) _INPLL(rinfo, addr)
376 #define PRIMARY_MONITOR(rinfo) ((rinfo->dviDisp_type != MT_NONE) && \
377 (rinfo->dviDisp_type != MT_STV) && \
378 (rinfo->dviDisp_type != MT_CTV) ? \
379 rinfo->dviDisp_type : rinfo->crtDisp_type)
381 static char *GET_MON_NAME(int type)
414 static __inline__ void radeon_engine_flush (struct radeonfb_info *rinfo)
419 OUTREGP(RB2D_DSTCACHE_CTLSTAT, RB2D_DC_FLUSH_ALL,
422 for (i=0; i < 2000000; i++) {
423 if (!(INREG(RB2D_DSTCACHE_CTLSTAT) & RB2D_DC_BUSY))
429 static __inline__ void _radeon_fifo_wait (struct radeonfb_info *rinfo, int entries)
433 for (i=0; i<2000000; i++)
434 if ((INREG(RBBM_STATUS) & 0x7f) >= entries)
439 static __inline__ void _radeon_engine_idle (struct radeonfb_info *rinfo)
443 /* ensure FIFO is empty before waiting for idle */
444 _radeon_fifo_wait (rinfo, 64);
446 for (i=0; i<2000000; i++) {
447 if (((INREG(RBBM_STATUS) & GUI_ACTIVE)) == 0) {
448 radeon_engine_flush (rinfo);
455 #define radeon_engine_idle() _radeon_engine_idle(rinfo)
456 #define radeon_fifo_wait(entries) _radeon_fifo_wait(rinfo,entries)
464 static __inline__ u32 radeon_get_dstbpp(u16 depth)
481 static inline int var_to_depth(const struct fb_var_screeninfo *var)
483 if (var->bits_per_pixel != 16)
484 return var->bits_per_pixel;
485 return (var->green.length == 6) ? 16 : 15;
489 static void _radeon_engine_reset(struct radeonfb_info *rinfo)
491 u32 clock_cntl_index, mclk_cntl, rbbm_soft_reset;
493 radeon_engine_flush (rinfo);
495 clock_cntl_index = INREG(CLOCK_CNTL_INDEX);
496 mclk_cntl = INPLL(MCLK_CNTL);
498 OUTPLL(MCLK_CNTL, (mclk_cntl |
505 rbbm_soft_reset = INREG(RBBM_SOFT_RESET);
507 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset |
516 INREG(RBBM_SOFT_RESET);
517 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset & (u32)
526 INREG(RBBM_SOFT_RESET);
528 OUTPLL(MCLK_CNTL, mclk_cntl);
529 OUTREG(CLOCK_CNTL_INDEX, clock_cntl_index);
530 OUTREG(RBBM_SOFT_RESET, rbbm_soft_reset);
535 #define radeon_engine_reset() _radeon_engine_reset(rinfo)
538 static __inline__ u8 radeon_get_post_div_bitval(int post_div)
562 static __inline__ int round_div(int num, int den)
564 return (num + (den / 2)) / den;
569 static __inline__ int min_bits_req(int val)
585 static __inline__ int _max(int val1, int val2)
599 static char fontname[40] __initdata;
600 static char *mode_option __initdata;
601 static char noaccel __initdata = 0;
602 static int panel_yres __initdata = 0;
603 static char force_dfp __initdata = 0;
604 static struct radeonfb_info *board_list = NULL;
606 #ifdef FBCON_HAS_CFB8
607 static struct display_switch fbcon_radeon8;
615 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
616 struct fb_info *info);
617 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
618 struct fb_info *info);
619 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
620 struct fb_info *info);
621 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
622 struct fb_info *info);
623 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
624 struct fb_info *info);
625 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
626 struct fb_info *info);
627 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
628 unsigned long arg, int con, struct fb_info *info);
629 static int radeonfb_switch (int con, struct fb_info *info);
630 static int radeonfb_updatevar (int con, struct fb_info *info);
631 static void radeonfb_blank (int blank, struct fb_info *info);
632 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var);
633 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
634 unsigned *blue, unsigned *transp,
635 struct fb_info *info);
636 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
637 unsigned blue, unsigned transp, struct fb_info *info);
638 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp);
639 static void radeon_save_state (struct radeonfb_info *rinfo,
640 struct radeon_regs *save);
641 static void radeon_engine_init (struct radeonfb_info *rinfo);
642 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
643 struct fb_var_screeninfo *mode);
644 static void radeon_write_mode (struct radeonfb_info *rinfo,
645 struct radeon_regs *mode);
646 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo);
647 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo);
648 static int radeon_init_disp_var (struct radeonfb_info *rinfo);
649 static int radeonfb_pci_register (struct pci_dev *pdev,
650 const struct pci_device_id *ent);
651 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev);
652 static char *radeon_find_rom(struct radeonfb_info *rinfo);
653 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg);
654 static void radeon_get_moninfo (struct radeonfb_info *rinfo);
655 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo);
656 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo);
657 static void radeon_get_EDID(struct radeonfb_info *rinfo);
658 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo);
659 static void radeon_update_default_var(struct radeonfb_info *rinfo);
662 #ifdef CONFIG_ALL_PPC
663 static int radeon_read_OF (struct radeonfb_info *rinfo);
664 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo);
665 extern struct device_node *pci_device_to_OF_node(struct pci_dev *dev);
667 #ifdef CONFIG_PMAC_PBOOK
668 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when);
669 static struct pmu_sleep_notifier radeon_sleep_notifier = {
670 radeon_sleep_notify, SLEEP_LEVEL_VIDEO,
672 static int radeon_set_backlight_enable(int on, int level, void *data);
673 static int radeon_set_backlight_level(int level, void *data);
674 static struct backlight_controller radeon_backlight_controller = {
675 radeon_set_backlight_enable,
676 radeon_set_backlight_level
678 #endif /* CONFIG_PMAC_PBOOK */
680 #endif /* CONFIG_ALL_PPC */
682 static struct fb_ops radeon_fb_ops = {
683 fb_get_fix: radeonfb_get_fix,
684 fb_get_var: radeonfb_get_var,
685 fb_set_var: radeonfb_set_var,
686 fb_get_cmap: radeonfb_get_cmap,
687 fb_set_cmap: radeonfb_set_cmap,
688 fb_pan_display: radeonfb_pan_display,
689 fb_ioctl: radeonfb_ioctl,
693 static struct pci_driver radeonfb_driver = {
695 id_table: radeonfb_pci_table,
696 probe: radeonfb_pci_register,
697 remove: __devexit_p(radeonfb_pci_unregister),
701 int __init radeonfb_init (void)
703 return pci_module_init (&radeonfb_driver);
707 void __exit radeonfb_exit (void)
709 pci_unregister_driver (&radeonfb_driver);
713 int __init radeonfb_setup (char *options)
717 if (!options || !*options)
720 while ((this_opt = strsep (&options, ",")) != NULL) {
723 if (!strncmp (this_opt, "font:", 5)) {
728 for (i=0; i<sizeof (fontname) - 1; i++)
729 if (!*p || *p == ' ' || *p == ',')
731 memcpy(fontname, this_opt + 5, i);
732 } else if (!strncmp(this_opt, "noaccel", 7)) {
734 } else if (!strncmp(this_opt, "dfp", 3)) {
736 } else if (!strncmp(this_opt, "panel_yres:", 11)) {
737 panel_yres = simple_strtoul((this_opt+11), NULL, 0);
739 mode_option = this_opt;
746 module_init(radeonfb_init);
747 module_exit(radeonfb_exit);
751 MODULE_AUTHOR("Ani Joshi");
752 MODULE_DESCRIPTION("framebuffer driver for ATI Radeon chipset");
753 MODULE_LICENSE("GPL");
755 static int radeonfb_pci_register (struct pci_dev *pdev,
756 const struct pci_device_id *ent)
758 struct radeonfb_info *rinfo;
762 RTRACE("radeonfb_pci_register BEGIN\n");
764 rinfo = kmalloc (sizeof (struct radeonfb_info), GFP_KERNEL);
766 printk ("radeonfb: could not allocate memory\n");
770 memset (rinfo, 0, sizeof (struct radeonfb_info));
778 if ((err = pci_enable_device(pdev))) {
779 printk("radeonfb: cannot enable device\n");
786 rinfo->fb_base_phys = pci_resource_start (pdev, 0);
787 rinfo->mmio_base_phys = pci_resource_start (pdev, 2);
789 /* request the mem regions */
790 if (!request_mem_region (rinfo->fb_base_phys,
791 pci_resource_len(pdev, 0), "radeonfb")) {
792 printk ("radeonfb: cannot reserve FB region\n");
797 if (!request_mem_region (rinfo->mmio_base_phys,
798 pci_resource_len(pdev, 2), "radeonfb")) {
799 printk ("radeonfb: cannot reserve MMIO region\n");
800 release_mem_region (rinfo->fb_base_phys,
801 pci_resource_len(pdev, 0));
806 /* map the regions */
807 rinfo->mmio_base = (unsigned long)ioremap (rinfo->mmio_base_phys,
809 if (!rinfo->mmio_base) {
810 printk ("radeonfb: cannot map MMIO\n");
811 release_mem_region (rinfo->mmio_base_phys,
812 pci_resource_len(pdev, 2));
813 release_mem_region (rinfo->fb_base_phys,
814 pci_resource_len(pdev, 0));
819 rinfo->chipset = pdev->device;
822 switch (pdev->device) {
823 case PCI_DEVICE_ID_RADEON_QD:
824 strcpy(rinfo->name, "Radeon QD ");
826 case PCI_DEVICE_ID_RADEON_QE:
827 strcpy(rinfo->name, "Radeon QE ");
829 case PCI_DEVICE_ID_RADEON_QF:
830 strcpy(rinfo->name, "Radeon QF ");
832 case PCI_DEVICE_ID_RADEON_QG:
833 strcpy(rinfo->name, "Radeon QG ");
835 case PCI_DEVICE_ID_RADEON_QY:
836 strcpy(rinfo->name, "Radeon QY VE ");
839 case PCI_DEVICE_ID_RADEON_QZ:
840 strcpy(rinfo->name, "Radeon QZ VE ");
843 case PCI_DEVICE_ID_RADEON_QW:
844 strcpy(rinfo->name, "Radeon 7500 QW ");
847 case PCI_DEVICE_ID_RADEON_QL:
848 strcpy(rinfo->name, "Radeon 8500 QL ");
851 case PCI_DEVICE_ID_RADEON_LW:
852 strcpy(rinfo->name, "Radeon M7 LW ");
855 case PCI_DEVICE_ID_RADEON_LY:
856 strcpy(rinfo->name, "Radeon M6 LY ");
859 case PCI_DEVICE_ID_RADEON_LZ:
860 strcpy(rinfo->name, "Radeon M6 LZ ");
863 case PCI_DEVICE_ID_RADEON_PM:
864 strcpy(rinfo->name, "Radeon P/M ");
870 /* framebuffer size */
871 tmp = INREG(CONFIG_MEMSIZE);
873 /* mem size is bits [28:0], mask off the rest */
874 rinfo->video_ram = tmp & CONFIG_MEMSIZE_MASK;
877 tmp = INREG(MEM_SDRAM_MODE_REG);
878 switch ((MEM_CFG_TYPE & tmp) >> 30) {
880 /* SDR SGRAM (2:1) */
881 strcpy(rinfo->ram_type, "SDR SGRAM");
888 rinfo->ram.loop_latency = 16;
889 rinfo->ram.rloop = 16;
894 strcpy(rinfo->ram_type, "DDR SGRAM");
902 rinfo->ram.loop_latency = 16;
903 rinfo->ram.rloop = 16;
907 /* 64-bit SDR SGRAM */
908 strcpy(rinfo->ram_type, "SDR SGRAM 64");
916 rinfo->ram.loop_latency = 17;
917 rinfo->ram.rloop = 17;
922 rinfo->bios_seg = radeon_find_rom(rinfo);
923 radeon_get_pllinfo(rinfo, rinfo->bios_seg);
925 RTRACE("radeonfb: probed %s %dk videoram\n", (rinfo->ram_type), (rinfo->video_ram/1024));
927 #if !defined(__powerpc__)
928 radeon_get_moninfo(rinfo);
930 switch (pdev->device) {
931 case PCI_DEVICE_ID_RADEON_LW:
932 case PCI_DEVICE_ID_RADEON_LY:
933 case PCI_DEVICE_ID_RADEON_LZ:
934 case PCI_DEVICE_ID_RADEON_PM:
935 rinfo->dviDisp_type = MT_LCD;
938 radeon_get_moninfo(rinfo);
943 radeon_get_EDID(rinfo);
945 if ((rinfo->dviDisp_type == MT_DFP) || (rinfo->dviDisp_type == MT_LCD) ||
946 (rinfo->crtDisp_type == MT_DFP)) {
947 if (!radeon_get_dfpinfo(rinfo)) {
948 iounmap ((void*)rinfo->mmio_base);
949 release_mem_region (rinfo->mmio_base_phys,
950 pci_resource_len(pdev, 2));
951 release_mem_region (rinfo->fb_base_phys,
952 pci_resource_len(pdev, 0));
958 rinfo->fb_base = (unsigned long) ioremap (rinfo->fb_base_phys,
960 if (!rinfo->fb_base) {
961 printk ("radeonfb: cannot map FB\n");
962 iounmap ((void*)rinfo->mmio_base);
963 release_mem_region (rinfo->mmio_base_phys,
964 pci_resource_len(pdev, 2));
965 release_mem_region (rinfo->fb_base_phys,
966 pci_resource_len(pdev, 0));
971 /* XXX turn off accel for now, blts aren't working right */
974 /* currcon not yet configured, will be set by first switch */
977 /* One PPC, OF based cards setup the internal memory
978 * mapping in strange ways. We change it so that the
979 * framebuffer is mapped at 0 and given half of the card's
980 * address space (2Gb). AGP is mapped high (0xe0000000) and
981 * can use up to 512Mb. Once DRI is fully implemented, we
982 * will have to setup the PCI remapper to remap the agp_special_page
983 * memory page somewhere between those regions so that the card
984 * use a normal PCI bus master cycle to access the ring read ptr.
987 #ifdef CONFIG_ALL_PPC
989 OUTREG(CRTC2_GEN_CNTL,
990 (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
991 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) | CRTC_DISPLAY_DIS);
992 OUTREG(MC_FB_LOCATION, 0x7fff0000);
993 OUTREG(MC_AGP_LOCATION, 0xffffe000);
994 OUTREG(DISPLAY_BASE_ADDR, 0x00000000);
996 OUTREG(CRTC2_DISPLAY_BASE_ADDR, 0x00000000);
997 OUTREG(SRC_OFFSET, 0x00000000);
998 OUTREG(DST_OFFSET, 0x00000000);
1000 OUTREG(CRTC_EXT_CNTL, INREG(CRTC_EXT_CNTL) & ~CRTC_DISPLAY_DIS);
1001 #endif /* CONFIG_ALL_PPC */
1003 /* set all the vital stuff */
1004 radeon_set_fbinfo (rinfo);
1006 /* save current mode regs before we switch into the new one
1007 * so we can restore this upon __exit
1009 radeon_save_state (rinfo, &rinfo->init_state);
1012 for (i=0; i<16; i++) {
1014 rinfo->palette[i].red = default_red[j];
1015 rinfo->palette[i].green = default_grn[j];
1016 rinfo->palette[i].blue = default_blu[j];
1019 pci_set_drvdata(pdev, rinfo);
1020 rinfo->next = board_list;
1023 if (register_framebuffer ((struct fb_info *) rinfo) < 0) {
1024 printk ("radeonfb: could not register framebuffer\n");
1025 iounmap ((void*)rinfo->fb_base);
1026 iounmap ((void*)rinfo->mmio_base);
1027 release_mem_region (rinfo->mmio_base_phys,
1028 pci_resource_len(pdev, 2));
1029 release_mem_region (rinfo->fb_base_phys,
1030 pci_resource_len(pdev, 0));
1037 /* initialize the engine */
1038 radeon_engine_init (rinfo);
1041 #ifdef CONFIG_PMAC_BACKLIGHT
1042 if (rinfo->dviDisp_type == MT_LCD)
1043 register_backlight_controller(&radeon_backlight_controller,
1047 #ifdef CONFIG_PMAC_PBOOK
1048 if (rinfo->dviDisp_type == MT_LCD) {
1049 rinfo->pm_reg = pci_find_capability(pdev, PCI_CAP_ID_PM);
1050 if (rinfo->pm_reg) {
1051 printk("radeonfb: pm reg @%x, clk_pwrmgt: %x, pll_pwrmgt: %x"
1052 ", mdll_cko: %x\n", rinfo->pm_reg, INPLL(CLK_PWRMGT_CNTL),
1053 INPLL(PLL_PWRMGT_CNTL), INPLL(MDLL_CKO));
1054 /* Fixup some PLL reg values for proper power management */
1055 OUTPLL(PLL_PWRMGT_CNTL, 0xc01f);
1056 OUTPLL(MDLL_CKO, 0x043c);
1057 pmu_register_sleep_notifier(&radeon_sleep_notifier);
1062 printk ("radeonfb: ATI %s %s %d MB\n", rinfo->name, rinfo->ram_type,
1063 (rinfo->video_ram/(1024*1024)));
1065 if (rinfo->hasCRTC2) {
1066 printk("radeonfb: DVI port %s monitor connected\n",
1067 GET_MON_NAME(rinfo->dviDisp_type));
1068 printk("radeonfb: CRT port %s monitor connected\n",
1069 GET_MON_NAME(rinfo->crtDisp_type));
1071 printk("radeonfb: CRT port %s monitor connected\n",
1072 GET_MON_NAME(rinfo->crtDisp_type));
1075 RTRACE("radeonfb_pci_register END\n");
1082 static void __devexit radeonfb_pci_unregister (struct pci_dev *pdev)
1084 struct radeonfb_info *rinfo = pci_get_drvdata(pdev);
1089 /* restore original state */
1090 radeon_write_mode (rinfo, &rinfo->init_state);
1092 unregister_framebuffer ((struct fb_info *) rinfo);
1094 iounmap ((void*)rinfo->mmio_base);
1095 iounmap ((void*)rinfo->fb_base);
1097 release_mem_region (rinfo->mmio_base_phys,
1098 pci_resource_len(pdev, 2));
1099 release_mem_region (rinfo->fb_base_phys,
1100 pci_resource_len(pdev, 0));
1107 static char *radeon_find_rom(struct radeonfb_info *rinfo)
1109 #if defined(__i386__)
1115 char aty_rom_sig[] = "761295520";
1116 char *radeon_sig[] = {
1121 for(segstart=0x000c0000; segstart<0x000f0000; segstart+=0x00001000) {
1125 rom_base = (char *)ioremap(segstart, 0x1000);
1127 if ((*rom_base == 0x55) && (((*(rom_base + 1)) & 0xff) == 0xaa))
1138 for (i = 0; (i < 128 - strlen(aty_rom_sig)) && (stage != 3); i++) {
1139 if (aty_rom_sig[0] == *rom)
1140 if (strncmp(aty_rom_sig, rom,
1141 strlen(aty_rom_sig)) == 0)
1151 for (i = 0; (i < 512) && (stage != 4); i++) {
1152 for(j = 0;j < sizeof(radeon_sig)/sizeof(char *);j++) {
1153 if (radeon_sig[j][0] == *rom)
1154 if (strncmp(radeon_sig[j], rom,
1155 strlen(radeon_sig[j])) == 0) {
1176 static void radeon_get_pllinfo(struct radeonfb_info *rinfo, char *bios_seg)
1180 u16 bios_header_offset, pll_info_offset;
1184 bios_header = bios_seg + 0x48L;
1185 header_ptr = bios_header;
1187 bios_header_offset = readw(header_ptr);
1188 bios_header = bios_seg + bios_header_offset;
1189 bios_header += 0x30;
1191 header_ptr = bios_header;
1192 pll_info_offset = readw(header_ptr);
1193 header_ptr = bios_seg + pll_info_offset;
1195 memcpy_fromio(&pll, header_ptr, 50);
1197 rinfo->pll.xclk = (u32)pll.XCLK;
1198 rinfo->pll.ref_clk = (u32)pll.PCLK_ref_freq;
1199 rinfo->pll.ref_div = (u32)pll.PCLK_ref_divider;
1200 rinfo->pll.ppll_min = pll.PCLK_min_freq;
1201 rinfo->pll.ppll_max = pll.PCLK_max_freq;
1203 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from BIOS\n",
1204 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
1206 #ifdef CONFIG_ALL_PPC
1207 if (radeon_read_OF(rinfo)) {
1208 unsigned int tmp, Nx, M, ref_div, xclk;
1210 tmp = INPLL(M_SPLL_REF_FB_DIV);
1211 ref_div = INPLL(PPLL_REF_DIV) & 0x3ff;
1213 Nx = (tmp & 0xff00) >> 8;
1215 xclk = ((((2 * Nx * rinfo->pll.ref_clk) + (M)) /
1218 rinfo->pll.xclk = xclk;
1219 rinfo->pll.ref_div = ref_div;
1220 rinfo->pll.ppll_min = 12000;
1221 rinfo->pll.ppll_max = 35000;
1223 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d from OF\n",
1224 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
1229 /* no BIOS or BIOS not found, use defaults */
1230 switch (rinfo->chipset) {
1231 case PCI_DEVICE_ID_RADEON_QW:
1232 rinfo->pll.ppll_max = 35000;
1233 rinfo->pll.ppll_min = 12000;
1234 rinfo->pll.xclk = 23000;
1235 rinfo->pll.ref_div = 12;
1236 rinfo->pll.ref_clk = 2700;
1238 case PCI_DEVICE_ID_RADEON_QL:
1239 rinfo->pll.ppll_max = 35000;
1240 rinfo->pll.ppll_min = 12000;
1241 rinfo->pll.xclk = 27500;
1242 rinfo->pll.ref_div = 12;
1243 rinfo->pll.ref_clk = 2700;
1245 case PCI_DEVICE_ID_RADEON_QD:
1246 case PCI_DEVICE_ID_RADEON_QE:
1247 case PCI_DEVICE_ID_RADEON_QF:
1248 case PCI_DEVICE_ID_RADEON_QG:
1250 rinfo->pll.ppll_max = 35000;
1251 rinfo->pll.ppll_min = 12000;
1252 rinfo->pll.xclk = 16600;
1253 rinfo->pll.ref_div = 67;
1254 rinfo->pll.ref_clk = 2700;
1258 printk("radeonfb: ref_clk=%d, ref_div=%d, xclk=%d defaults\n",
1259 rinfo->pll.ref_clk, rinfo->pll.ref_div, rinfo->pll.xclk);
1264 static void radeon_get_moninfo (struct radeonfb_info *rinfo)
1269 rinfo->dviDisp_type = MT_DFP;
1273 tmp = INREG(RADEON_BIOS_4_SCRATCH);
1275 if (rinfo->hasCRTC2) {
1276 /* primary DVI port */
1278 rinfo->dviDisp_type = MT_DFP;
1280 rinfo->dviDisp_type = MT_LCD;
1281 else if (tmp & 0x200)
1282 rinfo->dviDisp_type = MT_CRT;
1283 else if (tmp & 0x10)
1284 rinfo->dviDisp_type = MT_CTV;
1285 else if (tmp & 0x20)
1286 rinfo->dviDisp_type = MT_STV;
1288 /* secondary CRT port */
1290 rinfo->crtDisp_type = MT_CRT;
1291 else if (tmp & 0x800)
1292 rinfo->crtDisp_type = MT_DFP;
1293 else if (tmp & 0x400)
1294 rinfo->crtDisp_type = MT_LCD;
1295 else if (tmp & 0x1000)
1296 rinfo->crtDisp_type = MT_CTV;
1297 else if (tmp & 0x2000)
1298 rinfo->crtDisp_type = MT_STV;
1300 rinfo->dviDisp_type = MT_NONE;
1302 tmp = INREG(FP_GEN_CNTL);
1304 if (tmp & FP_EN_TMDS)
1305 rinfo->crtDisp_type = MT_DFP;
1307 rinfo->crtDisp_type = MT_CRT;
1313 static void radeon_get_EDID(struct radeonfb_info *rinfo)
1315 #ifdef CONFIG_ALL_PPC
1316 if (!radeon_get_EDID_OF(rinfo))
1317 RTRACE("radeonfb: could not retrieve EDID from OF\n");
1319 /* XXX use other methods later */
1324 #ifdef CONFIG_ALL_PPC
1325 static int radeon_get_EDID_OF(struct radeonfb_info *rinfo)
1327 struct device_node *dp;
1328 unsigned char *pedid = NULL;
1330 dp = pci_device_to_OF_node(rinfo->pdev);
1331 pedid = (unsigned char *) get_property(dp, "DFP,EDID", 0);
1333 pedid = (unsigned char *) get_property(dp, "LCD,EDID", 0);
1335 pedid = (unsigned char *) get_property(dp, "EDID", 0);
1338 rinfo->EDID = pedid;
1343 #endif /* CONFIG_ALL_PPC */
1346 static int radeon_dfp_parse_EDID(struct radeonfb_info *rinfo)
1348 unsigned char *block = rinfo->EDID;
1353 /* jump to the detailed timing block section */
1356 rinfo->clock = (block[0] + (block[1] << 8));
1357 rinfo->panel_xres = (block[2] + ((block[4] & 0xf0) << 4));
1358 rinfo->hblank = (block[3] + ((block[4] & 0x0f) << 8));
1359 rinfo->panel_yres = (block[5] + ((block[7] & 0xf0) << 4));
1360 rinfo->vblank = (block[6] + ((block[7] & 0x0f) << 8));
1361 rinfo->hOver_plus = (block[8] + ((block[11] & 0xc0) << 2));
1362 rinfo->hSync_width = (block[9] + ((block[11] & 0x30) << 4));
1363 rinfo->vOver_plus = ((block[10] >> 4) + ((block[11] & 0x0c) << 2));
1364 rinfo->vSync_width = ((block[10] & 0x0f) + ((block[11] & 0x03) << 4));
1365 rinfo->interlaced = ((block[17] & 0x80) >> 7);
1366 rinfo->synct = ((block[17] & 0x18) >> 3);
1367 rinfo->misc = ((block[17] & 0x06) >> 1);
1368 rinfo->hAct_high = rinfo->vAct_high = 0;
1369 if (rinfo->synct == 3) {
1370 if (rinfo->misc & 2)
1371 rinfo->hAct_high = 1;
1372 if (rinfo->misc & 1)
1373 rinfo->vAct_high = 1;
1376 printk("radeonfb: detected DFP panel size from EDID: %dx%d\n",
1377 rinfo->panel_xres, rinfo->panel_yres);
1379 rinfo->got_dfpinfo = 1;
1385 static void radeon_update_default_var(struct radeonfb_info *rinfo)
1387 struct fb_var_screeninfo *var = &radeonfb_default_var;
1389 var->xres = rinfo->panel_xres;
1390 var->yres = rinfo->panel_yres;
1391 var->xres_virtual = rinfo->panel_xres;
1392 var->yres_virtual = rinfo->panel_yres;
1393 var->xoffset = var->yoffset = 0;
1394 var->bits_per_pixel = 8;
1395 var->pixclock = 100000000 / rinfo->clock;
1396 var->left_margin = (rinfo->hblank - rinfo->hOver_plus - rinfo->hSync_width);
1397 var->right_margin = rinfo->hOver_plus;
1398 var->upper_margin = (rinfo->vblank - rinfo->vOver_plus - rinfo->vSync_width);
1399 var->lower_margin = rinfo->vOver_plus;
1400 var->hsync_len = rinfo->hSync_width;
1401 var->vsync_len = rinfo->vSync_width;
1403 if (rinfo->synct == 3) {
1404 if (rinfo->hAct_high)
1405 var->sync |= FB_SYNC_HOR_HIGH_ACT;
1406 if (rinfo->vAct_high)
1407 var->sync |= FB_SYNC_VERT_HIGH_ACT;
1411 if (rinfo->interlaced)
1412 var->vmode |= FB_VMODE_INTERLACED;
1414 rinfo->use_default_var = 1;
1418 static int radeon_get_dfpinfo_BIOS(struct radeonfb_info *rinfo)
1420 char *fpbiosstart, *tmp, *tmp0;
1424 if (!rinfo->bios_seg)
1427 if (!(fpbiosstart = rinfo->bios_seg + readw(rinfo->bios_seg + 0x48))) {
1428 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1432 if (!(tmp = rinfo->bios_seg + readw(fpbiosstart + 0x40))) {
1433 printk("radeonfb: Failed to detect DFP panel info using BIOS\n");
1438 stmp[i] = readb(tmp+i+1);
1440 printk("radeonfb: panel ID string: %s\n", stmp);
1441 rinfo->panel_xres = readw(tmp + 25);
1442 rinfo->panel_yres = readw(tmp + 27);
1443 printk("radeonfb: detected DFP panel size from BIOS: %dx%d\n",
1444 rinfo->panel_xres, rinfo->panel_yres);
1446 for(i=0; i<20; i++) {
1447 tmp0 = rinfo->bios_seg + readw(tmp+64+i*2);
1450 if ((readw(tmp0) == rinfo->panel_xres) &&
1451 (readw(tmp0+2) == rinfo->panel_yres)) {
1452 rinfo->hblank = (readw(tmp0+17) - readw(tmp0+19)) * 8;
1453 rinfo->hOver_plus = ((readw(tmp0+21) - readw(tmp0+19) -1) * 8) & 0x7fff;
1454 rinfo->hSync_width = readb(tmp0+23) * 8;
1455 rinfo->vblank = readw(tmp0+24) - readw(tmp0+26);
1456 rinfo->vOver_plus = (readw(tmp0+28) & 0x7ff) - readw(tmp0+26);
1457 rinfo->vSync_width = (readw(tmp0+28) & 0xf800) >> 11;
1458 rinfo->clock = readw(tmp0+9);
1460 rinfo->got_dfpinfo = 1;
1470 static int radeon_get_dfpinfo (struct radeonfb_info *rinfo)
1473 unsigned short a, b;
1475 if (radeon_get_dfpinfo_BIOS(rinfo))
1476 radeon_update_default_var(rinfo);
1478 if (radeon_dfp_parse_EDID(rinfo))
1479 radeon_update_default_var(rinfo);
1481 if (!rinfo->got_dfpinfo) {
1483 * it seems all else has failed now and we
1484 * resort to probing registers for our DFP info
1487 rinfo->panel_yres = panel_yres;
1489 tmp = INREG(FP_VERT_STRETCH);
1491 rinfo->panel_yres = (unsigned short)(tmp >> 0x0c) + 1;
1494 switch (rinfo->panel_yres) {
1496 rinfo->panel_xres = 640;
1499 rinfo->panel_xres = 800;
1502 #if defined(__powerpc__)
1503 if (rinfo->dviDisp_type == MT_LCD)
1504 rinfo->panel_xres = 1152;
1507 rinfo->panel_xres = 1024;
1510 rinfo->panel_xres = 1280;
1513 rinfo->panel_xres = 1400;
1516 rinfo->panel_xres = 1600;
1519 printk("radeonfb: Failed to detect DFP panel size\n");
1523 printk("radeonfb: detected DFP panel size from registers: %dx%d\n",
1524 rinfo->panel_xres, rinfo->panel_yres);
1526 tmp = INREG(FP_CRTC_H_TOTAL_DISP);
1527 a = (tmp & FP_CRTC_H_TOTAL_MASK) + 4;
1528 b = (tmp & 0x01ff0000) >> FP_CRTC_H_DISP_SHIFT;
1529 rinfo->hblank = (a - b + 1) * 8;
1531 tmp = INREG(FP_H_SYNC_STRT_WID);
1532 rinfo->hOver_plus = (unsigned short) ((tmp & FP_H_SYNC_STRT_CHAR_MASK) >>
1533 FP_H_SYNC_STRT_CHAR_SHIFT) - b - 1;
1534 rinfo->hOver_plus *= 8;
1535 rinfo->hSync_width = (unsigned short) ((tmp & FP_H_SYNC_WID_MASK) >>
1536 FP_H_SYNC_WID_SHIFT);
1537 rinfo->hSync_width *= 8;
1538 tmp = INREG(FP_CRTC_V_TOTAL_DISP);
1539 a = (tmp & FP_CRTC_V_TOTAL_MASK) + 1;
1540 b = (tmp & FP_CRTC_V_DISP_MASK) >> FP_CRTC_V_DISP_SHIFT;
1541 rinfo->vblank = a - b /* + 24 */ ;
1543 tmp = INREG(FP_V_SYNC_STRT_WID);
1544 rinfo->vOver_plus = (unsigned short) (tmp & FP_V_SYNC_STRT_MASK)
1546 rinfo->vSync_width = (unsigned short) ((tmp & FP_V_SYNC_WID_MASK) >>
1547 FP_V_SYNC_WID_SHIFT);
1556 #ifdef CONFIG_ALL_PPC
1557 static int radeon_read_OF (struct radeonfb_info *rinfo)
1559 struct device_node *dp;
1562 dp = pci_device_to_OF_node(rinfo->pdev);
1564 xtal = (unsigned int *) get_property(dp, "ATY,RefCLK", 0);
1566 rinfo->pll.ref_clk = *xtal / 10;
1576 static void radeon_engine_init (struct radeonfb_info *rinfo)
1580 /* disable 3D engine */
1581 OUTREG(RB3D_CNTL, 0);
1583 radeon_engine_reset ();
1585 radeon_fifo_wait (1);
1586 OUTREG(DSTCACHE_MODE, 0);
1589 rinfo->pitch = ((rinfo->xres * (rinfo->bpp / 8) + 0x3f)) >> 6;
1591 radeon_fifo_wait (1);
1592 temp = INREG(DEFAULT_PITCH_OFFSET);
1593 OUTREG(DEFAULT_PITCH_OFFSET, ((temp & 0xc0000000) |
1594 (rinfo->pitch << 0x16)));
1596 radeon_fifo_wait (1);
1597 OUTREGP(DP_DATATYPE, 0, ~HOST_BIG_ENDIAN_EN);
1599 radeon_fifo_wait (1);
1600 OUTREG(DEFAULT_SC_BOTTOM_RIGHT, (DEFAULT_SC_RIGHT_MAX |
1601 DEFAULT_SC_BOTTOM_MAX));
1603 temp = radeon_get_dstbpp(rinfo->depth);
1604 rinfo->dp_gui_master_cntl = ((temp << 8) | GMC_CLR_CMP_CNTL_DIS);
1605 radeon_fifo_wait (1);
1606 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
1607 GMC_BRUSH_SOLID_COLOR |
1608 GMC_SRC_DATATYPE_COLOR));
1610 radeon_fifo_wait (7);
1612 /* clear line drawing regs */
1613 OUTREG(DST_LINE_START, 0);
1614 OUTREG(DST_LINE_END, 0);
1616 /* set brush color regs */
1617 OUTREG(DP_BRUSH_FRGD_CLR, 0xffffffff);
1618 OUTREG(DP_BRUSH_BKGD_CLR, 0x00000000);
1620 /* set source color regs */
1621 OUTREG(DP_SRC_FRGD_CLR, 0xffffffff);
1622 OUTREG(DP_SRC_BKGD_CLR, 0x00000000);
1624 /* default write mask */
1625 OUTREG(DP_WRITE_MSK, 0xffffffff);
1627 radeon_engine_idle ();
1632 static int __devinit radeon_set_fbinfo (struct radeonfb_info *rinfo)
1634 struct fb_info *info;
1636 info = &rinfo->info;
1638 strcpy (info->modename, rinfo->name);
1640 info->flags = FBINFO_FLAG_DEFAULT;
1641 info->fbops = &radeon_fb_ops;
1642 info->display_fg = NULL;
1643 strncpy (info->fontname, fontname, sizeof (info->fontname));
1644 info->fontname[sizeof (info->fontname) - 1] = 0;
1645 info->changevar = NULL;
1646 info->switch_con = radeonfb_switch;
1647 info->updatevar = radeonfb_updatevar;
1648 info->blank = radeonfb_blank;
1650 if (radeon_init_disp (rinfo) < 0)
1658 static int __devinit radeon_init_disp (struct radeonfb_info *rinfo)
1660 struct fb_info *info;
1661 struct display *disp;
1663 info = &rinfo->info;
1664 disp = &rinfo->disp;
1666 disp->var = radeonfb_default_var;
1667 #if defined(__powerpc__)
1668 if (rinfo->dviDisp_type == MT_LCD) {
1669 if (mac_vmode_to_var(VMODE_1152_768_60, CMODE_8, &disp->var))
1670 disp->var = radeonfb_default_var;
1674 rinfo->depth = var_to_depth(&disp->var);
1675 rinfo->bpp = disp->var.bits_per_pixel;
1679 radeon_set_dispsw (rinfo, disp);
1682 disp->scrollmode = SCROLL_YREDRAW;
1684 disp->scrollmode = 0;
1686 rinfo->currcon_display = disp;
1688 if ((radeon_init_disp_var (rinfo)) < 0)
1696 static int radeon_init_disp_var (struct radeonfb_info *rinfo)
1700 fb_find_mode (&rinfo->disp.var, &rinfo->info, mode_option,
1704 #if defined(__powerpc__)
1705 if (rinfo->dviDisp_type == MT_LCD) {
1706 if (mac_vmode_to_var(VMODE_1152_768_60, CMODE_8, &rinfo->disp.var))
1707 rinfo->disp.var = radeonfb_default_var;
1711 if (rinfo->use_default_var)
1712 /* We will use the modified default far */
1713 rinfo->disp.var = radeonfb_default_var;
1716 fb_find_mode (&rinfo->disp.var, &rinfo->info, "640x480-8@60",
1720 rinfo->disp.var.accel_flags &= ~FB_ACCELF_TEXT;
1722 rinfo->disp.var.accel_flags |= FB_ACCELF_TEXT;
1729 static void radeon_set_dispsw (struct radeonfb_info *rinfo, struct display *disp)
1734 accel = disp->var.accel_flags & FB_ACCELF_TEXT;
1736 disp->dispsw_data = NULL;
1738 disp->screen_base = (char*)rinfo->fb_base;
1739 disp->type = FB_TYPE_PACKED_PIXELS;
1742 disp->ywrapstep = 0;
1743 disp->can_soft_blank = 1;
1746 switch (disp->var.bits_per_pixel) {
1747 #ifdef FBCON_HAS_CFB8
1749 disp->dispsw = &fbcon_cfb8;
1750 disp->visual = FB_VISUAL_PSEUDOCOLOR;
1751 disp->line_length = disp->var.xres_virtual;
1754 #ifdef FBCON_HAS_CFB16
1756 disp->dispsw = &fbcon_cfb16;
1757 disp->dispsw_data = &rinfo->con_cmap.cfb16;
1758 disp->visual = FB_VISUAL_DIRECTCOLOR;
1759 disp->line_length = disp->var.xres_virtual * 2;
1762 #ifdef FBCON_HAS_CFB32
1764 disp->dispsw = &fbcon_cfb24;
1765 disp->dispsw_data = &rinfo->con_cmap.cfb24;
1766 disp->visual = FB_VISUAL_DIRECTCOLOR;
1767 disp->line_length = disp->var.xres_virtual * 4;
1770 #ifdef FBCON_HAS_CFB32
1772 disp->dispsw = &fbcon_cfb32;
1773 disp->dispsw_data = &rinfo->con_cmap.cfb32;
1774 disp->visual = FB_VISUAL_DIRECTCOLOR;
1775 disp->line_length = disp->var.xres_virtual * 4;
1779 printk ("radeonfb: setting fbcon_dummy renderer\n");
1780 disp->dispsw = &fbcon_dummy;
1788 static void do_install_cmap(int con, struct fb_info *info)
1790 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1792 if (con != rinfo->currcon)
1795 if (fb_display[con].cmap.len)
1796 fb_set_cmap(&fb_display[con].cmap, 1, radeon_setcolreg, info);
1798 int size = radeon_get_cmap_len(&fb_display[con].var);
1799 fb_set_cmap(fb_default_cmap(size), 1, radeon_setcolreg, info);
1805 static int radeonfb_do_maximize(struct radeonfb_info *rinfo,
1806 struct fb_var_screeninfo *var,
1807 struct fb_var_screeninfo *v,
1822 /* use highest possible virtual resolution */
1823 if (v->xres_virtual == -1 && v->yres_virtual == -1) {
1824 printk("radeonfb: using max available virtual resolution\n");
1825 for (i=0; modes[i].xres != -1; i++) {
1826 if (modes[i].xres * nom / den * modes[i].yres <
1827 rinfo->video_ram / 2)
1830 if (modes[i].xres == -1) {
1831 printk("radeonfb: could not find virtual resolution that fits into video memory!\n");
1834 v->xres_virtual = modes[i].xres;
1835 v->yres_virtual = modes[i].yres;
1837 printk("radeonfb: virtual resolution set to max of %dx%d\n",
1838 v->xres_virtual, v->yres_virtual);
1839 } else if (v->xres_virtual == -1) {
1840 v->xres_virtual = (rinfo->video_ram * den /
1841 (nom * v->yres_virtual * 2)) & ~15;
1842 } else if (v->yres_virtual == -1) {
1843 v->xres_virtual = (v->xres_virtual + 15) & ~15;
1844 v->yres_virtual = rinfo->video_ram * den /
1845 (nom * v->xres_virtual *2);
1847 if (v->xres_virtual * nom / den * v->yres_virtual >
1853 if (v->xres_virtual * nom / den >= 8192) {
1854 v->xres_virtual = 8192 * den / nom - 16;
1857 if (v->xres_virtual < v->xres)
1860 if (v->yres_virtual < v->yres)
1872 static int radeonfb_get_fix (struct fb_fix_screeninfo *fix, int con,
1873 struct fb_info *info)
1875 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1876 struct display *disp;
1878 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
1880 memset (fix, 0, sizeof (struct fb_fix_screeninfo));
1881 strcpy (fix->id, rinfo->name);
1883 fix->smem_start = rinfo->fb_base_phys;
1884 fix->smem_len = rinfo->video_ram;
1886 fix->type = disp->type;
1887 fix->type_aux = disp->type_aux;
1888 fix->visual = disp->visual;
1894 fix->line_length = disp->line_length;
1896 fix->mmio_start = rinfo->mmio_base_phys;
1897 fix->mmio_len = RADEON_REGSIZE;
1899 fix->accel = FB_ACCEL_NONE;
1901 fix->accel = FB_ACCEL_ATI_RADEON;
1908 static int radeonfb_get_var (struct fb_var_screeninfo *var, int con,
1909 struct fb_info *info)
1911 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1913 *var = (con < 0) ? rinfo->disp.var : fb_display[con].var;
1920 static int radeonfb_set_var (struct fb_var_screeninfo *var, int con,
1921 struct fb_info *info)
1923 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
1924 struct display *disp;
1925 struct fb_var_screeninfo v;
1926 int nom, den, accel;
1927 unsigned chgvar = 0;
1929 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
1931 accel = var->accel_flags & FB_ACCELF_TEXT;
1934 chgvar = ((disp->var.xres != var->xres) ||
1935 (disp->var.yres != var->yres) ||
1936 (disp->var.xres_virtual != var->xres_virtual) ||
1937 (disp->var.yres_virtual != var->yres_virtual) ||
1938 (disp->var.bits_per_pixel != var->bits_per_pixel) ||
1939 memcmp (&disp->var.red, &var->red, sizeof (var->red)) ||
1940 memcmp (&disp->var.green, &var->green, sizeof (var->green)) ||
1941 memcmp (&disp->var.blue, &var->blue, sizeof (var->blue)));
1944 memcpy (&v, var, sizeof (v));
1946 switch (v.bits_per_pixel) {
1948 v.bits_per_pixel = 8;
1951 v.bits_per_pixel = 16;
1954 v.bits_per_pixel = 24;
1957 v.bits_per_pixel = 32;
1963 switch (var_to_depth(&v)) {
1964 #ifdef FBCON_HAS_CFB8
1967 disp->line_length = v.xres_virtual;
1968 disp->visual = FB_VISUAL_PSEUDOCOLOR;
1969 v.red.offset = v.green.offset = v.blue.offset = 0;
1970 v.red.length = v.green.length = v.blue.length = 8;
1971 v.transp.offset = v.transp.length = 0;
1975 #ifdef FBCON_HAS_CFB16
1979 disp->line_length = v.xres_virtual * 2;
1980 disp->visual = FB_VISUAL_DIRECTCOLOR;
1984 v.red.length = v.green.length = v.blue.length = 5;
1985 v.transp.offset = v.transp.length = 0;
1990 disp->line_length = v.xres_virtual * 2;
1991 disp->visual = FB_VISUAL_DIRECTCOLOR;
1998 v.transp.offset = v.transp.length = 0;
2002 #ifdef FBCON_HAS_CFB24
2006 disp->line_length = v.xres_virtual * 3;
2007 disp->visual = FB_VISUAL_DIRECTCOLOR;
2011 v.red.length = v.blue.length = v.green.length = 8;
2012 v.transp.offset = v.transp.length = 0;
2015 #ifdef FBCON_HAS_CFB32
2019 disp->line_length = v.xres_virtual * 4;
2020 disp->visual = FB_VISUAL_DIRECTCOLOR;
2024 v.red.length = v.blue.length = v.green.length = 8;
2025 v.transp.offset = 24;
2026 v.transp.length = 8;
2030 printk ("radeonfb: mode %dx%dx%d rejected, color depth invalid\n",
2031 var->xres, var->yres, var->bits_per_pixel);
2035 if (radeonfb_do_maximize(rinfo, var, &v, nom, den) < 0)
2043 if (v.xoffset > v.xres_virtual - v.xres)
2044 v.xoffset = v.xres_virtual - v.xres - 1;
2046 if (v.yoffset > v.yres_virtual - v.yres)
2047 v.yoffset = v.yres_virtual - v.yres - 1;
2049 v.red.msb_right = v.green.msb_right = v.blue.msb_right =
2050 v.transp.offset = v.transp.length =
2051 v.transp.msb_right = 0;
2053 switch (v.activate & FB_ACTIVATE_MASK) {
2054 case FB_ACTIVATE_TEST:
2056 case FB_ACTIVATE_NXTOPEN:
2057 case FB_ACTIVATE_NOW:
2063 memcpy (&disp->var, &v, sizeof (v));
2066 radeon_set_dispsw(rinfo, disp);
2069 disp->scrollmode = SCROLL_YREDRAW;
2071 disp->scrollmode = 0;
2073 if (info && info->changevar)
2074 info->changevar(con);
2077 radeon_load_video_mode (rinfo, &v);
2079 do_install_cmap(con, info);
2086 static int radeonfb_get_cmap (struct fb_cmap *cmap, int kspc, int con,
2087 struct fb_info *info)
2089 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2090 struct display *disp;
2092 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
2094 if (con == rinfo->currcon) {
2095 int rc = fb_get_cmap (cmap, kspc, radeon_getcolreg, info);
2097 } else if (disp->cmap.len)
2098 fb_copy_cmap (&disp->cmap, cmap, kspc ? 0 : 2);
2100 fb_copy_cmap (fb_default_cmap (radeon_get_cmap_len (&disp->var)),
2101 cmap, kspc ? 0 : 2);
2108 static int radeonfb_set_cmap (struct fb_cmap *cmap, int kspc, int con,
2109 struct fb_info *info)
2111 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2112 struct display *disp;
2113 unsigned int cmap_len;
2115 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
2117 cmap_len = radeon_get_cmap_len (&disp->var);
2118 if (disp->cmap.len != cmap_len) {
2119 int err = fb_alloc_cmap (&disp->cmap, cmap_len, 0);
2124 if (con == rinfo->currcon) {
2125 int rc = fb_set_cmap (cmap, kspc, radeon_setcolreg, info);
2128 fb_copy_cmap (cmap, &disp->cmap, kspc ? 0 : 1);
2135 static int radeonfb_pan_display (struct fb_var_screeninfo *var, int con,
2136 struct fb_info *info)
2138 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2139 u32 offset, xoffset, yoffset;
2141 xoffset = (var->xoffset + 7) & ~7;
2142 yoffset = var->yoffset;
2144 if ((xoffset + var->xres > var->xres_virtual) || (yoffset+var->yres >
2150 offset = ((yoffset * var->xres + xoffset) * var->bits_per_pixel) >> 6;
2152 OUTREG(CRTC_OFFSET, offset);
2158 static int radeonfb_ioctl (struct inode *inode, struct file *file, unsigned int cmd,
2159 unsigned long arg, int con, struct fb_info *info)
2165 static int radeonfb_switch (int con, struct fb_info *info)
2167 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2168 struct display *disp;
2169 struct fb_cmap *cmap;
2172 disp = (con < 0) ? rinfo->info.disp : &fb_display[con];
2174 if (rinfo->currcon >= 0) {
2175 cmap = &(rinfo->currcon_display->cmap);
2177 fb_get_cmap (cmap, 1, radeon_getcolreg, info);
2180 switchmode = (con != rinfo->currcon);
2182 rinfo->currcon = con;
2183 rinfo->currcon_display = disp;
2184 disp->var.activate = FB_ACTIVATE_NOW;
2187 radeonfb_set_var (&disp->var, con, info);
2188 radeon_set_dispsw (rinfo, disp);
2189 do_install_cmap(con, info);
2192 /* XXX absurd hack for X to restore console */
2194 OUTREGP(CRTC_EXT_CNTL, rinfo->hack_crtc_ext_cntl,
2195 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2196 OUTREG(CRTC_V_SYNC_STRT_WID, rinfo->hack_crtc_v_sync_strt_wid);
2204 static int radeonfb_updatevar (int con, struct fb_info *info)
2208 rc = (con < 0) ? -EINVAL : radeonfb_pan_display (&fb_display[con].var,
2214 static void radeonfb_blank (int blank, struct fb_info *info)
2216 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2217 u32 val = INREG(CRTC_EXT_CNTL);
2218 u32 val2 = INREG(LVDS_GEN_CNTL);
2223 #ifdef CONFIG_PMAC_BACKLIGHT
2224 if (rinfo->dviDisp_type == MT_LCD && _machine == _MACH_Pmac) {
2225 set_backlight_enable(!blank);
2231 val &= ~(CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS |
2233 val2 &= ~(LVDS_DISPLAY_DIS);
2236 case VESA_NO_BLANKING:
2238 case VESA_VSYNC_SUSPEND:
2239 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS);
2241 case VESA_HSYNC_SUSPEND:
2242 val |= (CRTC_DISPLAY_DIS | CRTC_HSYNC_DIS);
2244 case VESA_POWERDOWN:
2245 val |= (CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS |
2247 val2 |= (LVDS_DISPLAY_DIS);
2251 switch (rinfo->dviDisp_type) {
2253 OUTREG(LVDS_GEN_CNTL, val2);
2257 OUTREG(CRTC_EXT_CNTL, val);
2263 static int radeon_get_cmap_len (const struct fb_var_screeninfo *var)
2265 int rc = 256; /* reasonable default */
2267 switch (var_to_depth(var)) {
2281 static int radeon_getcolreg (unsigned regno, unsigned *red, unsigned *green,
2282 unsigned *blue, unsigned *transp,
2283 struct fb_info *info)
2285 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2290 *red = (rinfo->palette[regno].red<<8) | rinfo->palette[regno].red;
2291 *green = (rinfo->palette[regno].green<<8) | rinfo->palette[regno].green;
2292 *blue = (rinfo->palette[regno].blue<<8) | rinfo->palette[regno].blue;
2300 static int radeon_setcolreg (unsigned regno, unsigned red, unsigned green,
2301 unsigned blue, unsigned transp, struct fb_info *info)
2303 struct radeonfb_info *rinfo = (struct radeonfb_info *) info;
2304 u32 pindex, vclk_cntl;
2312 rinfo->palette[regno].red = red;
2313 rinfo->palette[regno].green = green;
2314 rinfo->palette[regno].blue = blue;
2319 if (!rinfo->asleep) {
2320 vclk_cntl = INPLL(VCLK_ECP_CNTL);
2321 OUTPLL(VCLK_ECP_CNTL, vclk_cntl & ~PIXCLK_DAC_ALWAYS_ONb);
2323 if (rinfo->bpp == 16) {
2326 if (rinfo->depth == 16 && regno > 63)
2328 if (rinfo->depth == 15 && regno > 31)
2331 /* For 565, the green component is mixed one order below */
2332 if (rinfo->depth == 16) {
2333 OUTREG(PALETTE_INDEX, pindex>>1);
2334 OUTREG(PALETTE_DATA, (rinfo->palette[regno>>1].red << 16) |
2335 (green << 8) | (rinfo->palette[regno>>1].blue));
2336 green = rinfo->palette[regno<<1].green;
2340 if (rinfo->depth != 16 || regno < 32) {
2341 OUTREG(PALETTE_INDEX, pindex);
2342 OUTREG(PALETTE_DATA, (red << 16) | (green << 8) | blue);
2345 OUTPLL(VCLK_ECP_CNTL, vclk_cntl);
2348 switch (rinfo->depth) {
2349 #ifdef FBCON_HAS_CFB16
2351 rinfo->con_cmap.cfb16[regno] = (regno << 10) | (regno << 5) |
2355 rinfo->con_cmap.cfb16[regno] = (regno << 11) | (regno << 5) |
2359 #ifdef FBCON_HAS_CFB24
2361 rinfo->con_cmap.cfb24[regno] = (regno << 16) | (regno << 8) | regno;
2364 #ifdef FBCON_HAS_CFB32
2368 i = (regno << 8) | regno;
2369 rinfo->con_cmap.cfb32[regno] = (i << 16) | i;
2380 static void radeon_save_state (struct radeonfb_info *rinfo,
2381 struct radeon_regs *save)
2384 save->crtc_gen_cntl = INREG(CRTC_GEN_CNTL);
2385 save->crtc_ext_cntl = INREG(CRTC_EXT_CNTL);
2386 save->dac_cntl = INREG(DAC_CNTL);
2387 save->crtc_h_total_disp = INREG(CRTC_H_TOTAL_DISP);
2388 save->crtc_h_sync_strt_wid = INREG(CRTC_H_SYNC_STRT_WID);
2389 save->crtc_v_total_disp = INREG(CRTC_V_TOTAL_DISP);
2390 save->crtc_v_sync_strt_wid = INREG(CRTC_V_SYNC_STRT_WID);
2391 save->crtc_pitch = INREG(CRTC_PITCH);
2392 #if defined(__BIG_ENDIAN)
2393 save->surface_cntl = INREG(SURFACE_CNTL);
2397 save->fp_crtc_h_total_disp = INREG(FP_CRTC_H_TOTAL_DISP);
2398 save->fp_crtc_v_total_disp = INREG(FP_CRTC_V_TOTAL_DISP);
2399 save->fp_gen_cntl = INREG(FP_GEN_CNTL);
2400 save->fp_h_sync_strt_wid = INREG(FP_H_SYNC_STRT_WID);
2401 save->fp_horz_stretch = INREG(FP_HORZ_STRETCH);
2402 save->fp_v_sync_strt_wid = INREG(FP_V_SYNC_STRT_WID);
2403 save->fp_vert_stretch = INREG(FP_VERT_STRETCH);
2404 save->lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2405 save->lvds_pll_cntl = INREG(LVDS_PLL_CNTL);
2406 save->tmds_crc = INREG(TMDS_CRC);
2407 save->tmds_transmitter_cntl = INREG(TMDS_TRANSMITTER_CNTL);
2408 save->vclk_ecp_cntl = INPLL(VCLK_ECP_CNTL);
2413 static void radeon_load_video_mode (struct radeonfb_info *rinfo,
2414 struct fb_var_screeninfo *mode)
2416 struct radeon_regs newmode;
2417 int hTotal, vTotal, hSyncStart, hSyncEnd,
2418 hSyncPol, vSyncStart, vSyncEnd, vSyncPol, cSync;
2419 u8 hsync_adj_tab[] = {0, 0x12, 9, 9, 6, 5};
2420 u8 hsync_fudge_fp[] = {2, 2, 0, 0, 5, 5};
2421 u32 dotClock = 1000000000 / mode->pixclock,
2422 sync, h_sync_pol, v_sync_pol;
2423 int freq = dotClock / 10; /* x 100 */
2424 int xclk_freq, vclk_freq, xclk_per_trans, xclk_per_trans_precise;
2425 int useable_precision, roff, ron;
2426 int min_bits, format = 0;
2427 int hsync_start, hsync_fudge, bytpp, hsync_wid, vsync_wid;
2428 int primary_mon = PRIMARY_MONITOR(rinfo);
2429 int depth = var_to_depth(mode);
2431 rinfo->xres = mode->xres;
2432 rinfo->yres = mode->yres;
2433 rinfo->pixclock = mode->pixclock;
2435 hSyncStart = mode->xres + mode->right_margin;
2436 hSyncEnd = hSyncStart + mode->hsync_len;
2437 hTotal = hSyncEnd + mode->left_margin;
2439 vSyncStart = mode->yres + mode->lower_margin;
2440 vSyncEnd = vSyncStart + mode->vsync_len;
2441 vTotal = vSyncEnd + mode->upper_margin;
2443 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2444 if (rinfo->panel_xres < mode->xres)
2445 rinfo->xres = mode->xres = rinfo->panel_xres;
2446 if (rinfo->panel_yres < mode->yres)
2447 rinfo->yres = mode->yres = rinfo->panel_yres;
2449 hTotal = mode->xres + rinfo->hblank;
2450 hSyncStart = mode->xres + rinfo->hOver_plus;
2451 hSyncEnd = hSyncStart + rinfo->hSync_width;
2453 vTotal = mode->yres + rinfo->vblank;
2454 vSyncStart = mode->yres + rinfo->vOver_plus;
2455 vSyncEnd = vSyncStart + rinfo->vSync_width;
2459 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
2460 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
2462 RTRACE("hStart = %d, hEnd = %d, hTotal = %d\n",
2463 hSyncStart, hSyncEnd, hTotal);
2464 RTRACE("vStart = %d, vEnd = %d, vTotal = %d\n",
2465 vSyncStart, vSyncEnd, vTotal);
2467 hsync_wid = (hSyncEnd - hSyncStart) / 8;
2468 vsync_wid = vSyncEnd - vSyncStart;
2471 else if (hsync_wid > 0x3f) /* max */
2476 else if (vsync_wid > 0x1f) /* max */
2479 hSyncPol = mode->sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
2480 vSyncPol = mode->sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
2482 cSync = mode->sync & FB_SYNC_COMP_HIGH_ACT ? (1 << 4) : 0;
2484 format = radeon_get_dstbpp(depth);
2485 bytpp = mode->bits_per_pixel >> 3;
2487 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD))
2488 hsync_fudge = hsync_fudge_fp[format-1];
2490 hsync_fudge = hsync_adj_tab[format-1];
2492 hsync_start = hSyncStart - 8 + hsync_fudge;
2494 newmode.crtc_gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN |
2497 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2498 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN;
2499 newmode.crtc_gen_cntl &= ~(CRTC_DBL_SCAN_EN |
2502 newmode.crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN |
2506 newmode.dac_cntl = /* INREG(DAC_CNTL) | */ DAC_MASK_ALL | DAC_VGA_ADR_EN |
2509 newmode.crtc_h_total_disp = ((((hTotal / 8) - 1) & 0x3ff) |
2510 (((mode->xres / 8) - 1) << 16));
2512 newmode.crtc_h_sync_strt_wid = ((hsync_start & 0x1fff) |
2513 (hsync_wid << 16) | (h_sync_pol << 23));
2515 newmode.crtc_v_total_disp = ((vTotal - 1) & 0xffff) |
2516 ((mode->yres - 1) << 16);
2518 newmode.crtc_v_sync_strt_wid = (((vSyncStart - 1) & 0xfff) |
2519 (vsync_wid << 16) | (v_sync_pol << 23));
2521 newmode.crtc_pitch = (mode->xres >> 3);
2522 newmode.crtc_pitch |= (newmode.crtc_pitch << 16);
2524 #if defined(__BIG_ENDIAN)
2525 newmode.surface_cntl = SURF_TRANSLATION_DIS;
2526 switch (mode->bits_per_pixel) {
2528 newmode.surface_cntl |= NONSURF_AP0_SWP_16BPP;
2532 newmode.surface_cntl |= NONSURF_AP0_SWP_32BPP;
2537 rinfo->pitch = ((mode->xres * ((mode->bits_per_pixel + 1) / 8) + 0x3f)
2540 RTRACE("h_total_disp = 0x%x\t hsync_strt_wid = 0x%x\n",
2541 newmode.crtc_h_total_disp, newmode.crtc_h_sync_strt_wid);
2542 RTRACE("v_total_disp = 0x%x\t vsync_strt_wid = 0x%x\n",
2543 newmode.crtc_v_total_disp, newmode.crtc_v_sync_strt_wid);
2545 newmode.xres = mode->xres;
2546 newmode.yres = mode->yres;
2548 rinfo->bpp = mode->bits_per_pixel;
2549 rinfo->depth = depth;
2551 rinfo->hack_crtc_ext_cntl = newmode.crtc_ext_cntl;
2552 rinfo->hack_crtc_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
2554 if (freq > rinfo->pll.ppll_max)
2555 freq = rinfo->pll.ppll_max;
2556 if (freq*12 < rinfo->pll.ppll_min)
2557 freq = rinfo->pll.ppll_min / 12;
2576 for (post_div = &post_divs[0]; post_div->divider; ++post_div) {
2577 rinfo->pll_output_freq = post_div->divider * freq;
2578 if (rinfo->pll_output_freq >= rinfo->pll.ppll_min &&
2579 rinfo->pll_output_freq <= rinfo->pll.ppll_max)
2583 rinfo->post_div = post_div->divider;
2584 rinfo->fb_div = round_div(rinfo->pll.ref_div*rinfo->pll_output_freq,
2585 rinfo->pll.ref_clk);
2586 newmode.ppll_ref_div = rinfo->pll.ref_div;
2587 newmode.ppll_div_3 = rinfo->fb_div | (post_div->bitvalue << 16);
2589 newmode.vclk_ecp_cntl = rinfo->init_state.vclk_ecp_cntl;
2592 RTRACE("post div = 0x%x\n", rinfo->post_div);
2593 RTRACE("fb_div = 0x%x\n", rinfo->fb_div);
2594 RTRACE("ppll_div_3 = 0x%x\n", newmode.ppll_div_3);
2597 vclk_freq = round_div(rinfo->pll.ref_clk * rinfo->fb_div,
2598 rinfo->pll.ref_div * rinfo->post_div);
2599 xclk_freq = rinfo->pll.xclk;
2601 xclk_per_trans = round_div(xclk_freq * 128, vclk_freq * mode->bits_per_pixel);
2603 min_bits = min_bits_req(xclk_per_trans);
2604 useable_precision = min_bits + 1;
2606 xclk_per_trans_precise = round_div((xclk_freq * 128) << (11 - useable_precision),
2607 vclk_freq * mode->bits_per_pixel);
2609 ron = (4 * rinfo->ram.mb + 3 * _max(rinfo->ram.trcd - 2, 0) +
2610 2 * rinfo->ram.trp + rinfo->ram.twr + rinfo->ram.cl + rinfo->ram.tr2w +
2611 xclk_per_trans) << (11 - useable_precision);
2612 roff = xclk_per_trans_precise * (32 - 4);
2614 RTRACE("ron = %d, roff = %d\n", ron, roff);
2615 RTRACE("vclk_freq = %d, per = %d\n", vclk_freq, xclk_per_trans_precise);
2617 if ((ron + rinfo->ram.rloop) >= roff) {
2618 printk("radeonfb: error ron out of range\n");
2622 newmode.dda_config = (xclk_per_trans_precise |
2623 (useable_precision << 16) |
2624 (rinfo->ram.rloop << 20));
2625 newmode.dda_on_off = (ron << 16) | roff;
2627 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2628 unsigned int hRatio, vRatio;
2630 /* We force the pixel clock to be always enabled. Allowing it
2631 * to be power managed during blanking would save power, but has
2632 * nasty interactions with the 2D engine & sleep code that haven't
2633 * been solved yet. --BenH
2635 newmode.vclk_ecp_cntl &= ~PIXCLK_DAC_ALWAYS_ONb;
2637 if (mode->xres > rinfo->panel_xres)
2638 mode->xres = rinfo->panel_xres;
2639 if (mode->yres > rinfo->panel_yres)
2640 mode->yres = rinfo->panel_yres;
2642 newmode.fp_horz_stretch = (((rinfo->panel_xres / 8) - 1)
2643 << HORZ_PANEL_SHIFT);
2644 newmode.fp_vert_stretch = ((rinfo->panel_yres - 1)
2645 << VERT_PANEL_SHIFT);
2647 if (mode->xres != rinfo->panel_xres) {
2648 hRatio = round_div(mode->xres * HORZ_STRETCH_RATIO_MAX,
2650 newmode.fp_horz_stretch = (((((unsigned long)hRatio) & HORZ_STRETCH_RATIO_MASK)) |
2651 (newmode.fp_horz_stretch &
2652 (HORZ_PANEL_SIZE | HORZ_FP_LOOP_STRETCH |
2653 HORZ_AUTO_RATIO_INC)));
2654 newmode.fp_horz_stretch |= (HORZ_STRETCH_BLEND |
2655 HORZ_STRETCH_ENABLE);
2657 newmode.fp_horz_stretch &= ~HORZ_AUTO_RATIO;
2659 if (mode->yres != rinfo->panel_yres) {
2660 vRatio = round_div(mode->yres * VERT_STRETCH_RATIO_MAX,
2662 newmode.fp_vert_stretch = (((((unsigned long)vRatio) & VERT_STRETCH_RATIO_MASK)) |
2663 (newmode.fp_vert_stretch &
2664 (VERT_PANEL_SIZE | VERT_STRETCH_RESERVED)));
2665 newmode.fp_vert_stretch |= (VERT_STRETCH_BLEND |
2666 VERT_STRETCH_ENABLE);
2668 newmode.fp_vert_stretch &= ~VERT_AUTO_RATIO_EN;
2670 newmode.fp_gen_cntl = (rinfo->init_state.fp_gen_cntl & (u32)
2672 FP_RMX_HVSYNC_CONTROL_EN |
2677 FP_CRTC_USE_SHADOW_VEND |
2680 newmode.fp_gen_cntl |= (FP_CRTC_DONT_SHADOW_VPAR |
2681 FP_CRTC_DONT_SHADOW_HEND);
2683 newmode.lvds_gen_cntl = rinfo->init_state.lvds_gen_cntl;
2684 newmode.lvds_pll_cntl = rinfo->init_state.lvds_pll_cntl;
2685 newmode.tmds_crc = rinfo->init_state.tmds_crc;
2686 newmode.tmds_transmitter_cntl = rinfo->init_state.tmds_transmitter_cntl;
2688 if (primary_mon == MT_LCD) {
2689 newmode.lvds_gen_cntl |= (LVDS_ON | LVDS_BLON);
2690 newmode.fp_gen_cntl &= ~(FP_FPON | FP_TMDS_EN);
2693 newmode.fp_gen_cntl |= (FP_FPON | FP_TMDS_EN);
2694 newmode.tmds_transmitter_cntl = (TMDS_RAN_PAT_RST |
2695 ICHCSEL) & ~(TMDS_PLLRST);
2696 newmode.crtc_ext_cntl &= ~CRTC_CRT_ON;
2699 newmode.fp_crtc_h_total_disp = newmode.crtc_h_total_disp;
2700 newmode.fp_crtc_v_total_disp = newmode.crtc_v_total_disp;
2701 newmode.fp_h_sync_strt_wid = newmode.crtc_h_sync_strt_wid;
2702 newmode.fp_v_sync_strt_wid = newmode.crtc_v_sync_strt_wid;
2707 radeon_write_mode (rinfo, &newmode);
2709 #if defined(CONFIG_BOOTX_TEXT)
2710 btext_update_display(rinfo->fb_base_phys, mode->xres, mode->yres,
2711 rinfo->depth, rinfo->pitch*64);
2718 static void radeon_write_mode (struct radeonfb_info *rinfo,
2719 struct radeon_regs *mode)
2722 int primary_mon = PRIMARY_MONITOR(rinfo);
2725 OUTREGP(CRTC_EXT_CNTL, CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS,
2726 ~(CRTC_DISPLAY_DIS | CRTC_VSYNC_DIS | CRTC_HSYNC_DIS));
2729 OUTREG(common_regs[i].reg, common_regs[i].val);
2731 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl);
2732 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl,
2733 CRTC_HSYNC_DIS | CRTC_VSYNC_DIS | CRTC_DISPLAY_DIS);
2734 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING);
2735 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp);
2736 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid);
2737 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp);
2738 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid);
2739 OUTREG(CRTC_OFFSET, 0);
2740 OUTREG(CRTC_OFFSET_CNTL, 0);
2741 OUTREG(CRTC_PITCH, mode->crtc_pitch);
2743 #if defined(__BIG_ENDIAN)
2744 OUTREG(SURFACE_CNTL, mode->surface_cntl);
2747 while ((INREG(CLOCK_CNTL_INDEX) & PPLL_DIV_SEL_MASK) !=
2748 PPLL_DIV_SEL_MASK) {
2749 OUTREGP(CLOCK_CNTL_INDEX, PPLL_DIV_SEL_MASK, 0xffff);
2752 OUTPLLP(PPLL_CNTL, PPLL_RESET, 0xffff);
2754 while ((INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK) !=
2755 (mode->ppll_ref_div & PPLL_REF_DIV_MASK)) {
2756 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK);
2759 while ((INPLL(PPLL_DIV_3) & PPLL_FB3_DIV_MASK) !=
2760 (mode->ppll_div_3 & PPLL_FB3_DIV_MASK)) {
2761 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK);
2764 while ((INPLL(PPLL_DIV_3) & PPLL_POST3_DIV_MASK) !=
2765 (mode->ppll_div_3 & PPLL_POST3_DIV_MASK)) {
2766 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK);
2769 OUTPLL(HTOTAL_CNTL, 0);
2771 OUTPLLP(PPLL_CNTL, 0, ~PPLL_RESET);
2773 OUTREG(DDA_CONFIG, mode->dda_config);
2774 OUTREG(DDA_ON_OFF, mode->dda_on_off);
2776 if ((primary_mon == MT_DFP) || (primary_mon == MT_LCD)) {
2777 OUTREG(FP_CRTC_H_TOTAL_DISP, mode->fp_crtc_h_total_disp);
2778 OUTREG(FP_CRTC_V_TOTAL_DISP, mode->fp_crtc_v_total_disp);
2779 OUTREG(FP_H_SYNC_STRT_WID, mode->fp_h_sync_strt_wid);
2780 OUTREG(FP_V_SYNC_STRT_WID, mode->fp_v_sync_strt_wid);
2781 OUTREG(FP_HORZ_STRETCH, mode->fp_horz_stretch);
2782 OUTREG(FP_VERT_STRETCH, mode->fp_vert_stretch);
2783 OUTREG(FP_GEN_CNTL, mode->fp_gen_cntl);
2784 OUTREG(TMDS_CRC, mode->tmds_crc);
2785 OUTREG(TMDS_TRANSMITTER_CNTL, mode->tmds_transmitter_cntl);
2787 if (primary_mon == MT_LCD) {
2788 unsigned int tmp = INREG(LVDS_GEN_CNTL);
2790 mode->lvds_gen_cntl &= ~LVDS_STATE_MASK;
2791 mode->lvds_gen_cntl |= (rinfo->init_state.lvds_gen_cntl & LVDS_STATE_MASK);
2793 if ((tmp & (LVDS_ON | LVDS_BLON)) ==
2794 (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON))) {
2795 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2797 if (mode->lvds_gen_cntl & (LVDS_ON | LVDS_BLON)) {
2799 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2801 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl |
2804 OUTREG(LVDS_GEN_CNTL, mode->lvds_gen_cntl);
2810 /* unblank screen */
2811 OUTREG8(CRTC_EXT_CNTL + 1, 0);
2813 OUTPLL(VCLK_ECP_CNTL, mode->vclk_ecp_cntl);
2819 #ifdef CONFIG_PMAC_BACKLIGHT
2821 static int backlight_conv[] = {
2822 0xff, 0xc0, 0xb5, 0xaa, 0x9f, 0x94, 0x89, 0x7e,
2823 0x73, 0x68, 0x5d, 0x52, 0x47, 0x3c, 0x31, 0x24
2826 #define BACKLIGHT_LVDS_OFF
2827 #undef BACKLIGHT_DAC_OFF
2829 /* We turn off the LCD completely instead of just dimming the backlight.
2830 * This provides some greater power saving and the display is useless
2831 * without backlight anyway.
2834 static int radeon_set_backlight_enable(int on, int level, void *data)
2836 struct radeonfb_info *rinfo = (struct radeonfb_info *)data;
2837 unsigned int lvds_gen_cntl = INREG(LVDS_GEN_CNTL);
2839 lvds_gen_cntl |= (LVDS_BL_MOD_EN | LVDS_BLON);
2840 if (on && (level > BACKLIGHT_OFF)) {
2841 lvds_gen_cntl |= LVDS_DIGON;
2842 if (!lvds_gen_cntl & LVDS_ON) {
2843 lvds_gen_cntl &= ~LVDS_BLON;
2844 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2845 (void)INREG(LVDS_GEN_CNTL);
2847 lvds_gen_cntl |= LVDS_BLON;
2848 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2850 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2851 lvds_gen_cntl |= (backlight_conv[level] <<
2852 LVDS_BL_MOD_LEVEL_SHIFT);
2853 lvds_gen_cntl |= (LVDS_ON | LVDS_EN);
2854 lvds_gen_cntl &= ~LVDS_DISPLAY_DIS;
2856 lvds_gen_cntl &= ~LVDS_BL_MOD_LEVEL_MASK;
2857 lvds_gen_cntl |= (backlight_conv[0] <<
2858 LVDS_BL_MOD_LEVEL_SHIFT);
2859 lvds_gen_cntl |= LVDS_DISPLAY_DIS;
2860 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2862 lvds_gen_cntl &= ~(LVDS_ON | LVDS_EN | LVDS_BLON | LVDS_DIGON);
2865 OUTREG(LVDS_GEN_CNTL, lvds_gen_cntl);
2866 rinfo->init_state.lvds_gen_cntl &= ~LVDS_STATE_MASK;
2867 rinfo->init_state.lvds_gen_cntl |= (lvds_gen_cntl & LVDS_STATE_MASK);
2872 static int radeon_set_backlight_level(int level, void *data)
2874 return radeon_set_backlight_enable(1, level, data);
2876 #endif /* CONFIG_PMAC_BACKLIGHT */
2879 #ifdef CONFIG_PMAC_PBOOK
2880 static void radeon_set_suspend(struct radeonfb_info *rinfo, int suspend)
2887 /* Set the chip into appropriate suspend mode (we use D2,
2888 * D3 would require a compete re-initialization of the chip,
2889 * including PCI config registers, clocks, AGP conf, ...)
2892 /* Save some registers */
2893 rinfo->save_regs[0] = INREG(CRTC_GEN_CNTL);
2894 rinfo->save_regs[1] = INREG(CRTC2_GEN_CNTL);
2897 OUTREG(CRTC_GEN_CNTL, (INREG(CRTC_GEN_CNTL) & ~CRTC_EN) | CRTC_DISP_REQ_EN_B);
2898 OUTREG(CRTC2_GEN_CNTL, (INREG(CRTC2_GEN_CNTL) & ~CRTC2_EN) | CRTC2_DISP_REQ_EN_B);
2899 (void)INREG(CRTC2_GEN_CNTL);
2902 /* Reset the MDLL */
2903 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) | MCKOA_RESET);
2904 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2906 /* Switch PCI power managment to D2. */
2908 pci_read_config_word(
2909 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2913 pci_write_config_word(
2914 rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL,
2915 (pwr_cmd & ~PCI_PM_CTRL_STATE_MASK) | 2);
2919 /* Switch back PCI powermanagment to D0 */
2921 pci_write_config_word(rinfo->pdev, rinfo->pm_reg+PCI_PM_CTRL, 0);
2924 /* Restore the MDLL */
2925 OUTPLL(MDLL_CKO, INPLL(MDLL_CKO) & ~MCKOA_RESET);
2927 /* Restore some registers */
2928 OUTREG(CRTC2_GEN_CNTL, rinfo->save_regs[1]);
2929 OUTREG(CRTC_GEN_CNTL, rinfo->save_regs[0]);
2934 * Save the contents of the framebuffer when we go to sleep,
2935 * and restore it when we wake up again.
2938 int radeon_sleep_notify(struct pmu_sleep_notifier *self, int when)
2940 struct radeonfb_info *rinfo;
2942 for (rinfo = board_list; rinfo != NULL; rinfo = rinfo->next) {
2943 struct fb_fix_screeninfo fix;
2945 struct display *disp;
2947 disp = (rinfo->currcon < 0) ? rinfo->info.disp : &fb_display[rinfo->currcon];
2949 switch (rinfo->chipset) {
2950 case PCI_DEVICE_ID_RADEON_LW:
2951 case PCI_DEVICE_ID_RADEON_LY:
2952 case PCI_DEVICE_ID_RADEON_LZ:
2953 case PCI_DEVICE_ID_RADEON_PM:
2956 return PBOOK_SLEEP_REFUSE;
2959 radeonfb_get_fix(&fix, fg_console, (struct fb_info *)rinfo);
2960 nb = fb_display[fg_console].var.yres * fix.line_length;
2963 case PBOOK_SLEEP_NOW:
2964 acquire_console_sem();
2965 disp->dispsw = &fbcon_dummy;
2968 /* Make sure engine is reset */
2969 radeon_engine_reset();
2970 radeon_engine_idle();
2973 /* Blank display and LCD */
2974 radeonfb_blank(VESA_POWERDOWN+1,
2975 (struct fb_info *)rinfo);
2979 radeon_set_suspend(rinfo, 1);
2980 release_console_sem();
2984 acquire_console_sem();
2986 radeon_set_suspend(rinfo, 0);
2989 radeon_engine_init(rinfo);
2991 radeon_set_dispsw(rinfo, disp);
2992 radeon_load_video_mode(rinfo, &disp->var);
2993 do_install_cmap(rinfo->currcon,
2994 (struct fb_info *)rinfo);
2996 radeonfb_blank(0, (struct fb_info *)rinfo);
2997 release_console_sem();
3002 return PBOOK_SLEEP_OK;
3005 #endif /* CONFIG_PMAC_PBOOK */
3008 * text console acceleration
3012 static void fbcon_radeon_bmove(struct display *p, int srcy, int srcx,
3013 int dsty, int dstx, int height, int width)
3015 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
3016 u32 dp_cntl = DST_LAST_PEL;
3018 srcx *= fontwidth(p);
3019 srcy *= fontheight(p);
3020 dstx *= fontwidth(p);
3021 dsty *= fontheight(p);
3022 width *= fontwidth(p);
3023 height *= fontheight(p);
3029 dp_cntl |= DST_Y_TOP_TO_BOTTOM;
3035 dp_cntl |= DST_X_LEFT_TO_RIGHT;
3037 radeon_fifo_wait(6);
3038 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
3040 GMC_SRC_DATATYPE_COLOR |
3042 DP_SRC_SOURCE_MEMORY));
3043 OUTREG(DP_WRITE_MSK, 0xffffffff);
3044 OUTREG(DP_CNTL, dp_cntl);
3045 OUTREG(SRC_Y_X, (srcy << 16) | srcx);
3046 OUTREG(DST_Y_X, (dsty << 16) | dstx);
3047 OUTREG(DST_HEIGHT_WIDTH, (height << 16) | width);
3052 static void fbcon_radeon_clear(struct vc_data *conp, struct display *p,
3053 int srcy, int srcx, int height, int width)
3055 struct radeonfb_info *rinfo = (struct radeonfb_info *)(p->fb_info);
3058 clr = attr_bgcol_ec(p, conp);
3062 srcx *= fontwidth(p);
3063 srcy *= fontheight(p);
3064 width *= fontwidth(p);
3065 height *= fontheight(p);
3067 radeon_fifo_wait(6);
3068 OUTREG(DP_GUI_MASTER_CNTL, (rinfo->dp_gui_master_cntl |
3069 GMC_BRUSH_SOLID_COLOR |
3070 GMC_SRC_DATATYPE_COLOR |
3072 OUTREG(DP_BRUSH_FRGD_CLR, clr);
3073 OUTREG(DP_WRITE_MSK, 0xffffffff);
3074 OUTREG(DP_CNTL, (DST_X_LEFT_TO_RIGHT | DST_Y_TOP_TO_BOTTOM));
3075 OUTREG(DST_Y_X, (srcy << 16) | srcx);
3076 OUTREG(DST_WIDTH_HEIGHT, (width << 16) | height);
3081 #ifdef FBCON_HAS_CFB8
3082 static struct display_switch fbcon_radeon8 = {
3083 setup: fbcon_cfb8_setup,
3084 bmove: fbcon_radeon_bmove,
3085 clear: fbcon_radeon_clear,
3086 putc: fbcon_cfb8_putc,
3087 putcs: fbcon_cfb8_putcs,
3088 revc: fbcon_cfb8_revc,
3089 clear_margins: fbcon_cfb8_clear_margins,
3090 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)