2 * linux/drivers/video/virgefb.c -- CyberVision64/3D frame buffer device
4 * Copyright (C) 1997 André Heynatz
7 * This file is based on the CyberVision frame buffer device (cyberfb.c):
9 * Copyright (C) 1996 Martin Apel
12 * Zorro II additions :
14 * Copyright (C) 1998-2000 Christian T. Steigies
16 * Initialization additions :
18 * Copyright (C) 1998-2000 Ken Tyler
20 * Parts of the Initialization code are based on Cyberfb.c by Allan Bair,
21 * and on the NetBSD CyberVision64 frame buffer driver by Michael Teske who gave
22 * permission for its use.
24 * Many thanks to Frank Mariak for his assistance with ZORRO 2 access and other
29 * This file is subject to the terms and conditions of the GNU General Public
30 * License. See the file COPYING in the main directory of this archive
37 #include <linux/module.h>
38 #include <linux/kernel.h>
39 #include <linux/errno.h>
40 #include <linux/string.h>
42 #include <linux/tty.h>
43 #include <linux/slab.h>
44 #include <linux/delay.h>
45 #include <linux/zorro.h>
47 #include <linux/init.h>
48 #include <asm/uaccess.h>
49 #include <asm/system.h>
50 #include <asm/amigahw.h>
53 #include <video/fbcon.h>
54 #include <video/fbcon-cfb8.h>
55 #include <video/fbcon-cfb16.h>
56 #include <video/fbcon-cfb32.h>
61 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "%s: " fmt, __FUNCTION__ , ## args)
63 #define DPRINTK(fmt, args...)
67 static void cv64_dump(void);
68 #define DUMP cv64_dump()
74 * Macros for register access and zorro control
77 static inline void mb_inline(void) { mb(); } /* for use in comma expressions */
84 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x01); \
91 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x02); \
98 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x04)) = 0x03); \
102 /* Set pass through, 0 = amiga, !=0 = cv64/3d */
104 #define SetVSwitch(x) \
106 (*(volatile u16 *)((u8 *)(vcode_switch_base)) = \
110 /* Zorro2 endian 'aperture' */
112 #define ENDIAN_BYTE 2
113 #define ENDIAN_WORD 1
114 #define ENDIAN_LONG 0
116 #define Select_Zorro2_FrameBuffer(x) \
120 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x08)) = \
126 /* SetPortVal - only used for interrupt enable (not yet implemented) */
129 #define SetPortVal(x) \
131 (*(volatile u16 *)((u8 *)(vcode_switch_base + 0x0c)) = \
138 #define byte_access_io(x) (((x) & 0x3ffc) | (((x) & 3)^3) | (((x) & 3) <<14))
139 #define byte_access_mmio(x) (((x) & 0xfffc) | (((x) & 3)^3))
141 /* Write 8 bit VGA register - used once for chip wakeup */
143 #define wb_vgaio(reg, dat) \
145 (*(volatile u8 *)(vgaio_regs + ((u32)byte_access_io(reg) & 0xffff)) = \
149 /* Read 8 bit VGA register - only used in dump (SelectIO not needed on read ?) */
152 #define rb_vgaio(reg) \
156 __zzyzx = (*(volatile u8 *)((vgaio_regs)+(u32)byte_access_io(reg))); \
164 /* Read 8 bit MMIO register */
166 #define rb_mmio(reg) \
168 (*(volatile u8 *)(mmio_regs + 0x8000 + (u32)byte_access_mmio(reg))))
170 /* Write 8 bit MMIO register */
172 #define wb_mmio(reg,dat) \
174 (*(volatile u8 *)(mmio_regs + 0x8000 + (byte_access_mmio((reg) & 0xffff))) = \
178 /* Read 32 bit MMIO register */
180 #define rl_mmio(reg) \
182 (*((volatile u32 *)((u8 *)((mmio_regs + (on_zorro2 ? 0x20000 : 0)) + (reg))))))
184 /* Write 32 bit MMIO register */
186 #define wl_mmio(reg,dat) \
188 ((*(volatile u32 *)((u8 *)((mmio_regs + (on_zorro2 ? 0x20000 : 0)) + (reg)))) = \
192 /* Write to virge graphics register */
194 #define wgfx(reg, dat) do { wb_mmio(GCT_ADDRESS, (reg)); wb_mmio(GCT_ADDRESS_W, (dat)); } while (0)
196 /* Write to virge sequencer register */
198 #define wseq(reg, dat) do { wb_mmio(SEQ_ADDRESS, (reg)); wb_mmio(SEQ_ADDRESS_W, (dat)); } while (0)
200 /* Write to virge CRT controller register */
202 #define wcrt(reg, dat) do { wb_mmio(CRT_ADDRESS, (reg)); wb_mmio(CRT_ADDRESS_W, (dat)); } while (0)
204 /* Write to virge attribute register */
206 #define watr(reg, dat) \
208 volatile unsigned char watr_tmp; \
209 watr_tmp = rb_mmio(ACT_ADDRESS_RESET); \
210 wb_mmio(ACT_ADDRESS_W, (reg)); \
211 wb_mmio(ACT_ADDRESS_W, (dat)); \
218 struct fb_var_screeninfo var;
225 static struct virgefb_par current_par;
227 static int current_par_valid = 0;
228 static int currcon = 0;
230 static struct display disp;
231 static struct fb_info fb_info;
234 #ifdef FBCON_HAS_CFB16
237 #ifdef FBCON_HAS_CFB32
243 * Switch for Chipset Independency
246 static struct fb_hwswitch {
252 /* Display Control */
254 int (*encode_fix)(struct fb_fix_screeninfo *fix, struct virgefb_par *par);
255 int (*decode_var)(struct fb_var_screeninfo *var, struct virgefb_par *par);
256 int (*encode_var)(struct fb_var_screeninfo *var, struct virgefb_par *par);
257 int (*getcolreg)(u_int regno, u_int *red, u_int *green, u_int *blue,
258 u_int *transp, struct fb_info *info);
259 int (*setcolreg)(u_int regno, u_int red, u_int green, u_int blue,
260 u_int transp, struct fb_info *info);
261 void (*blank)(int blank);
264 static unsigned char blit_maybe_busy = 0;
270 static char virgefb_name[16] = "CyberVision/3D";
273 * CyberVision64/3d Graphics Board
276 static unsigned char virgefb_colour_table [256][3];
277 static unsigned long v_ram;
278 static unsigned long v_ram_size;
279 static volatile unsigned char *mmio_regs;
280 static volatile unsigned char *vgaio_regs;
282 static unsigned long v_ram_phys;
283 static unsigned long mmio_regs_phys;
284 static unsigned long vcode_switch_base;
285 static unsigned char on_zorro2;
288 * Offsets from start of video ram to appropriate ZIII aperture
291 #ifdef FBCON_HAS_CFB8
292 #define CYBMEM_OFFSET_8 0x800000 /* BGRX */
294 #ifdef FBCON_HAS_CFB16
295 #define CYBMEM_OFFSET_16 0x400000 /* GBXR */
297 #ifdef FBCON_HAS_CFB32
298 #define CYBMEM_OFFSET_32 0x000000 /* XRGB */
302 * MEMCLOCK was 32MHz, 64MHz works, 72MHz doesn't (on my board)
305 #define MEMCLOCK 50000000
308 * Predefined Video Modes
313 struct fb_var_screeninfo var;
314 } virgefb_predefined[] __initdata = {
315 #ifdef FBCON_HAS_CFB8
317 "640x480-8", { /* Cybervision 8 bpp */
318 640, 480, 640, 480, 0, 0, 8, 0,
319 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
320 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 160, 136, 82, 61, 88, 2,
321 0, FB_VMODE_NONINTERLACED
324 "768x576-8", { /* Cybervision 8 bpp */
325 768, 576, 768, 576, 0, 0, 8, 0,
326 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
327 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
328 0, FB_VMODE_NONINTERLACED
331 "800x600-8", { /* Cybervision 8 bpp */
332 800, 600, 800, 600, 0, 0, 8, 0,
333 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
334 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
335 0, FB_VMODE_NONINTERLACED
339 "1024x768-8", { /* Cybervision 8 bpp */
340 1024, 768, 1024, 768, 0, 0, 8, 0,
341 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
342 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
343 0, FB_VMODE_NONINTERLACED
347 1024, 768, 1024, 768, 0, 0, 8, 0,
348 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
350 0, 0, -1, -1, FB_ACCELF_TEXT, 12500, 184, 40, 40, 2, 96, 1,
351 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
354 0, 0, -1, -1, FB_ACCELF_TEXT, 12699, 176, 16, 28, 1, 96, 3,
355 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
360 "1152x886-8", { /* Cybervision 8 bpp */
361 1152, 886, 1152, 886, 0, 0, 8, 0,
362 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
363 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
364 0, FB_VMODE_NONINTERLACED
367 "1280x1024-8", { /* Cybervision 8 bpp */
368 1280, 1024, 1280, 1024, 0, 0, 8, 0,
369 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
371 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
374 0, 0, -1, -1, FB_ACCELF_TEXT, 7414, 232, 64, 38, 1, 112, 3,
375 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
379 "1600x1200-8", { /* Cybervision 8 bpp */
380 1600, 1200, 1600, 1200, 0, 0, 8, 0,
381 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
383 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
384 0, FB_VMODE_NONINTERLACED
387 0, 0, -1, -1, FB_ACCELF_TEXT, 6411, 256, 32, 52, 10, 160, 8,
388 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
394 #ifdef FBCON_HAS_CFB16
396 "640x480-16", { /* Cybervision 16 bpp */
397 640, 480, 640, 480, 0, 0, 16, 0,
398 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
399 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 152, 144, 82, 61, 88, 2,
400 0, FB_VMODE_NONINTERLACED
403 "768x576-16", { /* Cybervision 16 bpp */
404 768, 576, 768, 576, 0, 0, 16, 0,
405 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
406 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
407 0, FB_VMODE_NONINTERLACED
410 "800x600-16", { /* Cybervision 16 bpp */
411 800, 600, 800, 600, 0, 0, 16, 0,
412 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
413 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
414 0, FB_VMODE_NONINTERLACED
418 "1024x768-16", { /* Cybervision 16 bpp */
419 1024, 768, 1024, 768, 0, 0, 16, 0,
420 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
421 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
422 0, FB_VMODE_NONINTERLACED
426 1024, 768, 1024, 768, 0, 0, 16, 0,
427 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
428 0, 0, -1, -1, FB_ACCELF_TEXT, 12500, 184, 40, 40, 2, 96, 1,
429 FB_SYNC_COMP_HIGH_ACT|FB_SYNC_VERT_HIGH_ACT, FB_VMODE_NONINTERLACED
433 "1152x886-16", { /* Cybervision 16 bpp */
434 1152, 886, 1152, 886, 0, 0, 16, 0,
435 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
436 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
437 0, FB_VMODE_NONINTERLACED
440 "1280x1024-16", { /* Cybervision 16 bpp */
441 1280, 1024, 1280, 1024, 0, 0, 16, 0,
442 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
443 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
444 0, FB_VMODE_NONINTERLACED
447 "1600x1200-16", { /* Cybervision 16 bpp */
448 1600, 1200, 1600, 1200, 0, 0, 16, 0,
449 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
450 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
451 0, FB_VMODE_NONINTERLACED
456 #ifdef FBCON_HAS_CFB32
458 "640x480-32", { /* Cybervision 32 bpp */
459 640, 480, 640, 480, 0, 0, 32, 0,
460 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
461 0, 0, -1, -1, FB_ACCELF_TEXT, 31250, 160, 136, 82, 61, 88, 2,
462 0, FB_VMODE_NONINTERLACED
465 "768x576-32", { /* Cybervision 32 bpp */
466 768, 576, 768, 576, 0, 0, 32, 0,
467 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
468 0, 0, -1, -1, FB_ACCELF_TEXT, 29411, 144, 112, 32, 15, 64, 2,
469 0, FB_VMODE_NONINTERLACED
472 "800x600-32", { /* Cybervision 32 bpp */
473 800, 600, 800, 600, 0, 0, 32, 0,
474 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
475 0, 0, -1, -1, FB_ACCELF_TEXT, 28571, 168, 104, 22, 1, 48, 2,
476 0, FB_VMODE_NONINTERLACED
479 "1024x768-32", { /* Cybervision 32 bpp */
480 1024, 768, 1024, 768, 0, 0, 32, 0,
481 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
482 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
483 0, FB_VMODE_NONINTERLACED
486 "1152x886-32", { /* Cybervision 32 bpp */
487 1152, 886, 1152, 886, 0, 0, 32, 0,
488 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
489 0, 0, -1, -1, FB_ACCELF_TEXT, 19230, 280, 168, 45, 1, 64, 10,
490 0, FB_VMODE_NONINTERLACED
493 "1280x1024-32", { /* Cybervision 32 bpp */
494 1280, 1024, 1280, 1024, 0, 0, 32, 0,
495 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
496 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
497 0, FB_VMODE_NONINTERLACED
500 "1600x1200-32", { /* Cybervision 32 bpp */
501 1600, 1200, 1600, 1200, 0, 0, 32, 0,
502 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
503 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
504 0, FB_VMODE_NONINTERLACED
509 /* interlaced modes */
511 #ifdef FBCON_HAS_CFB8
513 "1024x768-8i", { /* Cybervision 8 bpp */
514 1024, 768, 1024, 768, 0, 0, 8, 0,
515 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
516 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
517 0, FB_VMODE_INTERLACED
520 "1280x1024-8i", { /* Cybervision 8 bpp */
521 1280, 1024, 1280, 1024, 0, 0, 8, 0,
522 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
523 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
524 0, FB_VMODE_INTERLACED
527 "1600x1200-8i", { /* Cybervision 8 bpp */
528 1600, 1200, 1600, 1200, 0, 0, 8, 0,
529 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
530 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
531 0, FB_VMODE_INTERLACED
536 #ifdef FBCON_HAS_CFB16
538 "1024x768-16i", { /* Cybervision 16 bpp */
539 1024, 768, 1024, 768, 0, 0, 16, 0,
540 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
541 0, 0, -1, -1, FB_ACCELF_TEXT, 20833, 272, 168, 39, 2, 72, 1,
542 0, FB_VMODE_INTERLACED
545 "1280x1024-16i", { /* Cybervision 16 bpp */
546 1280, 1024, 1280, 1024, 0, 0, 16, 0,
547 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
548 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
549 0, FB_VMODE_INTERLACED
552 "1600x1200-16i", { /* Cybervision 16 bpp */
553 1600, 1200, 1600, 1200, 0, 0, 16, 0,
554 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
555 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
556 0, FB_VMODE_INTERLACED
561 #ifdef FBCON_HAS_CFB32
563 "1024x768-32i", { /* Cybervision 32 bpp */
564 1024, 768, 1024, 768, 0, 0, 32, 0,
565 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
566 0, 0, -1, -1, FB_ACCELF_TEXT, 22222, 216, 144, 39, 2, 72, 1,
567 0, FB_VMODE_INTERLACED
570 "1280x1024-32i", { /* Cybervision 32 bpp */
571 1280, 1024, 1280, 1024, 0, 0, 32, 0,
572 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {23, 0, 0},
573 0, 0, -1, -1, FB_ACCELF_TEXT, 17857, 232, 232, 71, 15, 176, 12,
574 0, FB_VMODE_INTERLACED
577 "1600x1200-32i", { /* Cybervision 32 bpp */
578 1600, 1200, 1600, 1200, 0, 0, 32, 0,
579 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
580 0, 0, -1, -1, FB_ACCELF_TEXT, 13698, 336, 224, 77, 15, 176, 12,
581 0, FB_VMODE_INTERLACED
586 /* doublescan modes */
588 #ifdef FBCON_HAS_CFB8
590 "320x240-8d", { /* Cybervision 8 bpp */
591 320, 240, 320, 240, 0, 0, 8, 0,
592 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
593 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
599 #ifdef FBCON_HAS_CFB16
601 "320x240-16d", { /* Cybervision 16 bpp */
602 320, 240, 320, 240, 0, 0, 16, 0,
603 {11, 5, 0}, {5, 6, 0}, {0, 5, 0}, {0, 0, 0},
604 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
610 #ifdef FBCON_HAS_CFB32
612 "320x240-32d", { /* Cybervision 32 bpp */
613 320, 240, 320, 240, 0, 0, 32, 0,
614 {16, 8, 0}, {8, 8, 0}, {0, 8, 0}, {24, 0, 0},
615 0, 0, -1, -1, FB_ACCELF_TEXT, 59259, 80, 80, 45, 26, 32, 1,
622 #define arraysize(x) (sizeof(x)/sizeof(*(x)))
623 #define NUM_TOTAL_MODES arraysize(virgefb_predefined)
626 * Default to 800x600 for video=virge8:, virge16: or virge32:
629 #ifdef FBCON_HAS_CFB8
630 #define VIRGE8_DEFMODE (2)
633 #ifdef FBCON_HAS_CFB16
634 #define VIRGE16_DEFMODE (9)
637 #ifdef FBCON_HAS_CFB32
638 #define VIRGE32_DEFMODE (16)
641 static struct fb_var_screeninfo virgefb_default;
642 static int virgefb_inverse = 0;
645 * Interface used by the world
648 int virgefb_setup(char*);
649 static int virgefb_get_fix(struct fb_fix_screeninfo *fix, int con, struct fb_info *info);
650 static int virgefb_get_var(struct fb_var_screeninfo *var, int con, struct fb_info *info);
651 static int virgefb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info);
652 static int virgefb_get_cmap(struct fb_cmap *cmap, int kspc, int con, struct fb_info *info);
653 static int virgefb_set_cmap(struct fb_cmap *cmap, int kspc, int con, struct fb_info *info);
656 * Interface to the low level console driver
659 int virgefb_init(void);
660 static int virgefb_switch(int con, struct fb_info *info);
661 static int virgefb_updatevar(int con, struct fb_info *info);
662 static void virgefb_blank(int blank, struct fb_info *info);
665 * Text console acceleration
668 #ifdef FBCON_HAS_CFB8
669 static struct display_switch fbcon_virge8;
672 #ifdef FBCON_HAS_CFB16
673 static struct display_switch fbcon_virge16;
676 #ifdef FBCON_HAS_CFB32
677 static struct display_switch fbcon_virge32;
681 * Hardware Specific Routines
684 static int Cyber_init(void);
685 static int virgefb_encode_fix(struct fb_fix_screeninfo *fix,
686 struct virgefb_par *par);
687 static int virgefb_decode_var(struct fb_var_screeninfo *var,
688 struct virgefb_par *par);
689 static int virgefb_encode_var(struct fb_var_screeninfo *var,
690 struct virgefb_par *par);
691 static int virgefb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
692 u_int *transp, struct fb_info *info);
693 static int virgefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
694 u_int transp, struct fb_info *info);
695 static void virgefb_gfx_on_off(int blank);
696 static inline void virgefb_wait_for_idle(void);
697 static void virgefb_BitBLT(u_short curx, u_short cury, u_short destx, u_short desty,
698 u_short width, u_short height, u_short stride, u_short depth);
699 static void virgefb_RectFill(u_short x, u_short y, u_short width, u_short height,
700 u_short color, u_short stride, u_short depth);
706 static void virgefb_get_par(struct virgefb_par *par);
707 static void virgefb_set_par(struct virgefb_par *par);
708 static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive);
709 static void virgefb_do_install_cmap(int con, struct fb_info *info);
710 static void virgefb_set_disp(int con, struct fb_info *info);
711 static int virgefb_get_video_mode(const char *name);
712 static void virgefb_set_video(struct fb_var_screeninfo *var);
715 * Additions for Initialization
718 static void virgefb_load_video_mode(struct fb_var_screeninfo *video_mode);
719 static int cv3d_has_4mb(void);
720 static unsigned short virgefb_compute_clock(unsigned long freq);
721 static inline unsigned char rattr(short);
722 static inline unsigned char rseq(short);
723 static inline unsigned char rcrt(short);
724 static inline unsigned char rgfx(short);
725 static inline void gfx_on_off(int toggle);
726 static void virgefb_pci_init(void);
728 /* -------------------- Hardware specific routines ------------------------- */
731 * Functions for register access
734 /* Read attribute controller register */
736 static inline unsigned char rattr(short idx)
738 volatile unsigned char rattr_tmp;
740 rattr_tmp = rb_mmio(ACT_ADDRESS_RESET);
741 wb_mmio(ACT_ADDRESS_W, idx);
742 return (rb_mmio(ACT_ADDRESS_R));
745 /* Read sequencer register */
747 static inline unsigned char rseq(short idx)
749 wb_mmio(SEQ_ADDRESS, idx);
750 return (rb_mmio(SEQ_ADDRESS_R));
753 /* Read CRT controller register */
755 static inline unsigned char rcrt(short idx)
757 wb_mmio(CRT_ADDRESS, idx);
758 return (rb_mmio(CRT_ADDRESS_R));
761 /* Read graphics controller register */
763 static inline unsigned char rgfx(short idx)
765 wb_mmio(GCT_ADDRESS, idx);
766 return (rb_mmio(GCT_ADDRESS_R));
776 void virgefb_pci_init(void) {
783 *((short *)(vgaio_regs + 0x00000010)) = 0;
784 *((long *)(vgaio_regs + 0x00000004)) = 0x02000003;
786 *((short *)(vgaio_regs + 0x000e0010)) = 0;
787 *((long *)(vgaio_regs + 0x000e0004)) = 0x02000003;
790 /* SelectIO is in wb_vgaio macro */
791 wb_vgaio(SREG_VIDEO_SUBS_ENABLE, 0x01);
792 /* SelectMMIO is in wb_vgaio macro */
800 * Initalize all mode independent regs, find mem size and clear mem
803 static int Cyber_init(void)
812 wb_mmio(GREG_MISC_OUTPUT_W, 0x07); /* colour, ram enable, clk sel */
814 wseq(SEQ_ID_UNLOCK_EXT, 0x06); /* unlock extensions */
815 tmp = rb_mmio(GREG_MISC_OUTPUT_R);
816 wcrt(CRT_ID_REGISTER_LOCK_1, 0x48); /* unlock CR2D to CR3F */
818 wcrt(CRT_ID_BACKWAD_COMP_1, 0x00); /* irq disable */
820 wcrt(CRT_ID_REGISTER_LOCK_2, 0xa5); /* unlock CR40 to CRFF and more */
821 wcrt(CRT_ID_REGISTER_LOCK,0x00); /* unlock h and v timing */
822 wcrt(CRT_ID_SYSTEM_CONFIG, 0x01); /* unlock enhanced programming registers */
824 wb_mmio(GREG_FEATURE_CONTROL_W, 0x00);
826 wcrt(CRT_ID_EXT_MISC_CNTL, 0x00); /* b2 = 0 to allow VDAC mmio access */
828 /* write strap options ... ? */
829 wcrt(CRT_ID_CONFIG_1, 0x08);
830 wcrt(CRT_ID_CONFIG_2, 0xff); /* 0x0x2 bit needs to be set ?? */
831 wcrt(CRT_ID_CONFIG_3, 0x0f);
832 wcrt(CRT_ID_CONFIG_4, 0x1a);
834 wcrt(CRT_ID_EXT_MISC_CNTL_1, 0x82); /* PCI DE and software reset S3D engine */
835 /* EXT_MISC_CNTL_1, CR66 bit 0 should be the same as bit 0 MR_ADVANCED_FUNCTION_CONTROL - check */
836 wl_mmio(MR_ADVANCED_FUNCTION_CONTROL, 0x00000011); /* enhanced mode, linear addressing */
840 wcrt(CRT_ID_PRESET_ROW_SCAN, 0x00);
842 /* Disable h/w cursor */
844 wcrt(CRT_ID_CURSOR_START, 0x00);
845 wcrt(CRT_ID_CURSOR_END, 0x00);
846 wcrt(CRT_ID_START_ADDR_HIGH, 0x00);
847 wcrt(CRT_ID_START_ADDR_LOW, 0x00);
848 wcrt(CRT_ID_CURSOR_LOC_HIGH, 0x00);
849 wcrt(CRT_ID_CURSOR_LOC_LOW, 0x00);
850 wcrt(CRT_ID_EXT_MODE, 0x00);
851 wcrt(CRT_ID_HWGC_MODE, 0x00);
852 wcrt(CRT_ID_HWGC_ORIGIN_X_HI, 0x00);
853 wcrt(CRT_ID_HWGC_ORIGIN_X_LO, 0x00);
854 wcrt(CRT_ID_HWGC_ORIGIN_Y_HI, 0x00);
855 wcrt(CRT_ID_HWGC_ORIGIN_Y_LO, 0x00);
856 i = rcrt(CRT_ID_HWGC_MODE);
857 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
858 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
859 wcrt(CRT_ID_HWGC_FG_STACK, 0x00);
860 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
861 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
862 wcrt(CRT_ID_HWGC_BG_STACK, 0x00);
863 wcrt(CRT_ID_HWGC_START_AD_HI, 0x00);
864 wcrt(CRT_ID_HWGC_START_AD_LO, 0x00);
865 wcrt(CRT_ID_HWGC_DSTART_X, 0x00);
866 wcrt(CRT_ID_HWGC_DSTART_Y, 0x00);
868 wcrt(CRT_ID_UNDERLINE_LOC, 0x00);
870 wcrt(CRT_ID_MODE_CONTROL, 0xe3);
871 wcrt(CRT_ID_BACKWAD_COMP_2, 0x22); /* blank bdr bit 5 blanking only on 8 bit */
873 wcrt(CRT_ID_EX_SYNC_1, 0x00);
877 wcrt(CRT_ID_EXT_SYS_CNTL_3, 0x00);
878 wcrt(CRT_ID_MEMORY_CONF, 0x08); /* config enhanced map */
879 wcrt(CRT_ID_EXT_MEM_CNTL_1, 0x08); /* MMIO Select (0x0c works as well)*/
880 wcrt(CRT_ID_EXT_MEM_CNTL_2, 0x02); /* why 02 big endian 00 works ? */
881 wcrt(CRT_ID_EXT_MEM_CNTL_4, 0x9f); /* config big endian - 0x00 ? */
882 wcrt(CRT_ID_LAW_POS_HI, 0x00);
883 wcrt(CRT_ID_LAW_POS_LO, 0x00);
884 wcrt(CRT_ID_EXT_MISC_CNTL_1, 0x81);
885 wcrt(CRT_ID_MISC_1, 0x90); /* must follow CRT_ID_EXT_MISC_CNTL_1 */
886 wcrt(CRT_ID_LAW_CNTL, 0x13); /* force 4 Meg for test */
887 if (cv3d_has_4mb()) {
888 v_ram_size = 0x00400000;
889 wcrt(CRT_ID_LAW_CNTL, 0x13); /* 4 MB */
891 v_ram_size = 0x00200000;
892 wcrt(CRT_ID_LAW_CNTL, 0x12); /* 2 MB */
896 v_ram_size -= 0x60000; /* we need some space for the registers */
898 wcrt(CRT_ID_EXT_SYS_CNTL_4, 0x00);
899 wcrt(CRT_ID_EXT_DAC_CNTL, 0x00); /* 0x10 for X11 cursor mode */
901 /* sequencer registers */
903 wseq(SEQ_ID_CLOCKING_MODE, 0x01); /* 8 dot clock */
904 wseq(SEQ_ID_MAP_MASK, 0xff);
905 wseq(SEQ_ID_CHAR_MAP_SELECT, 0x00);
906 wseq(SEQ_ID_MEMORY_MODE, 0x02);
907 wseq(SEQ_ID_RAMDAC_CNTL, 0x00);
908 wseq(SEQ_ID_SIGNAL_SELECT, 0x00);
909 wseq(SEQ_ID_EXT_SEQ_REG9, 0x00); /* MMIO and PIO reg access enabled */
910 wseq(SEQ_ID_EXT_MISC_SEQ, 0x00);
911 wseq(SEQ_ID_CLKSYN_CNTL_1, 0x00);
912 wseq(SEQ_ID_EXT_SEQ, 0x00);
914 /* graphic registers */
916 wgfx(GCT_ID_SET_RESET, 0x00);
917 wgfx(GCT_ID_ENABLE_SET_RESET, 0x00);
918 wgfx(GCT_ID_COLOR_COMPARE, 0x00);
919 wgfx(GCT_ID_DATA_ROTATE, 0x00);
920 wgfx(GCT_ID_READ_MAP_SELECT, 0x00);
921 wgfx(GCT_ID_GRAPHICS_MODE, 0x40);
922 wgfx(GCT_ID_MISC, 0x01);
923 wgfx(GCT_ID_COLOR_XCARE, 0x0f);
924 wgfx(GCT_ID_BITMASK, 0xff);
926 /* attribute registers */
928 for(i = 0; i <= 15; i++)
929 watr(ACT_ID_PALETTE0 + i, i);
930 watr(ACT_ID_ATTR_MODE_CNTL, 0x41);
931 watr(ACT_ID_OVERSCAN_COLOR, 0xff);
932 watr(ACT_ID_COLOR_PLANE_ENA, 0x0f);
933 watr(ACT_ID_HOR_PEL_PANNING, 0x00);
934 watr(ACT_ID_COLOR_SELECT, 0x00);
936 wb_mmio(VDAC_MASK, 0xff);
938 /* init local cmap as greyscale levels */
940 for (i = 0; i < 256; i++) {
941 virgefb_colour_table [i][0] = i;
942 virgefb_colour_table [i][1] = i;
943 virgefb_colour_table [i][2] = i;
946 /* clear framebuffer memory */
948 memset((char*)v_ram, 0x00, v_ram_size);
956 * This function should fill in the `fix' structure based on the
957 * values in the `par' structure.
960 static int virgefb_encode_fix(struct fb_fix_screeninfo *fix,
961 struct virgefb_par *par)
963 DPRINTK("ENTER set video phys addr\n");
965 memset(fix, 0, sizeof(struct fb_fix_screeninfo));
966 strcpy(fix->id, virgefb_name);
968 fix->smem_start = v_ram_phys;
969 switch (par->var.bits_per_pixel) {
970 #ifdef FBCON_HAS_CFB8
973 Select_Zorro2_FrameBuffer(ENDIAN_BYTE);
975 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_8);
978 #ifdef FBCON_HAS_CFB16
981 Select_Zorro2_FrameBuffer(ENDIAN_WORD);
983 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_16);
986 #ifdef FBCON_HAS_CFB32
989 Select_Zorro2_FrameBuffer(ENDIAN_LONG);
991 fix->smem_start = (v_ram_phys + CYBMEM_OFFSET_32);
996 fix->smem_len = v_ram_size;
997 fix->mmio_start = mmio_regs_phys;
998 fix->mmio_len = 0x10000; /* TODO: verify this for the CV64/3D */
1000 fix->type = FB_TYPE_PACKED_PIXELS;
1002 if (par->var.bits_per_pixel == 8)
1003 fix->visual = FB_VISUAL_PSEUDOCOLOR;
1005 fix->visual = FB_VISUAL_TRUECOLOR;
1010 fix->line_length = par->var.xres_virtual*par->var.bits_per_pixel/8;
1011 fix->accel = FB_ACCEL_S3_VIRGE;
1012 DPRINTK("EXIT v_ram_phys = 0x%8.8lx\n", (unsigned long)fix->smem_start);
1018 * Fill the `par' structure based on the values in `var'.
1019 * TODO: Verify and adjust values, return -EINVAL if bad.
1022 static int virgefb_decode_var(struct fb_var_screeninfo *var,
1023 struct virgefb_par *par)
1026 par->var.xres = var->xres;
1027 par->var.yres = var->yres;
1028 par->var.xres_virtual = var->xres_virtual;
1029 par->var.yres_virtual = var->yres_virtual;
1030 /* roundup and validate */
1031 par->var.xres = (par->var.xres+7) & ~7;
1032 par->var.xres_virtual = (par->var.xres_virtual+7) & ~7;
1033 if (par->var.xres_virtual < par->var.xres)
1034 par->var.xres_virtual = par->var.xres;
1035 if (par->var.yres_virtual < par->var.yres)
1036 par->var.yres_virtual = par->var.yres;
1037 par->var.xoffset = var->xoffset;
1038 par->var.yoffset = var->yoffset;
1039 par->var.bits_per_pixel = var->bits_per_pixel;
1040 if (par->var.bits_per_pixel <= 8)
1041 par->var.bits_per_pixel = 8;
1042 else if (par->var.bits_per_pixel <= 16)
1043 par->var.bits_per_pixel = 16;
1045 par->var.bits_per_pixel = 32;
1046 #ifndef FBCON_HAS_CFB32
1047 if (par->var.bits_per_pixel == 32)
1048 par->var.bits_per_pixel = 16;
1050 #ifndef FBCON_HAS_CFB16
1051 if (par->var.bits_per_pixel == 16)
1052 par->var.bits_per_pixel = 8;
1054 par->var.grayscale = var->grayscale;
1055 par->var.red = var->red;
1056 par->var.green = var->green;
1057 par->var.blue = var->blue;
1058 par->var.transp = var->transp;
1059 par->var.nonstd = var->nonstd;
1060 par->var.activate = var->activate;
1061 par->var.height = var->height;
1062 par->var.width = var->width;
1063 if (var->accel_flags & FB_ACCELF_TEXT) {
1064 par->var.accel_flags = FB_ACCELF_TEXT;
1066 par->var.accel_flags = 0;
1068 par->var.pixclock = var->pixclock;
1069 par->var.left_margin = var->left_margin;
1070 par->var.right_margin = var->right_margin;
1071 par->var.upper_margin = var->upper_margin;
1072 par->var.lower_margin = var->lower_margin;
1073 par->var.hsync_len = var->hsync_len;
1074 par->var.vsync_len = var->vsync_len;
1075 par->var.sync = var->sync;
1076 par->var.vmode = var->vmode;
1082 * Fill the `var' structure based on the values in `par' and maybe
1083 * other values read out of the hardware.
1086 static int virgefb_encode_var(struct fb_var_screeninfo *var,
1087 struct virgefb_par *par)
1090 memset(var, 0, sizeof(struct fb_var_screeninfo)); /* need this ? */
1091 var->xres = par->var.xres;
1092 var->yres = par->var.yres;
1093 var->xres_virtual = par->var.xres_virtual;
1094 var->yres_virtual = par->var.yres_virtual;
1095 var->xoffset = par->var.xoffset;
1096 var->yoffset = par->var.yoffset;
1097 var->bits_per_pixel = par->var.bits_per_pixel;
1098 var->grayscale = par->var.grayscale;
1099 var->red = par->var.red;
1100 var->green = par->var.green;
1101 var->blue = par->var.blue;
1102 var->transp = par->var.transp;
1103 var->nonstd = par->var.nonstd;
1104 var->activate = par->var.activate;
1105 var->height = par->var.height;
1106 var->width = par->var.width;
1107 var->accel_flags = par->var.accel_flags;
1108 var->pixclock = par->var.pixclock;
1109 var->left_margin = par->var.left_margin;
1110 var->right_margin = par->var.right_margin;
1111 var->upper_margin = par->var.upper_margin;
1112 var->lower_margin = par->var.lower_margin;
1113 var->hsync_len = par->var.hsync_len;
1114 var->vsync_len = par->var.vsync_len;
1115 var->sync = par->var.sync;
1116 var->vmode = par->var.vmode;
1122 * Set a single color register. The values supplied are already
1123 * rounded down to the hardware's capabilities (according to the
1124 * entries in the var structure). Return != 0 for invalid regno.
1127 static int virgefb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
1128 u_int transp, struct fb_info *info)
1131 if (((current_par.var.bits_per_pixel==8) && (regno>255)) ||
1132 ((current_par.var.bits_per_pixel!=8) && (regno>15))) {
1136 if (((current_par.var.bits_per_pixel==8) && (regno<256)) ||
1137 ((current_par.var.bits_per_pixel!=8) && (regno<16))) {
1138 virgefb_colour_table [regno][0] = red >> 10;
1139 virgefb_colour_table [regno][1] = green >> 10;
1140 virgefb_colour_table [regno][2] = blue >> 10;
1143 switch (current_par.var.bits_per_pixel) {
1144 #ifdef FBCON_HAS_CFB8
1146 wb_mmio(VDAC_ADDRESS_W, (unsigned char)regno);
1147 wb_mmio(VDAC_DATA, ((unsigned char)(red >> 10)));
1148 wb_mmio(VDAC_DATA, ((unsigned char)(green >> 10)));
1149 wb_mmio(VDAC_DATA, ((unsigned char)(blue >> 10)));
1152 #ifdef FBCON_HAS_CFB16
1154 fbcon_cmap.cfb16[regno] =
1156 ((green & 0xfc00) >> 5) |
1157 ((blue & 0xf800) >> 11));
1160 #ifdef FBCON_HAS_CFB32
1162 fbcon_cmap.cfb32[regno] =
1163 /* transp = 0's or 1's ? */
1164 (((red & 0xff00) << 8) |
1165 ((green & 0xff00) >> 0) |
1166 ((blue & 0xff00) >> 8));
1176 * Read a single color register and split it into
1177 * colors/transparent. Return != 0 for invalid regno.
1180 static int virgefb_getcolreg(u_int regno, u_int *red, u_int *green, u_int *blue,
1181 u_int *transp, struct fb_info *info)
1190 if (((current_par.var.bits_per_pixel==8) && (regno<256)) ||
1191 ((current_par.var.bits_per_pixel!=8) && (regno<16))) {
1193 t = virgefb_colour_table [regno][0];
1194 *red = (t<<10) | (t<<4) | (t>>2);
1195 t = virgefb_colour_table [regno][1];
1196 *green = (t<<10) | (t<<4) | (t>>2);
1197 t = virgefb_colour_table [regno][2];
1198 *blue = (t<<10) | (t<<4) | (t>>2);
1207 * (Un)Blank the screen
1210 static void virgefb_gfx_on_off(int blank)
1218 * CV3D low-level support
1222 static inline void wait_3d_fifo_slots(int n) /* WaitQueue */
1226 } while (((rl_mmio(MR_SUBSYSTEM_STATUS_R) >> 8) & 0x1f) < (n + 2));
1229 static inline void virgefb_wait_for_idle(void) /* WaitIdle */
1231 while(!(rl_mmio(MR_SUBSYSTEM_STATUS_R) & 0x2000)) ;
1232 blit_maybe_busy = 0;
1236 * BitBLT - Through the Plane
1239 static void virgefb_BitBLT(u_short curx, u_short cury, u_short destx, u_short desty,
1240 u_short width, u_short height, u_short stride, u_short depth)
1242 unsigned int blitcmd = S3V_BITBLT | S3V_DRAW | S3V_BLT_COPY;
1245 #ifdef FBCON_HAS_CFB8
1247 blitcmd |= S3V_DST_8BPP;
1250 #ifdef FBCON_HAS_CFB16
1252 blitcmd |= S3V_DST_16BPP;
1255 #ifdef FBCON_HAS_CFB32
1257 /* 32 bit uses 2 by 16 bit values, see fbcon_virge32_bmove */
1258 blitcmd |= S3V_DST_16BPP;
1263 /* Set drawing direction */
1264 /* -Y, X maj, -X (default) */
1266 blitcmd |= (1 << 25); /* Drawing direction +X */
1268 curx += (width - 1);
1269 destx += (width - 1);
1273 blitcmd |= (1 << 26); /* Drawing direction +Y */
1275 cury += (height - 1);
1276 desty += (height - 1);
1279 wait_3d_fifo_slots(8); /* wait on fifo slots for 8 writes */
1281 if (blit_maybe_busy)
1282 virgefb_wait_for_idle();
1283 blit_maybe_busy = 1;
1285 wl_mmio(BLT_PATTERN_COLOR, 1); /* pattern fb color */
1286 wl_mmio(BLT_MONO_PATTERN_0, ~0);
1287 wl_mmio(BLT_MONO_PATTERN_1, ~0);
1288 wl_mmio(BLT_SIZE_X_Y, ((width << 16) | height));
1289 wl_mmio(BLT_SRC_X_Y, ((curx << 16) | cury));
1290 wl_mmio(BLT_DEST_X_Y, ((destx << 16) | desty));
1291 wl_mmio(BLT_SRC_DEST_STRIDE, (((stride << 16) | stride) /* & 0x0ff80ff8 */)); /* why is this needed now ? */
1292 wl_mmio(BLT_COMMAND_SET, blitcmd);
1296 * Rectangle Fill Solid
1299 static void virgefb_RectFill(u_short x, u_short y, u_short width, u_short height,
1300 u_short color, u_short stride, u_short depth)
1302 unsigned int blitcmd = S3V_RECTFILL | S3V_DRAW |
1303 S3V_BLT_CLEAR | S3V_MONO_PAT | (1 << 26) | (1 << 25);
1306 #ifdef FBCON_HAS_CFB8
1308 blitcmd |= S3V_DST_8BPP;
1311 #ifdef FBCON_HAS_CFB16
1313 blitcmd |= S3V_DST_16BPP;
1316 #ifdef FBCON_HAS_CFB32
1318 /* 32 bit uses 2 times 16 bit values, see fbcon_virge32_clear */
1319 blitcmd |= S3V_DST_16BPP;
1324 wait_3d_fifo_slots(5); /* wait on fifo slots for 5 writes */
1326 if (blit_maybe_busy)
1327 virgefb_wait_for_idle();
1328 blit_maybe_busy = 1;
1330 wl_mmio(BLT_PATTERN_COLOR, (color & 0xff));
1331 wl_mmio(BLT_SIZE_X_Y, ((width << 16) | height));
1332 wl_mmio(BLT_DEST_X_Y, ((x << 16) | y));
1333 wl_mmio(BLT_SRC_DEST_STRIDE, (((stride << 16) | stride) /* & 0x0ff80ff8 */));
1334 wl_mmio(BLT_COMMAND_SET, blitcmd);
1338 * Move cursor to x, y
1342 static void virgefb_move_cursor(u_short x, u_short y)
1344 DPRINTK("Yuck .... MoveCursor on a 3D\n");
1349 /* -------------------- Interfaces to hardware functions -------------------- */
1351 static struct fb_hwswitch virgefb_hw_switch = {
1352 Cyber_init, virgefb_encode_fix, virgefb_decode_var, virgefb_encode_var,
1353 virgefb_getcolreg, virgefb_setcolreg, virgefb_gfx_on_off
1357 /* -------------------- Generic routines ------------------------------------ */
1361 * Fill the hardware's `par' structure.
1364 static void virgefb_get_par(struct virgefb_par *par)
1367 if (current_par_valid) {
1370 fbhw->decode_var(&virgefb_default, par);
1376 static void virgefb_set_par(struct virgefb_par *par)
1380 current_par_valid = 1;
1385 static void virgefb_set_video(struct fb_var_screeninfo *var)
1387 /* Set clipping rectangle to current screen size */
1392 wait_3d_fifo_slots(4);
1393 clip = ((0 << 16) | (var->xres - 1));
1394 wl_mmio(BLT_CLIP_LEFT_RIGHT, clip);
1395 clip = ((0 << 16) | (var->yres - 1));
1396 wl_mmio(BLT_CLIP_TOP_BOTTOM, clip);
1397 wl_mmio(BLT_SRC_BASE, 0); /* seems we need to clear these two */
1398 wl_mmio(BLT_DEST_BASE, 0);
1400 /* Load the video mode defined by the 'var' data */
1402 virgefb_load_video_mode(var);
1407 Merge these two functions, Geert's suggestion.
1408 static int virgefb_set_var(struct fb_var_screeninfo *var, int con, struct fb_info *info);
1409 static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive);
1412 static int virgefb_do_fb_set_var(struct fb_var_screeninfo *var, int isactive)
1415 struct virgefb_par par;
1418 if ((err = fbhw->decode_var(var, &par))) {
1423 activate = var->activate;
1424 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW && isactive)
1425 virgefb_set_par(&par);
1426 fbhw->encode_var(var, &par);
1427 var->activate = activate;
1428 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW && isactive)
1429 virgefb_set_video(var);
1435 static void virgefb_do_install_cmap(int con, struct fb_info *info)
1438 if (con != currcon) {
1439 DPRINTK("EXIT - Not current console\n");
1442 if (fb_display[con].cmap.len) {
1443 DPRINTK("Use console cmap\n");
1444 fb_set_cmap(&fb_display[con].cmap, 1, fbhw->setcolreg, info);
1446 DPRINTK("Use default cmap\n");
1447 fb_set_cmap(fb_default_cmap(fb_display[con].var.bits_per_pixel==8 ? 256 : 16),
1448 1, fbhw->setcolreg, info);
1456 * Get the Fixed Part of the Display
1459 static int virgefb_get_fix(struct fb_fix_screeninfo *fix, int con,
1460 struct fb_info *info)
1462 struct virgefb_par par;
1467 virgefb_get_par(&par);
1469 error = fbhw->decode_var(&fb_display[con].var, &par);
1472 error = fbhw->encode_fix(fix, &par);
1479 * Get the User Defined Part of the Display
1482 static int virgefb_get_var(struct fb_var_screeninfo *var, int con,
1483 struct fb_info *info)
1485 struct virgefb_par par;
1490 virgefb_get_par(&par);
1491 error = fbhw->encode_var(var, &par);
1492 disp.var = *var; /* ++Andre: don't know if this is the right place */
1494 *var = fb_display[con].var;
1500 static void virgefb_set_disp(int con, struct fb_info *info)
1502 struct fb_fix_screeninfo fix;
1503 struct display *display;
1507 display = &fb_display[con];
1509 display = &disp; /* used during initialization */
1511 virgefb_get_fix(&fix, con, info);
1515 display->screen_base = (char*)v_ram;
1517 switch (display->var.bits_per_pixel) {
1518 #ifdef FBCON_HAS_CFB8
1520 display->screen_base = (char*)(v_ram + CYBMEM_OFFSET_8);
1523 #ifdef FBCON_HAS_CFB16
1525 display->screen_base = (char*)(v_ram + CYBMEM_OFFSET_16);
1528 #ifdef FBCON_HAS_CFB32
1530 display->screen_base = (char*)(v_ram + CYBMEM_OFFSET_32);
1535 display->visual = fix.visual;
1536 display->type = fix.type;
1537 display->type_aux = fix.type_aux;
1538 display->ypanstep = fix.ypanstep;
1539 display->ywrapstep = fix.ywrapstep;
1540 display->can_soft_blank = 1;
1541 display->inverse = virgefb_inverse;
1542 display->line_length = display->var.xres_virtual*
1543 display->var.bits_per_pixel/8;
1545 switch (display->var.bits_per_pixel) {
1546 #ifdef FBCON_HAS_CFB8
1548 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1549 display->dispsw = &fbcon_virge8;
1550 #warning FIXME: We should reinit the graphics engine here
1552 display->dispsw = &fbcon_cfb8;
1555 #ifdef FBCON_HAS_CFB16
1557 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1558 display->dispsw = &fbcon_virge16;
1560 display->dispsw = &fbcon_cfb16;
1561 display->dispsw_data = &fbcon_cmap.cfb16;
1564 #ifdef FBCON_HAS_CFB32
1566 if (display->var.accel_flags & FB_ACCELF_TEXT) {
1567 display->dispsw = &fbcon_virge32;
1569 display->dispsw = &fbcon_cfb32;
1570 display->dispsw_data = &fbcon_cmap.cfb32;
1574 display->dispsw = &fbcon_dummy;
1577 DPRINTK("EXIT v_ram virt = 0x%8.8lx\n",(unsigned long)display->screen_base);
1582 * Set the User Defined Part of the Display
1585 static int virgefb_set_var(struct fb_var_screeninfo *var, int con,
1586 struct fb_info *info)
1588 int err, oldxres, oldyres, oldvxres, oldvyres, oldbpp, oldaccel;
1592 if ((err = virgefb_do_fb_set_var(var, con == currcon))) {
1596 if ((var->activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW) {
1597 oldxres = fb_display[con].var.xres;
1598 oldyres = fb_display[con].var.yres;
1599 oldvxres = fb_display[con].var.xres_virtual;
1600 oldvyres = fb_display[con].var.yres_virtual;
1601 oldbpp = fb_display[con].var.bits_per_pixel;
1602 oldaccel = fb_display[con].var.accel_flags;
1603 fb_display[con].var = *var;
1604 if (oldxres != var->xres || oldyres != var->yres ||
1605 oldvxres != var->xres_virtual ||
1606 oldvyres != var->yres_virtual ||
1607 oldbpp != var->bits_per_pixel ||
1608 oldaccel != var->accel_flags) {
1609 virgefb_set_disp(con, info);
1610 if (fb_info.changevar)
1611 (*fb_info.changevar)(con);
1612 fb_alloc_cmap(&fb_display[con].cmap, 0, 0);
1613 virgefb_do_install_cmap(con, info);
1626 static int virgefb_get_cmap(struct fb_cmap *cmap, int kspc, int con,
1627 struct fb_info *info)
1630 if (con == currcon) { /* current console? */
1631 DPRINTK("EXIT - console is current console, fb_get_cmap\n");
1632 return(fb_get_cmap(cmap, kspc, fbhw->getcolreg, info));
1633 } else if (fb_display[con].cmap.len) { /* non default colormap? */
1634 DPRINTK("Use console cmap\n");
1635 fb_copy_cmap(&fb_display[con].cmap, cmap, kspc ? 0 : 2);
1637 DPRINTK("Use default cmap\n");
1638 fb_copy_cmap(fb_default_cmap(fb_display[con].var.bits_per_pixel==8 ? 256 : 16),
1639 cmap, kspc ? 0 : 2);
1650 static int virgefb_set_cmap(struct fb_cmap *cmap, int kspc, int con,
1651 struct fb_info *info)
1656 if (!fb_display[con].cmap.len) { /* no colormap allocated? */
1657 if ((err = fb_alloc_cmap(&fb_display[con].cmap,
1658 (fb_display[con].var.bits_per_pixel==8 ? 256 : 16), 0))) {
1659 DPRINTK("EXIT - fb_alloc_cmap failed\n");
1663 if (con == currcon) { /* current console? */
1664 DPRINTK("EXIT - Current console, fb_set_cmap()\n");
1665 return(fb_set_cmap(cmap, kspc, fbhw->setcolreg, info));
1667 DPRINTK(" Not current console, fb_copy_cmap()\n");
1668 fb_copy_cmap(cmap, &fb_display[con].cmap, kspc ? 0 : 1);
1675 static struct fb_ops virgefb_ops = {
1677 fb_get_fix: virgefb_get_fix,
1678 fb_get_var: virgefb_get_var,
1679 fb_set_var: virgefb_set_var,
1680 fb_get_cmap: virgefb_get_cmap,
1681 fb_set_cmap: virgefb_set_cmap,
1685 int __init virgefb_setup(char *options)
1688 fb_info.fontname[0] = '\0';
1691 if (!options || !*options) {
1696 while ((this_opt = strsep(&options, ",")) != NULL) {
1699 if (!strcmp(this_opt, "inverse")) {
1700 virgefb_inverse = 1;
1702 } else if (!strncmp(this_opt, "font:", 5))
1703 strcpy(fb_info.fontname, this_opt+5);
1704 #ifdef FBCON_HAS_CFB8
1705 else if (!strcmp (this_opt, "virge8")){
1706 virgefb_default = virgefb_predefined[VIRGE8_DEFMODE].var;
1709 #ifdef FBCON_HAS_CFB16
1710 else if (!strcmp (this_opt, "virge16")){
1711 virgefb_default = virgefb_predefined[VIRGE16_DEFMODE].var;
1714 #ifdef FBCON_HAS_CFB32
1715 else if (!strcmp (this_opt, "virge32")){
1716 virgefb_default = virgefb_predefined[VIRGE32_DEFMODE].var;
1720 virgefb_get_video_mode(this_opt);
1723 printk(KERN_INFO "mode : xres=%d, yres=%d, bpp=%d\n", virgefb_default.xres,
1724 virgefb_default.yres, virgefb_default.bits_per_pixel);
1734 static int __init virgefb_get_video_mode(const char *name)
1739 for (i = 0; i < NUM_TOTAL_MODES; i++) {
1740 if (!strcmp(name, virgefb_predefined[i].name)) {
1741 virgefb_default = virgefb_predefined[i].var;
1746 /* ++Andre: set virgefb default mode */
1748 /* prefer 16 bit depth, 8 if no 16, if no 8 or 16 use 32 */
1750 #ifdef FBCON_HAS_CFB32
1751 virgefb_default = virgefb_predefined[VIRGE32_DEFMODE].var;
1753 #ifdef FBCON_HAS_CFB8
1754 virgefb_default = virgefb_predefined[VIRGE8_DEFMODE].var;
1756 #ifdef FBCON_HAS_CFB16
1757 virgefb_default = virgefb_predefined[VIRGE16_DEFMODE].var;
1767 int __init virgefb_init(void)
1769 struct virgefb_par par;
1770 unsigned long board_addr, board_size;
1771 struct zorro_dev *z = NULL;
1775 z = zorro_find_device(ZORRO_PROD_PHASE5_CYBERVISION64_3D, NULL);
1779 board_addr = z->resource.start;
1780 if (board_addr < 0x01000000) {
1782 /* board running in Z2 space. This includes the video memory
1783 as well as the S3 register set */
1786 board_size = 0x00400000;
1788 if (!request_mem_region(board_addr, board_size, "S3 ViRGE"))
1791 v_ram_phys = board_addr;
1792 v_ram = ZTWO_VADDR(v_ram_phys);
1793 mmio_regs_phys = (unsigned long)(board_addr + 0x003c0000);
1794 vgaio_regs = (unsigned char *) ZTWO_VADDR(board_addr + 0x003c0000);
1795 mmio_regs = (unsigned char *)ZTWO_VADDR(mmio_regs_phys);
1796 vcode_switch_base = (unsigned long) ZTWO_VADDR(board_addr + 0x003a0000);
1797 printk(KERN_INFO "CV3D detected running in Z2 mode.\n");
1801 /* board running in Z3 space. Seperate video memory (3 apertures)
1802 and S3 register set */
1805 board_size = 0x01000000;
1807 if (!request_mem_region(board_addr, board_size, "S3 ViRGE"))
1810 v_ram_phys = board_addr + 0x04000000;
1811 v_ram = (unsigned long)ioremap(v_ram_phys, 0x01000000);
1812 mmio_regs_phys = board_addr + 0x05000000;
1813 vgaio_regs = (unsigned char *)ioremap(board_addr +0x0c000000, 0x00100000); /* includes PCI regs */
1814 mmio_regs = ioremap(mmio_regs_phys, 0x00010000);
1815 vcode_switch_base = (unsigned long)ioremap(board_addr + 0x08000000, 0x1000);
1816 printk(KERN_INFO "CV3D detected running in Z3 mode\n");
1819 #if defined (VIRGEFBDEBUG)
1820 DPRINTK("board_addr : 0x%8.8lx\n",board_addr);
1821 DPRINTK("board_size : 0x%8.8lx\n",board_size);
1822 DPRINTK("mmio_regs_phy : 0x%8.8lx\n",mmio_regs_phys);
1823 DPRINTK("v_ram_phys : 0x%8.8lx\n",v_ram_phys);
1824 DPRINTK("vgaio_regs : 0x%8.8lx\n",(unsigned long)vgaio_regs);
1825 DPRINTK("mmio_regs : 0x%8.8lx\n",(unsigned long)mmio_regs);
1826 DPRINTK("v_ram : 0x%8.8lx\n",v_ram);
1827 DPRINTK("vcode sw base : 0x%8.8lx\n",vcode_switch_base);
1829 fbhw = &virgefb_hw_switch;
1830 strcpy(fb_info.modename, virgefb_name);
1831 fb_info.changevar = NULL;
1833 fb_info.fbops = &virgefb_ops;
1834 fb_info.disp = &disp;
1835 fb_info.switch_con = &virgefb_switch;
1836 fb_info.updatevar = &virgefb_updatevar;
1837 fb_info.blank = &virgefb_blank;
1838 fb_info.flags = FBINFO_FLAG_DEFAULT;
1840 fbhw->decode_var(&virgefb_default, &par);
1841 fbhw->encode_var(&virgefb_default, &par);
1842 virgefb_do_fb_set_var(&virgefb_default, 1);
1843 virgefb_get_var(&fb_display[0].var, -1, &fb_info);
1844 virgefb_set_disp(-1, &fb_info);
1845 virgefb_do_install_cmap(0, &fb_info);
1847 if (register_framebuffer(&fb_info) < 0) {
1848 #warning release resources
1849 printk(KERN_ERR "virgefb.c: register_framebuffer failed\n");
1854 printk(KERN_INFO "fb%d: %s frame buffer device, using %ldK of video memory\n",
1855 GET_FB_IDX(fb_info.node), fb_info.modename, v_ram_size>>10);
1857 /* TODO: This driver cannot be unloaded yet */
1865 static int virgefb_switch(int con, struct fb_info *info)
1868 /* Do we have to save the colormap? */
1869 if (fb_display[currcon].cmap.len)
1870 fb_get_cmap(&fb_display[currcon].cmap, 1, fbhw->getcolreg, info);
1871 virgefb_do_fb_set_var(&fb_display[con].var, 1);
1873 /* Install new colormap */
1874 virgefb_do_install_cmap(con, info);
1881 * Update the `var' structure (called by fbcon.c)
1883 * This call looks only at yoffset and the FB_VMODE_YWRAP flag in `var'.
1884 * Since it's called by a kernel driver, no range checking is done.
1887 static int virgefb_updatevar(int con, struct fb_info *info)
1895 * Blank the display.
1898 static void virgefb_blank(int blank, struct fb_info *info)
1907 * Text console acceleration
1910 #ifdef FBCON_HAS_CFB8
1911 static void fbcon_virge8_bmove(struct display *p, int sy, int sx, int dy,
1912 int dx, int height, int width)
1914 sx *= 8; dx *= 8; width *= 8;
1915 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
1916 (u_short)(dy*fontheight(p)), (u_short)width,
1917 (u_short)(height*fontheight(p)), (u_short)p->next_line, 8);
1920 static void fbcon_virge8_clear(struct vc_data *conp, struct display *p, int sy,
1921 int sx, int height, int width)
1925 sx *= 8; width *= 8;
1926 bg = attr_bgcol_ec(p,conp);
1927 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
1928 (u_short)width, (u_short)(height*fontheight(p)),
1929 (u_short)bg, (u_short)p->next_line, 8);
1932 static void fbcon_virge8_putc(struct vc_data *conp, struct display *p, int c, int yy,
1935 if (blit_maybe_busy)
1936 virgefb_wait_for_idle();
1937 fbcon_cfb8_putc(conp, p, c, yy, xx);
1940 static void fbcon_virge8_putcs(struct vc_data *conp, struct display *p,
1941 const unsigned short *s, int count, int yy, int xx)
1943 if (blit_maybe_busy)
1944 virgefb_wait_for_idle();
1945 fbcon_cfb8_putcs(conp, p, s, count, yy, xx);
1948 static void fbcon_virge8_revc(struct display *p, int xx, int yy)
1950 if (blit_maybe_busy)
1951 virgefb_wait_for_idle();
1952 fbcon_cfb8_revc(p, xx, yy);
1955 static void fbcon_virge8_clear_margins(struct vc_data *conp, struct display *p,
1958 if (blit_maybe_busy)
1959 virgefb_wait_for_idle();
1960 fbcon_cfb8_clear_margins(conp, p, bottom_only);
1963 static struct display_switch fbcon_virge8 = {
1964 setup: fbcon_cfb8_setup,
1965 bmove: fbcon_virge8_bmove,
1966 clear: fbcon_virge8_clear,
1967 putc: fbcon_virge8_putc,
1968 putcs: fbcon_virge8_putcs,
1969 revc: fbcon_virge8_revc,
1970 clear_margins: fbcon_virge8_clear_margins,
1971 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
1975 #ifdef FBCON_HAS_CFB16
1976 static void fbcon_virge16_bmove(struct display *p, int sy, int sx, int dy,
1977 int dx, int height, int width)
1979 sx *= 8; dx *= 8; width *= 8;
1980 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
1981 (u_short)(dy*fontheight(p)), (u_short)width,
1982 (u_short)(height*fontheight(p)), (u_short)p->next_line, 16);
1985 static void fbcon_virge16_clear(struct vc_data *conp, struct display *p, int sy,
1986 int sx, int height, int width)
1990 sx *= 8; width *= 8;
1991 bg = attr_bgcol_ec(p,conp);
1992 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
1993 (u_short)width, (u_short)(height*fontheight(p)),
1994 (u_short)bg, (u_short)p->next_line, 16);
1997 static void fbcon_virge16_putc(struct vc_data *conp, struct display *p, int c, int yy,
2000 if (blit_maybe_busy)
2001 virgefb_wait_for_idle();
2002 fbcon_cfb16_putc(conp, p, c, yy, xx);
2005 static void fbcon_virge16_putcs(struct vc_data *conp, struct display *p,
2006 const unsigned short *s, int count, int yy, int xx)
2008 if (blit_maybe_busy)
2009 virgefb_wait_for_idle();
2010 fbcon_cfb16_putcs(conp, p, s, count, yy, xx);
2013 static void fbcon_virge16_revc(struct display *p, int xx, int yy)
2015 if (blit_maybe_busy)
2016 virgefb_wait_for_idle();
2017 fbcon_cfb16_revc(p, xx, yy);
2020 static void fbcon_virge16_clear_margins(struct vc_data *conp, struct display *p,
2023 if (blit_maybe_busy)
2024 virgefb_wait_for_idle();
2025 fbcon_cfb16_clear_margins(conp, p, bottom_only);
2028 static struct display_switch fbcon_virge16 = {
2029 setup: fbcon_cfb16_setup,
2030 bmove: fbcon_virge16_bmove,
2031 clear: fbcon_virge16_clear,
2032 putc: fbcon_virge16_putc,
2033 putcs: fbcon_virge16_putcs,
2034 revc: fbcon_virge16_revc,
2035 clear_margins: fbcon_virge16_clear_margins,
2036 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2040 #ifdef FBCON_HAS_CFB32
2041 static void fbcon_virge32_bmove(struct display *p, int sy, int sx, int dy,
2042 int dx, int height, int width)
2044 sx *= 16; dx *= 16; width *= 16; /* doubled these values to do 32 bit blit */
2045 virgefb_BitBLT((u_short)sx, (u_short)(sy*fontheight(p)), (u_short)dx,
2046 (u_short)(dy*fontheight(p)), (u_short)width,
2047 (u_short)(height*fontheight(p)), (u_short)p->next_line, 16);
2050 static void fbcon_virge32_clear(struct vc_data *conp, struct display *p, int sy,
2051 int sx, int height, int width)
2055 sx *= 16; width *= 16; /* doubled these values to do 32 bit blit */
2056 bg = attr_bgcol_ec(p,conp);
2057 virgefb_RectFill((u_short)sx, (u_short)(sy*fontheight(p)),
2058 (u_short)width, (u_short)(height*fontheight(p)),
2059 (u_short)bg, (u_short)p->next_line, 16);
2062 static void fbcon_virge32_putc(struct vc_data *conp, struct display *p, int c, int yy,
2065 if (blit_maybe_busy)
2066 virgefb_wait_for_idle();
2067 fbcon_cfb32_putc(conp, p, c, yy, xx);
2070 static void fbcon_virge32_putcs(struct vc_data *conp, struct display *p,
2071 const unsigned short *s, int count, int yy, int xx)
2073 if (blit_maybe_busy)
2074 virgefb_wait_for_idle();
2075 fbcon_cfb32_putcs(conp, p, s, count, yy, xx);
2078 static void fbcon_virge32_revc(struct display *p, int xx, int yy)
2080 if (blit_maybe_busy)
2081 virgefb_wait_for_idle();
2082 fbcon_cfb32_revc(p, xx, yy);
2085 static void fbcon_virge32_clear_margins(struct vc_data *conp, struct display *p,
2088 if (blit_maybe_busy)
2089 virgefb_wait_for_idle();
2090 fbcon_cfb32_clear_margins(conp, p, bottom_only);
2093 static struct display_switch fbcon_virge32 = {
2094 setup: fbcon_cfb32_setup,
2095 bmove: fbcon_virge32_bmove,
2096 clear: fbcon_virge32_clear,
2097 putc: fbcon_virge32_putc,
2098 putcs: fbcon_virge32_putcs,
2099 revc: fbcon_virge32_revc,
2100 clear_margins: fbcon_virge32_clear_margins,
2101 fontwidthmask: FONTWIDTH(4)|FONTWIDTH(8)|FONTWIDTH(12)|FONTWIDTH(16)
2106 MODULE_LICENSE("GPL");
2108 int init_module(void)
2110 return virgefb_init();
2113 void cleanup_module(void)
2115 /* Not reached because the usecount will never be
2116 decremented to zero */
2117 unregister_framebuffer(&fb_info);
2118 /* TODO: clean up ... */
2122 static int cv3d_has_4mb(void)
2124 /* cyberfb version didn't work, neither does this (not reliably)
2125 forced to return 4MB */
2127 volatile unsigned long *t0, *t2;
2131 /* write patterns in memory and test if they can be read */
2132 t0 = (volatile unsigned long *)v_ram;
2133 t2 = (volatile unsigned long *)(v_ram + 0x00200000);
2137 if (*t0 != 0x87654321) {
2138 /* read of first location failed */
2139 DPRINTK("EXIT - 0MB !\n");
2143 if (*t2 == 0x87654321) {
2144 /* should read 0x12345678 if 4MB */
2145 DPRINTK("EXIT - 2MB(a) \n");
2149 if (*t2 != 0x12345678) {
2150 /* upper 2MB read back match failed */
2151 DPRINTK("EXIT - 2MB(b)\n");
2159 if(*t2 != 0xAAAAAAAA) {
2160 /* upper 2MB read back match failed */
2161 DPRINTK("EXIT - 2MB(c)\n");
2167 if(*t2 != 0x55555555) {
2168 /* upper 2MB read back match failed */
2169 DPRINTK("EXIT - 2MB(d)\n");
2174 DPRINTK("EXIT - 4MB\n");
2180 * Computes M, N, and R pll params for freq arg.
2181 * Returns 16 bits - hi 0MMMMMM lo 0RRNNNNN
2184 #define REFCLOCK 14318000
2186 static unsigned short virgefb_compute_clock(unsigned long freq)
2189 unsigned char m, n, r, rpwr;
2190 unsigned long diff, ftry, save = ~0UL;
2195 for (r = 0, rpwr = 1 ; r < 4 ; r++, rpwr *= 2) {
2196 if ((135000000 <= (rpwr * freq)) && ((rpwr * freq) <= 270000000)) {
2197 for (n = 1 ; n < 32 ; n++) {
2198 m = ((freq * (n + 2) * rpwr)/REFCLOCK) - 2;
2199 if (m == 0 || m >127)
2201 ftry = ((REFCLOCK / (n + 2)) * (m + 2)) / rpwr;
2208 mnr = (m << 8) | (r<<5) | (n & 0x7f);
2214 printk("Can't compute clock PLL values for %ld Hz clock\n", freq);
2219 static void virgefb_load_video_mode(struct fb_var_screeninfo *video_mode)
2221 unsigned char lace, dblscan, tmp;
2223 unsigned short HT, HDE, HBS, HBW, HSS, HSW;
2224 unsigned short VT, VDE, VBS, VBW, VSS, VSW;
2229 int xres, xres_virtual, hfront, hsync, hback;
2230 int yres, vfront, vsync, vback;
2235 DPRINTK("ENTER : %dx%d-%d\n",video_mode->xres, video_mode->yres,
2236 video_mode->bits_per_pixel);
2238 bpp = video_mode->bits_per_pixel;
2239 xres = video_mode->xres;
2240 xres_virtual = video_mode->xres_virtual;
2241 hfront = video_mode->right_margin;
2242 hsync = video_mode->hsync_len;
2243 hback = video_mode->left_margin;
2248 if (video_mode->vmode & FB_VMODE_DOUBLE) {
2249 yres = video_mode->yres * 2;
2250 vfront = video_mode->lower_margin * 2;
2251 vsync = video_mode->vsync_len * 2;
2252 vback = video_mode->upper_margin * 2;
2254 } else if (video_mode->vmode & FB_VMODE_INTERLACED) {
2255 yres = (video_mode->yres + 1) / 2;
2256 vfront = (video_mode->lower_margin + 1) / 2;
2257 vsync = (video_mode->vsync_len + 1) / 2;
2258 vback = (video_mode->upper_margin + 1) / 2;
2261 yres = video_mode->yres;
2262 vfront = video_mode->lower_margin;
2263 vsync = video_mode->vsync_len;
2264 vback = video_mode->upper_margin;
2269 video_mode->red.offset = 0;
2270 video_mode->green.offset = 0;
2271 video_mode->blue.offset = 0;
2272 video_mode->transp.offset = 0;
2273 video_mode->red.length = 8;
2274 video_mode->green.length = 8;
2275 video_mode->blue.length = 8;
2276 video_mode->transp.length = 0;
2279 SCO = xres_virtual / 8;
2282 video_mode->red.offset = 11;
2283 video_mode->green.offset = 5;
2284 video_mode->blue.offset = 0;
2285 video_mode->transp.offset = 0;
2286 video_mode->red.length = 5;
2287 video_mode->green.length = 6;
2288 video_mode->blue.length = 5;
2289 video_mode->transp.length = 0;
2292 SCO = xres_virtual / 4;
2295 video_mode->red.offset = 16;
2296 video_mode->green.offset = 8;
2297 video_mode->blue.offset = 0;
2298 video_mode->transp.offset = 24;
2299 video_mode->red.length = 8;
2300 video_mode->green.length = 8;
2301 video_mode->blue.length = 8;
2302 video_mode->transp.length = 8;
2305 SCO = xres_virtual / 2;
2309 HT = (((xres + hfront + hsync + hback) / 8) * hmul) - 5;
2310 HDE = ((xres / 8) * hmul) - 1;
2311 HBS = (xres / 8) * hmul;
2312 HSS = ((xres + hfront) / 8) * hmul;
2313 HSW = (hsync / 8) * hmul;
2314 HBW = (((hfront + hsync + hback) / 8) * hmul) - 2;
2316 VT = yres + vfront + vsync + vback - 2;
2319 VSS = yres + vfront;
2321 VBW = vfront + vsync + vback - 2;
2324 DPRINTK("HDE : 0x%4.4x, %4.4d\n", HDE, HDE);
2325 DPRINTK("HBS : 0x%4.4x, %4.4d\n", HBS, HBS);
2326 DPRINTK("HSS : 0x%4.4x, %4.4d\n", HSS, HSS);
2327 DPRINTK("HSW : 0x%4.4x, %4.4d\n", HSW, HSW);
2328 DPRINTK("HBW : 0x%4.4x, %4.4d\n", HBW, HBW);
2329 DPRINTK("HSS + HSW : 0x%4.4x, %4.4d\n", HSS+HSW, HSS+HSW);
2330 DPRINTK("HBS + HBW : 0x%4.4x, %4.4d\n", HBS+HBW, HBS+HBW);
2331 DPRINTK("HT : 0x%4.4x, %4.4d\n", HT, HT);
2332 DPRINTK("VDE : 0x%4.4x, %4.4d\n", VDE, VDE);
2333 DPRINTK("VBS : 0x%4.4x, %4.4d\n", VBS, VBS);
2334 DPRINTK("VSS : 0x%4.4x, %4.4d\n", VSS, VSS);
2335 DPRINTK("VSW : 0x%4.4x, %4.4d\n", VSW, VSW);
2336 DPRINTK("VBW : 0x%4.4x, %4.4d\n", VBW, VBW);
2337 DPRINTK("VT : 0x%4.4x, %4.4d\n", VT, VT);
2340 /* turn gfx off, don't mess up the display */
2344 /* H and V sync polarity */
2346 tmp = rb_mmio(GREG_MISC_OUTPUT_R) & 0x2f; /* colour, ram enable, clk sr12/s13 sel */
2347 if (!(video_mode->sync & FB_SYNC_HOR_HIGH_ACT))
2348 tmp |= 0x40; /* neg H sync polarity */
2349 if (!(video_mode->sync & FB_SYNC_VERT_HIGH_ACT))
2350 tmp |= 0x80; /* neg V sync polarity */
2351 tmp |= 0x0c; /* clk from sr12/sr13 */
2352 wb_mmio(GREG_MISC_OUTPUT_W, tmp);
2356 wseq(SEQ_ID_BUS_REQ_CNTL, 0xc0); /* 2 clk mem wr and /RAS1 */
2357 wseq(SEQ_ID_CLKSYN_CNTL_2, 0x80); /* b7 is 2 mem clk wr */
2358 mnr = virgefb_compute_clock(MEMCLOCK);
2359 DPRINTK("mem clock %d, m %d, n %d, r %d.\n", MEMCLOCK, ((mnr>>8)&0x7f), (mnr&0x1f), ((mnr >> 5)&0x03));
2360 wseq(SEQ_ID_MCLK_LO, (mnr & 0x7f));
2361 wseq(SEQ_ID_MCLK_HI, ((mnr & 0x7f00) >> 8));
2362 freq = (1000000000 / video_mode->pixclock) * 1000; /* pixclock is in ps ... convert to Hz */
2363 mnr = virgefb_compute_clock(freq);
2364 DPRINTK("dot clock %ld, m %d, n %d, r %d.\n", freq, ((mnr>>8)&0x7f), (mnr&0x1f), ((mnr>>5)&0x03));
2365 wseq(SEQ_ID_DCLK_LO, (mnr & 0x7f));
2366 wseq(SEQ_ID_DCLK_HI, ((mnr & 0x7f00) >> 8));
2367 wseq(SEQ_ID_CLKSYN_CNTL_2, 0xa0);
2368 wseq(SEQ_ID_CLKSYN_CNTL_2, 0x80);
2371 /* load display parameters into board */
2373 /* not sure about sync and blanking extensions bits in cr5d and cr5 */
2375 wcrt(CRT_ID_EXT_HOR_OVF, /* 0x5d */
2376 ((HT & 0x100) ? 0x01 : 0x00) |
2377 ((HDE & 0x100) ? 0x02 : 0x00) |
2378 ((HBS & 0x100) ? 0x04 : 0x00) |
2379 /* (((HBS + HBW) & 0x40) ? 0x08 : 0x00) | */
2380 ((HSS & 0x100) ? 0x10 : 0x00) |
2381 /* (((HSS + HSW) & 0x20) ? 0x20 : 0x00) | */
2382 ((HSW >= 0x20) ? 0x20 : 0x00) |
2383 (((HT-5) & 0x100) ? 0x40 : 0x00));
2385 wcrt(CRT_ID_EXT_VER_OVF, /* 0x5e */
2386 ((VT & 0x400) ? 0x01 : 0x00) |
2387 ((VDE & 0x400) ? 0x02 : 0x00) |
2388 ((VBS & 0x400) ? 0x04 : 0x00) |
2389 ((VSS & 0x400) ? 0x10 : 0x00) |
2390 0x40); /* line compare */
2392 wcrt(CRT_ID_START_VER_RETR, VSS);
2393 cr11 = rcrt(CRT_ID_END_VER_RETR) | 0x20; /* vert interrupt flag */
2394 wcrt(CRT_ID_END_VER_RETR, ((cr11 & 0x20) | ((VSS + VSW) & 0x0f))); /* keeps vert irq enable state, also has unlock bit cr0 to 7 */
2395 wcrt(CRT_ID_VER_DISP_ENA_END, VDE);
2396 wcrt(CRT_ID_START_VER_BLANK, VBS);
2397 wcrt(CRT_ID_END_VER_BLANK, VBS + VBW); /* might be +/- 1 out */
2398 wcrt(CRT_ID_HOR_TOTAL, HT);
2399 wcrt(CRT_ID_DISPLAY_FIFO, HT - 5);
2400 wcrt(CRT_ID_BACKWAD_COMP_3, 0x10); /* enable display fifo */
2401 wcrt(CRT_ID_HOR_DISP_ENA_END, HDE);
2402 wcrt(CRT_ID_START_HOR_BLANK , HBS);
2403 wcrt(CRT_ID_END_HOR_BLANK, (HBS + HBW) & 0x1f);
2404 wcrt(CRT_ID_START_HOR_RETR, HSS);
2405 wcrt(CRT_ID_END_HOR_RETR, /* cr5 */
2406 ((HSS + HSW) & 0x1f) |
2407 (((HBS + HBW) & 0x20) ? 0x80 : 0x00));
2408 wcrt(CRT_ID_VER_TOTAL, VT);
2409 wcrt(CRT_ID_OVERFLOW,
2410 ((VT & 0x100) ? 0x01 : 0x00) |
2411 ((VDE & 0x100) ? 0x02 : 0x00) |
2412 ((VSS & 0x100) ? 0x04 : 0x00) |
2413 ((VBS & 0x100) ? 0x08 : 0x00) |
2415 ((VT & 0x200) ? 0x20 : 0x00) |
2416 ((VDE & 0x200) ? 0x40 : 0x00) |
2417 ((VSS & 0x200) ? 0x80 : 0x00));
2418 wcrt(CRT_ID_MAX_SCAN_LINE,
2419 (dblscan ? 0x80 : 0x00) |
2421 ((VBS & 0x200) ? 0x20 : 0x00));
2422 wcrt(CRT_ID_LINE_COMPARE, 0xff);
2423 wcrt(CRT_ID_LACE_RETR_START, HT / 2); /* (HT-5)/2 ? */
2424 wcrt(CRT_ID_LACE_CONTROL, (lace ? 0x20 : 0x00));
2426 wcrt(CRT_ID_SCREEN_OFFSET, SCO);
2427 wcrt(CRT_ID_EXT_SYS_CNTL_2, (SCO >> 4) & 0x30 );
2429 /* wait for vert sync before cr67 update */
2431 for (i=0; i < 10000; i++) {
2434 if (rb_mmio(GREG_INPUT_STATUS1_R) & 0x08)
2438 wl_mmio(0x8200, 0x0000c000); /* fifo control (0x00110400 ?) */
2439 wcrt(CRT_ID_EXT_MISC_CNTL_2, cr67);
2443 tmp = rb_mmio(ACT_ADDRESS_RESET);
2444 wb_mmio(ACT_ADDRESS_W, ((bpp == 8) ? 0x20 : 0x00)); /* set b5, ENB PLT in attr idx reg) */
2445 tmp = rb_mmio(ACT_ADDRESS_RESET);
2447 /* turn gfx on again */
2453 SetVSwitch(1); /* cv3d */
2459 static inline void gfx_on_off(int toggle)
2463 DPRINTK("ENTER gfx %s\n", (toggle ? "off" : "on"));
2465 toggle = (toggle & 0x01) << 5;
2466 tmp = rseq(SEQ_ID_CLOCKING_MODE) & (~(0x01 << 5));
2467 wseq(SEQ_ID_CLOCKING_MODE, tmp | toggle);
2472 #if defined (VIRGEFBDUMP)
2475 * Dump board registers
2478 static void cv64_dump(void)
2485 /* crt, seq, gfx and atr regs */
2490 for (i = 0; i <= 0x6f; i++) {
2491 wb_mmio(CRT_ADDRESS, i);
2492 printk("crt idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(CRT_ADDRESS_R));
2494 for (i = 0; i <= 0x1c; i++) {
2495 wb_mmio(SEQ_ADDRESS, i);
2496 printk("seq idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(SEQ_ADDRESS_R));
2498 for (i = 0; i <= 8; i++) {
2499 wb_mmio(GCT_ADDRESS, i);
2500 printk("gfx idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(GCT_ADDRESS_R));
2502 for (i = 0; i <= 0x14; i++) {
2503 c = rb_mmio(ACT_ADDRESS_RESET);
2504 wb_mmio(ACT_ADDRESS_W, i);
2505 printk("atr idx : 0x%2.2x : 0x%2.2x\n", i, rb_mmio(ACT_ADDRESS_R));
2508 /* re-enable video access to palette */
2510 c = rb_mmio(ACT_ADDRESS_RESET);
2512 wb_mmio(ACT_ADDRESS_W, 0x20);
2513 c = rb_mmio(ACT_ADDRESS_RESET);
2518 printk("0x3cc(w 0x3c2) : 0x%2.2x\n", rb_mmio(0x3cc)); /* GREG_MISC_OUTPUT READ */
2519 printk("0x3c2(-------) : 0x%2.2x\n", rb_mmio(0x3c2)); /* GREG_INPUT_STATUS 0 READ */
2520 printk("0x3c3(w 0x3c3) : 0x%2.2x\n", rb_vgaio(0x3c3)); /* GREG_VIDEO_SUBS_ENABLE */
2521 printk("0x3ca(w 0x3da) : 0x%2.2x\n", rb_vgaio(0x3ca)); /* GREG_FEATURE_CONTROL read */
2522 printk("0x3da(-------) : 0x%2.2x\n", rb_mmio(0x3da)); /* GREG_INPUT_STATUS 1 READ */
2526 for (i = 0x8180; i <= 0x8200; i = i + 4)
2527 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2530 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2532 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2533 for (i = 0xa4d4; i <= 0xa50c; i = i + 4)
2534 printk("0x%8.8x : 0x%8.8x\n", i, rl_mmio(i));
2540 for (c = 0; c < 0x08; c = c + 2) {
2541 w = (*((u16 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 2)));
2542 printk("pci 0x%2.2x : 0x%4.4x\n", c, w);
2545 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2546 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2548 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2549 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2551 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2552 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2554 l = (*((u32 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)))));
2555 printk("pci 0x%2.2x : 0x%8.8x\n", c, l);
2557 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2558 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2560 b = (*((u8 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 3)));
2561 printk("pci 0x%2.2x : 0x%2.2x\n", c, b);
2563 w = (*((u16 *)((u32)(vgaio_regs + c + (on_zorro2 ? 0 : 0x000e0000)) ^ 2)));
2564 printk("pci 0x%2.2x : 0x%4.4x\n", c, w);