include/asm-arm/arch-at91rm9200/at91rm9200dk.h

   1 /*
   2  * linux/include/asm-arm/arch-at91rm9200/at91rm9200dk.h
   3  *
   4  *  Copyright (c) 2003 SAN People
   5  *  Copyright (c) 2003 ATMEL
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License, or
  10  * (at your option) any later version.
  11  *
  12  */
  13
  14 #ifndef __ASM_ARCH_HARDWARE_AT91RM9200DK_H
  15 #define __ASM_ARCH_HARDWARE_AT91RM9200DK_H
  16
  17
  18 /* AT91RM92000 clocks */
  19 #define AT91C_MAIN_CLOCK        179712000       /* from 18.432 MHz crystal (18432000 / 4 * 39) */
  20 #define AT91C_MASTER_CLOCK      59904000        /* peripheral clock (AT91C_MASTER_CLOCK / 3) */
  21 #define AT91C_SLOW_CLOCK        32768           /* slow clock */
  22
  23
  24 /* FLASH */
  25 #define AT91_FLASH_BASE         0x10000000      // NCS0: Flash physical base address
  26
  27 /* SDRAM */
  28 #define AT91_SDRAM_BASE         0x20000000      // NCS1: SDRAM physical base address
  29
  30 /* SmartMedia */
  31 #define AT91_SMARTMEDIA_BASE    0x40000000      // NCS3: Smartmedia physical base address
  32
  33 /* Multi-Master Memory controller */
  34 #define AT91_UHP_BASE           0x00300000      // USB Host controller
  35
  36
  37 /* Peripheral interrupt configuration */
  38 #define AT91_SMR_FIQ    (AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (FIQ)
  39 #define AT91_SMR_SYS    (AT91C_AIC_PRIOR_HIGHEST | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // System Peripheral
  40 #define AT91_SMR_PIOA   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Parallel IO Controller A
  41 #define AT91_SMR_PIOB   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Parallel IO Controller B
  42 #define AT91_SMR_PIOC   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Parallel IO Controller C
  43 #define AT91_SMR_PIOD   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Parallel IO Controller D
  44 #define AT91_SMR_US0    (AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // USART 0
  45 #define AT91_SMR_US1    (AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // USART 1
  46 #define AT91_SMR_US2    (AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // USART 2
  47 #define AT91_SMR_US3    (AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // USART 3
  48 #define AT91_SMR_MCI    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Multimedia Card Interface
  49 #define AT91_SMR_UDP    (AT91C_AIC_PRIOR_4       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // USB Device Port
  50 #define AT91_SMR_TWI    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Two-Wire Interface
  51 #define AT91_SMR_SPI    (AT91C_AIC_PRIOR_6       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Serial Peripheral Interface
  52 #define AT91_SMR_SSC0   (AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Serial Synchronous Controller 0
  53 #define AT91_SMR_SSC1   (AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Serial Synchronous Controller 1
  54 #define AT91_SMR_SSC2   (AT91C_AIC_PRIOR_5       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Serial Synchronous Controller 2
  55 #define AT91_SMR_TC0    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Timer Counter 0
  56 #define AT91_SMR_TC1    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Timer Counter 1
  57 #define AT91_SMR_TC2    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Timer Counter 2
  58 #define AT91_SMR_TC3    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Timer Counter 3
  59 #define AT91_SMR_TC4    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Timer Counter 4
  60 #define AT91_SMR_TC5    (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Timer Counter 5
  61 #define AT91_SMR_UHP    (AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // USB Host port
  62 #define AT91_SMR_EMAC   (AT91C_AIC_PRIOR_3       | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Ethernet MAC
  63 #define AT91_SMR_IRQ0   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (IRQ0)
  64 #define AT91_SMR_IRQ1   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (IRQ1)
  65 #define AT91_SMR_IRQ2   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (IRQ2)
  66 #define AT91_SMR_IRQ3   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (IRQ3)
  67 #define AT91_SMR_IRQ4   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (IRQ4)
  68 #define AT91_SMR_IRQ5   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (IRQ5)
  69 #define AT91_SMR_IRQ6   (AT91C_AIC_PRIOR_LOWEST  | AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE)       // Advanced Interrupt Controller (IRQ6)
  70
  71
  72 /*
  73  * Serial port configuration.
  74  *    0 .. 3 = USART0 .. USART3
  75  *    4      = DBGU
  76  */
  77 #define AT91C_UART_MAP          { 4, 1, -1, -1, -1 }    /* ttyS0, ..., ttyS4 */
  78 #define AT91C_CONSOLE           0                       /* ttyS0 */
  79
  80 #endif