2 * This program is free software; you can redistribute it and/or modify
3 * it under the terms of the GNU General Public License as published by
4 * the Free Software Foundation; either version 2 of the License, or
5 * (at your option) any later version.
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
12 * You should have received a copy of the GNU General Public License
13 * along with this program; if not, write to the Free Software
14 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 * Copyright (C) 2002 Shane Nay (shane@minirl.com)
21 /**************************************************************************
22 * * Copyright © ARM Limited 1998. All rights reserved.
23 * ***********************************************************************/
24 /* ************************************************************************
28 * ***********************************************************************/
31 /* ========================================================================
33 * ========================================================================
34 * ------------------------------------------------------------------------
36 * ------------------------------------------------------------------------
41 #ifndef __MX1ADS_PLATFORM_H__
42 #define __MX1ADS_PLATFORM_H__
45 #define MX1ADS_SRAM_BASE 0x00300000
46 #define MX1ADS_SRAM_SIZE SZ_128K
48 #define MX1ADS_SFLASH_BASE 0x0C000000
49 #define MX1ADS_SFLASH_SIZE SZ_16M
51 #define MX1ADS_IO_BASE 0x00200000
52 #define MX1ADS_IO_SIZE SZ_256K
54 #define MX1ADS_VID_BASE 0x00300000
55 #define MX1ADS_VID_SIZE 0x26000
57 #define MX1ADS_VID_START IO_ADDRESS(MX1ADS_VID_BASE)
60 /* ------------------------------------------------------------------------
61 * Motorola MX1 system registers
62 * ------------------------------------------------------------------------
71 #define MX1ADS_AIPI1_OFFSET 0x00000
72 #define MX1ADS_WDT_OFFSET 0x01000
73 #define MX1ADS_TIM1_OFFSET 0x02000
74 #define MX1ADS_TIM2_OFFSET 0x03000
75 #define MX1ADS_RTC_OFFSET 0x04000
76 #define MX1ADS_LCDC_OFFSET 0x05000
77 #define MX1ADS_UART1_OFFSET 0x06000
78 #define MX1ADS_UART2_OFFSET 0x07000
79 #define MX1ADS_PWM_OFFSET 0x08000
80 #define MX1ADS_DMAC_OFFSET 0x09000
81 #define MX1ADS_AIPI2_OFFSET 0x10000
82 #define MX1ADS_SIM_OFFSET 0x11000
83 #define MX1ADS_USBD_OFFSET 0x12000
84 #define MX1ADS_SPI1_OFFSET 0x13000
85 #define MX1ADS_MMC_OFFSET 0x14000
86 #define MX1ADS_ASP_OFFSET 0x15000
87 #define MX1ADS_BTA_OFFSET 0x16000
88 #define MX1ADS_I2C_OFFSET 0x17000
89 #define MX1ADS_SSI_OFFSET 0x18000
90 #define MX1ADS_SPI2_OFFSET 0x19000
91 #define MX1ADS_MSHC_OFFSET 0x1A000
92 #define MX1ADS_PLL_OFFSET 0x1B000
93 #define MX1ADS_GPIO_OFFSET 0x1C000
94 #define MX1ADS_EIM_OFFSET 0x20000
95 #define MX1ADS_SDRAMC_OFFSET 0x21000
96 #define MX1ADS_MMA_OFFSET 0x22000
97 #define MX1ADS_AITC_OFFSET 0x23000
98 #define MX1ADS_CSI_OFFSET 0x24000
102 * Register BASEs, based on OFFSETs
106 #define MX1ADS_AIPI1_BASE (MX1ADS_AIPI1_OFFSET + MX1ADS_IO_BASE)
107 #define MX1ADS_WDT_BASE (MX1ADS_WDT_OFFSET + MX1ADS_IO_BASE)
108 #define MX1ADS_TIM1_BASE (MX1ADS_TIM1_OFFSET + MX1ADS_IO_BASE)
109 #define MX1ADS_TIM2_BASE (MX1ADS_TIM2_OFFSET + MX1ADS_IO_BASE)
110 #define MX1ADS_RTC_BASE (MX1ADS_RTC_OFFSET + MX1ADS_IO_BASE)
111 #define MX1ADS_LCDC_BASE (MX1ADS_LCDC_OFFSET + MX1ADS_IO_BASE)
112 #define MX1ADS_UART1_BASE (MX1ADS_UART1_OFFSET + MX1ADS_IO_BASE)
113 #define MX1ADS_UART2_BASE (MX1ADS_UART2_OFFSET + MX1ADS_IO_BASE)
114 #define MX1ADS_PWM_BASE (MX1ADS_PWM_OFFSET + MX1ADS_IO_BASE)
115 #define MX1ADS_DMAC_BASE (MX1ADS_DMAC_OFFSET + MX1ADS_IO_BASE)
116 #define MX1ADS_AIPI2_BASE (MX1ADS_AIPI2_OFFSET + MX1ADS_IO_BASE)
117 #define MX1ADS_SIM_BASE (MX1ADS_SIM_OFFSET + MX1ADS_IO_BASE)
118 #define MX1ADS_USBD_BASE (MX1ADS_USBD_OFFSET + MX1ADS_IO_BASE)
119 #define MX1ADS_SPI1_BASE (MX1ADS_SPI1_OFFSET + MX1ADS_IO_BASE)
120 #define MX1ADS_MMC_BASE (MX1ADS_MMC_OFFSET + MX1ADS_IO_BASE)
121 #define MX1ADS_ASP_BASE (MX1ADS_ASP_OFFSET + MX1ADS_IO_BASE)
122 #define MX1ADS_BTA_BASE (MX1ADS_BTA_OFFSET + MX1ADS_IO_BASE)
123 #define MX1ADS_I2C_BASE (MX1ADS_I2C_OFFSET + MX1ADS_IO_BASE)
124 #define MX1ADS_SSI_BASE (MX1ADS_SSI_OFFSET + MX1ADS_IO_BASE)
125 #define MX1ADS_SPI2_BASE (MX1ADS_SPI2_OFFSET + MX1ADS_IO_BASE)
126 #define MX1ADS_MSHC_BASE (MX1ADS_MSHC_OFFSET + MX1ADS_IO_BASE)
127 #define MX1ADS_PLL_BASE (MX1ADS_PLL_OFFSET + MX1ADS_IO_BASE)
128 #define MX1ADS_GPIO_BASE (MX1ADS_GPIO_OFFSET + MX1ADS_IO_BASE)
129 #define MX1ADS_EIM_BASE (MX1ADS_EIM_OFFSET + MX1ADS_IO_BASE)
130 #define MX1ADS_SDRAMC_BASE (MX1ADS_SDRAMC_OFFSET + MX1ADS_IO_BASE)
131 #define MX1ADS_MMA_BASE (MX1ADS_MMA_OFFSET + MX1ADS_IO_BASE)
132 #define MX1ADS_AITC_BASE (MX1ADS_AITC_OFFSET + MX1ADS_IO_BASE)
133 #define MX1ADS_CSI_BASE (MX1ADS_CSI_OFFSET + MX1ADS_IO_BASE)
137 * MX1 Interrupt numbers
140 #define INT_SOFTINT 0
142 #define DSPA_MAC_INT 7
146 #define GPIO_INT_PORTA 11
147 #define GPIO_INT_PORTB 12
148 #define GPIO_INT_PORTC 13
151 #define SIM_DATA_INT 16
153 #define RTC_SAMINT 18
154 #define UART2_MINT_PFERR 19
155 #define UART2_MINT_RTS 20
156 #define UART2_MINT_DTR 21
157 #define UART2_MINT_UARTC 22
158 #define UART2_MINT_TX 23
159 #define UART2_MINT_RX 24
160 #define UART1_MINT_PFERR 25
161 #define UART1_MINT_RTS 26
162 #define UART1_MINT_DTR 27
163 #define UART1_MINT_UARTC 28
164 #define UART1_MINT_TX 29
165 #define UART1_MINT_RX 30
166 #define VOICE_DAC_INT 31
167 #define VOICE_ADC_INT 32
168 #define PEN_DATA_INT 33
173 #define SSI_TX_INT 42
174 #define SSI_TX_ERR_INT 43
175 #define SSI_RX_INT 44
176 #define SSI_RX_ERR_INT 45
192 #define GPIO_INT_PORTD 62
205 #define TICKS_PER_uSEC 24
208 * These are useconds NOT ticks.
212 #define mSEC_5 (mSEC_1 * 5)
213 #define mSEC_10 (mSEC_1 * 10)
214 #define mSEC_25 (mSEC_1 * 25)
215 #define SEC_1 (mSEC_1 * 1000)