include/asm-i386/apicdef.h

   1 #ifndef __ASM_APICDEF_H
   2 #define __ASM_APICDEF_H
   3
   4 /*
   5  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
   6  *
   7  * Alan Cox <Alan.Cox@linux.org>, 1995.
   8  * Ingo Molnar <mingo@redhat.com>, 1999, 2000
   9  */
  10
  11 #define         APIC_DEFAULT_PHYS_BASE  0xfee00000
  12
  13 #define         APIC_ID         0x20
  14 #define                 APIC_ID_MASK            (0x0F<<24)
  15 #define                 GET_APIC_ID(x)          (((x)>>24)&0x0F)
  16 #define         APIC_LVR        0x30
  17 #define                 APIC_LVR_MASK           0xFF00FF
  18 #define                 GET_APIC_VERSION(x)     ((x)&0xFF)
  19 #define                 GET_APIC_MAXLVT(x)      (((x)>>16)&0xFF)
  20 #define                 APIC_INTEGRATED(x)      ((x)&0xF0)
  21 #define         APIC_TASKPRI    0x80
  22 #define                 APIC_TPRI_MASK          0xFF
  23 #define         APIC_ARBPRI     0x90
  24 #define                 APIC_ARBPRI_MASK        0xFF
  25 #define         APIC_PROCPRI    0xA0
  26 #define         APIC_EOI        0xB0
  27 #define                 APIC_EIO_ACK            0x0             /* Write this to the EOI register */
  28 #define         APIC_RRR        0xC0
  29 #define         APIC_LDR        0xD0
  30 #define                 APIC_LDR_MASK           (0xFF<<24)
  31 #define                 GET_APIC_LOGICAL_ID(x)  (((x)>>24)&0xFF)
  32 #define                 SET_APIC_LOGICAL_ID(x)  (((x)<<24))
  33 #define                 APIC_ALL_CPUS           0xFF
  34 #define         APIC_DFR        0xE0
  35 #define                 APIC_DFR_CLUSTER        0x0FFFFFFFul    /* Clustered */
  36 #define                 APIC_DFR_FLAT           0xFFFFFFFFul    /* Flat mode */
  37 #define         APIC_SPIV       0xF0
  38 #define                 APIC_SPIV_FOCUS_DISABLED        (1<<9)
  39 #define                 APIC_SPIV_APIC_ENABLED          (1<<8)
  40 #define         APIC_ISR        0x100
  41 #define         APIC_TMR        0x180
  42 #define         APIC_IRR        0x200
  43 #define         APIC_ESR        0x280
  44 #define                 APIC_ESR_SEND_CS        0x00001
  45 #define                 APIC_ESR_RECV_CS        0x00002
  46 #define                 APIC_ESR_SEND_ACC       0x00004
  47 #define                 APIC_ESR_RECV_ACC       0x00008
  48 #define                 APIC_ESR_SENDILL        0x00020
  49 #define                 APIC_ESR_RECVILL        0x00040
  50 #define                 APIC_ESR_ILLREGA        0x00080
  51 #define         APIC_ICR        0x300
  52 #define                 APIC_DEST_SELF          0x40000
  53 #define                 APIC_DEST_ALLINC        0x80000
  54 #define                 APIC_DEST_ALLBUT        0xC0000
  55 #define                 APIC_ICR_RR_MASK        0x30000
  56 #define                 APIC_ICR_RR_INVALID     0x00000
  57 #define                 APIC_ICR_RR_INPROG      0x10000
  58 #define                 APIC_ICR_RR_VALID       0x20000
  59 #define                 APIC_INT_LEVELTRIG      0x08000
  60 #define                 APIC_INT_ASSERT         0x04000
  61 #define                 APIC_ICR_BUSY           0x01000
  62 #define                 APIC_DEST_PHYSICAL      0x00000
  63 #define                 APIC_DEST_LOGICAL       0x00800
  64 #define                 APIC_DM_FIXED           0x00000
  65 #define                 APIC_DM_LOWEST          0x00100
  66 #define                 APIC_DM_SMI             0x00200
  67 #define                 APIC_DM_REMRD           0x00300
  68 #define                 APIC_DM_NMI             0x00400
  69 #define                 APIC_DM_INIT            0x00500
  70 #define                 APIC_DM_STARTUP         0x00600
  71 #define                 APIC_DM_EXTINT          0x00700
  72 #define                 APIC_VECTOR_MASK        0x000FF
  73 #define         APIC_ICR2       0x310
  74 #define                 GET_APIC_DEST_FIELD(x)  (((x)>>24)&0xFF)
  75 #define                 SET_APIC_DEST_FIELD(x)  ((x)<<24)
  76 #define         APIC_LVTT       0x320
  77 #define         APIC_LVTPC      0x340
  78 #define         APIC_LVT0       0x350
  79 #define                 APIC_LVT_TIMER_BASE_MASK        (0x3<<18)
  80 #define                 GET_APIC_TIMER_BASE(x)          (((x)>>18)&0x3)
  81 #define                 SET_APIC_TIMER_BASE(x)          (((x)<<18))
  82 #define                 APIC_TIMER_BASE_CLKIN           0x0
  83 #define                 APIC_TIMER_BASE_TMBASE          0x1
  84 #define                 APIC_TIMER_BASE_DIV             0x2
  85 #define                 APIC_LVT_TIMER_PERIODIC         (1<<17)
  86 #define                 APIC_LVT_MASKED                 (1<<16)
  87 #define                 APIC_LVT_LEVEL_TRIGGER          (1<<15)
  88 #define                 APIC_LVT_REMOTE_IRR             (1<<14)
  89 #define                 APIC_INPUT_POLARITY             (1<<13)
  90 #define                 APIC_SEND_PENDING               (1<<12)
  91 #define                 GET_APIC_DELIVERY_MODE(x)       (((x)>>8)&0x7)
  92 #define                 SET_APIC_DELIVERY_MODE(x,y)     (((x)&~0x700)|((y)<<8))
  93 #define                         APIC_MODE_FIXED         0x0
  94 #define                         APIC_MODE_NMI           0x4
  95 #define                         APIC_MODE_EXINT         0x7
  96 #define         APIC_LVT1       0x360
  97 #define         APIC_LVTERR     0x370
  98 #define         APIC_TMICT      0x380
  99 #define         APIC_TMCCT      0x390
 100 #define         APIC_TDCR       0x3E0
 101 #define                 APIC_TDR_DIV_TMBASE     (1<<2)
 102 #define                 APIC_TDR_DIV_1          0xB
 103 #define                 APIC_TDR_DIV_2          0x0
 104 #define                 APIC_TDR_DIV_4          0x1
 105 #define                 APIC_TDR_DIV_8          0x2
 106 #define                 APIC_TDR_DIV_16         0x3
 107 #define                 APIC_TDR_DIV_32         0x8
 108 #define                 APIC_TDR_DIV_64         0x9
 109 #define                 APIC_TDR_DIV_128        0xA
 110
 111 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
 112
 113 #ifdef CONFIG_X86_CLUSTERED_APIC
 114 #define MAX_IO_APICS 32
 115 #else
 116 #define MAX_IO_APICS 8
 117 #endif
 118
 119
 120 /*
 121  * The broadcast ID is 0xF for old APICs and 0xFF for xAPICs.  SAPICs
 122  * don't broadcast (yet?), but if they did, they might use 0xFFFF.
 123  */
 124 #define APIC_BROADCAST_ID_XAPIC (0xFF)
 125 #define APIC_BROADCAST_ID_APIC  (0x0F)
 126
 127 /*
 128  * the local APIC register structure, memory mapped. Not terribly well
 129  * tested, but we might eventually use this one in the future - the
 130  * problem why we cannot use it right now is the P5 APIC, it has an
 131  * errata which cannot take 8-bit reads and writes, only 32-bit ones ...
 132  */
 133 #define u32 unsigned int
 134
 135 #define lapic ((volatile struct local_apic *)APIC_BASE)
 136
 137 struct local_apic {
 138
 139 /*000*/ struct { u32 __reserved[4]; } __reserved_01;
 140
 141 /*010*/ struct { u32 __reserved[4]; } __reserved_02;
 142
 143 /*020*/ struct { /* APIC ID Register */
 144                 u32   __reserved_1      : 24,
 145                         phys_apic_id    :  4,
 146                         __reserved_2    :  4;
 147                 u32 __reserved[3];
 148         } id;
 149
 150 /*030*/ const
 151         struct { /* APIC Version Register */
 152                 u32   version           :  8,
 153                         __reserved_1    :  8,
 154                         max_lvt         :  8,
 155                         __reserved_2    :  8;
 156                 u32 __reserved[3];
 157         } version;
 158
 159 /*040*/ struct { u32 __reserved[4]; } __reserved_03;
 160
 161 /*050*/ struct { u32 __reserved[4]; } __reserved_04;
 162
 163 /*060*/ struct { u32 __reserved[4]; } __reserved_05;
 164
 165 /*070*/ struct { u32 __reserved[4]; } __reserved_06;
 166
 167 /*080*/ struct { /* Task Priority Register */
 168                 u32   priority  :  8,
 169                         __reserved_1    : 24;
 170                 u32 __reserved_2[3];
 171         } tpr;
 172
 173 /*090*/ const
 174         struct { /* Arbitration Priority Register */
 175                 u32   priority  :  8,
 176                         __reserved_1    : 24;
 177                 u32 __reserved_2[3];
 178         } apr;
 179
 180 /*0A0*/ const
 181         struct { /* Processor Priority Register */
 182                 u32   priority  :  8,
 183                         __reserved_1    : 24;
 184                 u32 __reserved_2[3];
 185         } ppr;
 186
 187 /*0B0*/ struct { /* End Of Interrupt Register */
 188                 u32   eoi;
 189                 u32 __reserved[3];
 190         } eoi;
 191
 192 /*0C0*/ struct { u32 __reserved[4]; } __reserved_07;
 193
 194 /*0D0*/ struct { /* Logical Destination Register */
 195                 u32   __reserved_1      : 24,
 196                         logical_dest    :  8;
 197                 u32 __reserved_2[3];
 198         } ldr;
 199
 200 /*0E0*/ struct { /* Destination Format Register */
 201                 u32   __reserved_1      : 28,
 202                         model           :  4;
 203                 u32 __reserved_2[3];
 204         } dfr;
 205
 206 /*0F0*/ struct { /* Spurious Interrupt Vector Register */
 207                 u32     spurious_vector :  8,
 208                         apic_enabled    :  1,
 209                         focus_cpu       :  1,
 210                         __reserved_2    : 22;
 211                 u32 __reserved_3[3];
 212         } svr;
 213
 214 /*100*/ struct { /* In Service Register */
 215 /*170*/         u32 bitfield;
 216                 u32 __reserved[3];
 217         } isr [8];
 218
 219 /*180*/ struct { /* Trigger Mode Register */
 220 /*1F0*/         u32 bitfield;
 221                 u32 __reserved[3];
 222         } tmr [8];
 223
 224 /*200*/ struct { /* Interrupt Request Register */
 225 /*270*/         u32 bitfield;
 226                 u32 __reserved[3];
 227         } irr [8];
 228
 229 /*280*/ union { /* Error Status Register */
 230                 struct {
 231                         u32   send_cs_error                     :  1,
 232                                 receive_cs_error                :  1,
 233                                 send_accept_error               :  1,
 234                                 receive_accept_error            :  1,
 235                                 __reserved_1                    :  1,
 236                                 send_illegal_vector             :  1,
 237                                 receive_illegal_vector          :  1,
 238                                 illegal_register_address        :  1,
 239                                 __reserved_2                    : 24;
 240                         u32 __reserved_3[3];
 241                 } error_bits;
 242                 struct {
 243                         u32 errors;
 244                         u32 __reserved_3[3];
 245                 } all_errors;
 246         } esr;
 247
 248 /*290*/ struct { u32 __reserved[4]; } __reserved_08;
 249
 250 /*2A0*/ struct { u32 __reserved[4]; } __reserved_09;
 251
 252 /*2B0*/ struct { u32 __reserved[4]; } __reserved_10;
 253
 254 /*2C0*/ struct { u32 __reserved[4]; } __reserved_11;
 255
 256 /*2D0*/ struct { u32 __reserved[4]; } __reserved_12;
 257
 258 /*2E0*/ struct { u32 __reserved[4]; } __reserved_13;
 259
 260 /*2F0*/ struct { u32 __reserved[4]; } __reserved_14;
 261
 262 /*300*/ struct { /* Interrupt Command Register 1 */
 263                 u32   vector                    :  8,
 264                         delivery_mode           :  3,
 265                         destination_mode        :  1,
 266                         delivery_status         :  1,
 267                         __reserved_1            :  1,
 268                         level                   :  1,
 269                         trigger                 :  1,
 270                         __reserved_2            :  2,
 271                         shorthand               :  2,
 272                         __reserved_3            :  12;
 273                 u32 __reserved_4[3];
 274         } icr1;
 275
 276 /*310*/ struct { /* Interrupt Command Register 2 */
 277                 union {
 278                         u32   __reserved_1      : 24,
 279                                 phys_dest       :  4,
 280                                 __reserved_2    :  4;
 281                         u32   __reserved_3      : 24,
 282                                 logical_dest    :  8;
 283                 } dest;
 284                 u32 __reserved_4[3];
 285         } icr2;
 286
 287 /*320*/ struct { /* LVT - Timer */
 288                 u32   vector            :  8,
 289                         __reserved_1    :  4,
 290                         delivery_status :  1,
 291                         __reserved_2    :  3,
 292                         mask            :  1,
 293                         timer_mode      :  1,
 294                         __reserved_3    : 14;
 295                 u32 __reserved_4[3];
 296         } lvt_timer;
 297
 298 /*330*/ struct { u32 __reserved[4]; } __reserved_15;
 299
 300 /*340*/ struct { /* LVT - Performance Counter */
 301                 u32   vector            :  8,
 302                         delivery_mode   :  3,
 303                         __reserved_1    :  1,
 304                         delivery_status :  1,
 305                         __reserved_2    :  3,
 306                         mask            :  1,
 307                         __reserved_3    : 15;
 308                 u32 __reserved_4[3];
 309         } lvt_pc;
 310
 311 /*350*/ struct { /* LVT - LINT0 */
 312                 u32   vector            :  8,
 313                         delivery_mode   :  3,
 314                         __reserved_1    :  1,
 315                         delivery_status :  1,
 316                         polarity        :  1,
 317                         remote_irr      :  1,
 318                         trigger         :  1,
 319                         mask            :  1,
 320                         __reserved_2    : 15;
 321                 u32 __reserved_3[3];
 322         } lvt_lint0;
 323
 324 /*360*/ struct { /* LVT - LINT1 */
 325                 u32   vector            :  8,
 326                         delivery_mode   :  3,
 327                         __reserved_1    :  1,
 328                         delivery_status :  1,
 329                         polarity        :  1,
 330                         remote_irr      :  1,
 331                         trigger         :  1,
 332                         mask            :  1,
 333                         __reserved_2    : 15;
 334                 u32 __reserved_3[3];
 335         } lvt_lint1;
 336
 337 /*370*/ struct { /* LVT - Error */
 338                 u32   vector            :  8,
 339                         __reserved_1    :  4,
 340                         delivery_status :  1,
 341                         __reserved_2    :  3,
 342                         mask            :  1,
 343                         __reserved_3    : 15;
 344                 u32 __reserved_4[3];
 345         } lvt_error;
 346
 347 /*380*/ struct { /* Timer Initial Count Register */
 348                 u32   initial_count;
 349                 u32 __reserved_2[3];
 350         } timer_icr;
 351
 352 /*390*/ const
 353         struct { /* Timer Current Count Register */
 354                 u32   curr_count;
 355                 u32 __reserved_2[3];
 356         } timer_ccr;
 357
 358 /*3A0*/ struct { u32 __reserved[4]; } __reserved_16;
 359
 360 /*3B0*/ struct { u32 __reserved[4]; } __reserved_17;
 361
 362 /*3C0*/ struct { u32 __reserved[4]; } __reserved_18;
 363
 364 /*3D0*/ struct { u32 __reserved[4]; } __reserved_19;
 365
 366 /*3E0*/ struct { /* Timer Divide Configuration Register */
 367                 u32   divisor           :  4,
 368                         __reserved_1    : 28;
 369                 u32 __reserved_2[3];
 370         } timer_dcr;
 371
 372 /*3F0*/ struct { u32 __reserved[4]; } __reserved_20;
 373
 374 } __attribute__ ((packed));
 375
 376 #undef u32
 377
 378 #endif