2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1995, 1996, 1997 by Ralf Baechle
7 * Copyright (C) 2002 Maciej W. Rozycki
9 * Some useful macros for MIPS assembler code
11 * Some of the routines below contain useless nops that will be optimized
12 * away by gas in -O mode. These nops are however required to fill delay
13 * slots in noreorder mode.
18 #include <linux/config.h>
19 #include <asm/sgidefs.h>
23 #define __CAT(str1,str2) str1##str2
25 #define __CAT(str1,str2) str1/**/str2
27 #define CAT(str1,str2) __CAT(str1,str2)
31 * PIC specific declarations
32 * Not used for the kernel but here seems to be the right place.
35 #define CPRESTORE(register) \
37 #define CPADD(register) \
39 #define CPLOAD(register) \
42 #define CPRESTORE(register)
43 #define CPADD(register)
44 #define CPLOAD(register)
48 * LEAF - declare leaf routine
50 #define LEAF(symbol) \
53 .type symbol,@function; \
55 symbol: .frame sp,0,ra
58 * NESTED - declare nested routine entry point
60 #define NESTED(symbol, framesize, rpc) \
63 .type symbol,@function; \
65 symbol: .frame sp, framesize, rpc
68 * END - mark end of function
70 #define END(function) \
72 .size function,.-function
75 * EXPORT - export definition of symbol
77 #define EXPORT(symbol) \
82 * FEXPORT - export definition of a function symbol
84 #define FEXPORT(symbol) \
86 .type symbol,@function; \
90 * ABS - export absolute symbol
92 #define ABS(symbol,value) \
106 * Print formatted string
108 #define PRINT(string) \
117 .pushsection .data; \
124 #define TTABLE(string) \
125 .pushsection .text; \
128 .pushsection .data; \
133 * MIPS IV pref instruction.
134 * Use with .set noreorder only!
136 * MIPS IV implementations are free to treat this as a nop. The R5000
137 * is one of them. So we should have an option not to use this instruction.
139 #if CONFIG_CPU_HAS_PREFETCH
141 #define PREF(hint,addr) \
147 #define PREFX(hint,addr) \
155 #define PREF(hint,addr)
156 #define PREFX(hint,addr)
161 * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
163 #if (_MIPS_ISA == _MIPS_ISA_MIPS1)
164 #define MOVN(rd,rs,rt) \
171 #define MOVZ(rd,rs,rt) \
178 #endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
179 #if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
180 #define MOVN(rd,rs,rt) \
187 #define MOVZ(rd,rs,rt) \
194 #endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
195 #if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
196 (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
197 #define MOVN(rd,rs,rt) \
199 #define MOVZ(rd,rs,rt) \
201 #endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
206 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
207 (_MIPS_ISA == _MIPS_ISA_MIPS32)
211 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
212 (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
218 * Macros to handle different pointer/register sizes for 32/64-bit code
231 * Use the following macros in assemblercode to load/store registers,
234 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
235 (_MIPS_ISA == _MIPS_ISA_MIPS32)
238 #define REG_SUBU subu
239 #define REG_ADDU addu
241 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
242 (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
245 #define REG_SUBU dsubu
246 #define REG_ADDU daddu
250 * How to add/sub/load/store/shift C int variables.
252 #if (_MIPS_SZINT == 32)
254 #define INT_ADDU addu
255 #define INT_ADDI addi
256 #define INT_ADDIU addiu
258 #define INT_SUBU subu
262 #define INT_SLLV sllv
264 #define INT_SRLV srlv
266 #define INT_SRAV srav
269 #if (_MIPS_SZINT == 64)
271 #define INT_ADDU daddu
272 #define INT_ADDI daddi
273 #define INT_ADDIU daddiu
275 #define INT_SUBU dsubu
279 #define INT_SLLV dsllv
281 #define INT_SRLV dsrlv
283 #define INT_SRAV dsrav
287 * How to add/sub/load/store/shift C long variables.
289 #if (_MIPS_SZLONG == 32)
291 #define LONG_ADDU addu
292 #define LONG_ADDI addi
293 #define LONG_ADDIU addiu
295 #define LONG_SUBU subu
299 #define LONG_SLLV sllv
301 #define LONG_SRLV srlv
303 #define LONG_SRAV srav
306 #if (_MIPS_SZLONG == 64)
307 #define LONG_ADD dadd
308 #define LONG_ADDU daddu
309 #define LONG_ADDI daddi
310 #define LONG_ADDIU daddiu
311 #define LONG_SUB dsub
312 #define LONG_SUBU dsubu
315 #define LONG_SLL dsll
316 #define LONG_SLLV dsllv
317 #define LONG_SRL dsrl
318 #define LONG_SRLV dsrlv
319 #define LONG_SRA dsra
320 #define LONG_SRAV dsrav
324 * How to add/sub/load/store/shift pointers.
326 #if (_MIPS_SZPTR == 32)
328 #define PTR_ADDU addu
329 #define PTR_ADDI addi
330 #define PTR_ADDIU addiu
332 #define PTR_SUBU subu
337 #define PTR_SLLV sllv
339 #define PTR_SRLV srlv
341 #define PTR_SRAV srav
343 #define PTR_SCALESHIFT 2
350 #if (_MIPS_SZPTR == 64)
352 #define PTR_ADDU daddu
353 #define PTR_ADDI daddi
354 #define PTR_ADDIU daddiu
356 #define PTR_SUBU dsubu
361 #define PTR_SLLV dsllv
363 #define PTR_SRLV dsrlv
365 #define PTR_SRAV dsrav
367 #define PTR_SCALESHIFT 3
375 * Some cp0 registers were extended to 64bit for MIPS III.
377 #if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
378 (_MIPS_ISA == _MIPS_ISA_MIPS32)
382 #if (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
383 (_MIPS_ISA == _MIPS_ISA_MIPS5) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
388 #define SSNOP sll zero,zero,1
390 #endif /* __ASM_ASM_H */