2 * BRIEF MODULE DESCRIPTION
3 * Defines for using and allocating dma channels on the Alchemy
4 * Au1000 mips processor.
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * stevel@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 #ifndef __ASM_AU1000_DMA_H
32 #define __ASM_AU1000_DMA_H
34 #include <asm/io.h> /* need byte IO */
35 #include <linux/spinlock.h> /* And spinlocks */
36 #include <linux/delay.h>
37 #include <asm/system.h>
39 #define NUM_AU1000_DMA_CHANNELS 8
41 /* DMA Channel Base Addresses */
42 #define DMA_CHANNEL_BASE 0xB4002000
43 #define DMA_CHANNEL_LEN 0x00000100
45 /* DMA Channel Register Offsets */
46 #define DMA_MODE_SET 0x00000000
47 #define DMA_MODE_READ DMA_MODE_SET
48 #define DMA_MODE_CLEAR 0x00000004
49 /* DMA Mode register bits follow */
50 #define DMA_DAH_MASK (0x0f << 20)
51 #define DMA_DID_BIT 16
52 #define DMA_DID_MASK (0x0f << DMA_DID_BIT)
53 #define DMA_BE (1<<13)
54 #define DMA_DR (1<<12)
55 #define DMA_TS8 (1<<11)
57 #define DMA_DW_MASK (0x03 << DMA_DW_BIT)
58 #define DMA_DW8 (0 << DMA_DW_BIT)
59 #define DMA_DW16 (1 << DMA_DW_BIT)
60 #define DMA_DW32 (2 << DMA_DW_BIT)
63 #define DMA_HALT (1<<6)
67 #define DMA_BE1 (1<<2)
69 #define DMA_BE0 (1<<0)
71 #define DMA_PERIPHERAL_ADDR 0x00000008
72 #define DMA_BUFFER0_START 0x0000000C
73 #define DMA_BUFFER1_START 0x00000014
74 #define DMA_BUFFER0_COUNT 0x00000010
75 #define DMA_BUFFER1_COUNT 0x00000018
76 #define DMA_BAH_BIT 16
77 #define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
78 #define DMA_COUNT_BIT 0
79 #define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
81 /* DMA Device ID's follow */
103 int dev_id; // this channel is allocated if >=0, free otherwise
108 unsigned int fifo_addr;
112 /* These are in arch/mips/au1000/common/dma.c */
113 extern struct dma_chan au1000_dma_table[];
114 extern int request_au1000_dma(int dev_id,
116 void (*irqhandler)(int, void *,
118 unsigned long irqflags,
120 extern void free_au1000_dma(unsigned int dmanr);
121 extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
122 int length, int *eof, void *data);
123 extern void dump_au1000_dma_channel(unsigned int dmanr);
124 extern spinlock_t au1000_dma_spin_lock;
127 static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
129 if (dmanr > NUM_AU1000_DMA_CHANNELS
130 || au1000_dma_table[dmanr].dev_id < 0)
132 return &au1000_dma_table[dmanr];
135 static __inline__ unsigned long claim_dma_lock(void)
138 spin_lock_irqsave(&au1000_dma_spin_lock, flags);
142 static __inline__ void release_dma_lock(unsigned long flags)
144 spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
148 * Set the DMA buffer enable bits in the mode register.
150 static __inline__ void enable_dma_buffer0(unsigned int dmanr)
152 struct dma_chan *chan = get_dma_chan(dmanr);
155 au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
157 static __inline__ void enable_dma_buffer1(unsigned int dmanr)
159 struct dma_chan *chan = get_dma_chan(dmanr);
162 au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
164 static __inline__ void enable_dma_buffers(unsigned int dmanr)
166 struct dma_chan *chan = get_dma_chan(dmanr);
169 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
172 static __inline__ void start_dma(unsigned int dmanr)
174 struct dma_chan *chan = get_dma_chan(dmanr);
178 au_writel(DMA_GO, chan->io + DMA_MODE_SET);
181 #define DMA_HALT_POLL 0x5000
183 static __inline__ void halt_dma(unsigned int dmanr)
185 struct dma_chan *chan = get_dma_chan(dmanr);
190 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
192 for (i = 0; i < DMA_HALT_POLL; i++)
193 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
195 if (i == DMA_HALT_POLL)
196 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
200 static __inline__ void disable_dma(unsigned int dmanr)
202 struct dma_chan *chan = get_dma_chan(dmanr);
208 // now we can disable the buffers
209 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
212 static __inline__ int dma_halted(unsigned int dmanr)
214 struct dma_chan *chan = get_dma_chan(dmanr);
217 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
220 /* initialize a DMA channel */
221 static __inline__ void init_dma(unsigned int dmanr)
223 struct dma_chan *chan = get_dma_chan(dmanr);
230 // set device FIFO address
231 au_writel(virt_to_phys((void *) chan->fifo_addr),
232 chan->io + DMA_PERIPHERAL_ADDR);
234 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
238 au_writel(~mode, chan->io + DMA_MODE_CLEAR);
239 au_writel(mode, chan->io + DMA_MODE_SET);
243 * set mode for a specific DMA channel
245 static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
247 struct dma_chan *chan = get_dma_chan(dmanr);
251 * set_dma_mode is only allowed to change endianess, direction,
252 * transfer size, device FIFO width, and coherency settings.
253 * Make sure anything else is masked off.
255 mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
256 chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
260 static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
262 struct dma_chan *chan = get_dma_chan(dmanr);
268 static __inline__ int get_dma_active_buffer(unsigned int dmanr)
270 struct dma_chan *chan = get_dma_chan(dmanr);
273 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
278 * set the device FIFO address for a specific DMA channel - only
279 * applicable to GPO4 and GPO5. All the other devices have fixed
282 static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
285 struct dma_chan *chan = get_dma_chan(dmanr);
289 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
292 au_writel(virt_to_phys((void *) a),
293 chan->io + DMA_PERIPHERAL_ADDR);
297 * Clear the DMA buffer done bits in the mode register.
299 static __inline__ void clear_dma_done0(unsigned int dmanr)
301 struct dma_chan *chan = get_dma_chan(dmanr);
304 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
306 static __inline__ void clear_dma_done1(unsigned int dmanr)
308 struct dma_chan *chan = get_dma_chan(dmanr);
311 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
315 * This does nothing - not applicable to Au1000 DMA.
317 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
322 * Set Buffer 0 transfer address for specific DMA channel.
324 static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
326 struct dma_chan *chan = get_dma_chan(dmanr);
329 au_writel(a, chan->io + DMA_BUFFER0_START);
333 * Set Buffer 1 transfer address for specific DMA channel.
335 static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
337 struct dma_chan *chan = get_dma_chan(dmanr);
340 au_writel(a, chan->io + DMA_BUFFER1_START);
345 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
347 static __inline__ void set_dma_count0(unsigned int dmanr,
350 struct dma_chan *chan = get_dma_chan(dmanr);
353 count &= DMA_COUNT_MASK;
354 au_writel(count, chan->io + DMA_BUFFER0_COUNT);
358 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
360 static __inline__ void set_dma_count1(unsigned int dmanr,
363 struct dma_chan *chan = get_dma_chan(dmanr);
366 count &= DMA_COUNT_MASK;
367 au_writel(count, chan->io + DMA_BUFFER1_COUNT);
371 * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
373 static __inline__ void set_dma_count(unsigned int dmanr,
376 struct dma_chan *chan = get_dma_chan(dmanr);
379 count &= DMA_COUNT_MASK;
380 au_writel(count, chan->io + DMA_BUFFER0_COUNT);
381 au_writel(count, chan->io + DMA_BUFFER1_COUNT);
385 * Returns which buffer has its done bit set in the mode register.
386 * Returns -1 if neither or both done bits set.
388 static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
390 struct dma_chan *chan = get_dma_chan(dmanr);
394 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
399 * Returns the DMA channel's Buffer Done IRQ number.
401 static __inline__ int get_dma_done_irq(unsigned int dmanr)
403 struct dma_chan *chan = get_dma_chan(dmanr);
411 * Get DMA residue count. Returns the number of _bytes_ left to transfer.
413 static __inline__ int get_dma_residue(unsigned int dmanr)
415 int curBufCntReg, count;
416 struct dma_chan *chan = get_dma_chan(dmanr);
420 curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
421 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
423 count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
425 if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
427 else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
433 #endif /* __ASM_AU1000_DMA_H */