2 * BRIEF MODULE DESCRIPTION
3 * Defines for using and allocating dma channels on the Alchemy
4 * Au1000 mips processor.
6 * Copyright 2000 MontaVista Software Inc.
7 * Author: MontaVista Software, Inc.
8 * stevel@mvista.com or source@mvista.com
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 #ifndef __ASM_AU1000_DMA_H
32 #define __ASM_AU1000_DMA_H
34 #include <linux/config.h>
35 #include <asm/io.h> /* need byte IO */
36 #include <linux/spinlock.h> /* And spinlocks */
37 #include <linux/delay.h>
38 #include <asm/system.h>
40 #define NUM_AU1000_DMA_CHANNELS 8
42 /* DMA Channel Base Addresses */
43 #define DMA_CHANNEL_BASE 0xB4002000
44 #define DMA_CHANNEL_LEN 0x00000100
46 /* DMA Channel Register Offsets */
47 #define DMA_MODE_SET 0x00000000
48 #define DMA_MODE_READ DMA_MODE_SET
49 #define DMA_MODE_CLEAR 0x00000004
50 /* DMA Mode register bits follow */
51 #define DMA_DAH_MASK (0x0f << 20)
52 #define DMA_DID_BIT 16
53 #define DMA_DID_MASK (0x0f << DMA_DID_BIT)
54 #define DMA_DS (1<<15)
55 #define DMA_BE (1<<13)
56 #define DMA_DR (1<<12)
57 #define DMA_TS8 (1<<11)
59 #define DMA_DW_MASK (0x03 << DMA_DW_BIT)
60 #define DMA_DW8 (0 << DMA_DW_BIT)
61 #define DMA_DW16 (1 << DMA_DW_BIT)
62 #define DMA_DW32 (2 << DMA_DW_BIT)
65 #define DMA_HALT (1<<6)
69 #define DMA_BE1 (1<<2)
71 #define DMA_BE0 (1<<0)
73 #define DMA_PERIPHERAL_ADDR 0x00000008
74 #define DMA_BUFFER0_START 0x0000000C
75 #define DMA_BUFFER1_START 0x00000014
76 #define DMA_BUFFER0_COUNT 0x00000010
77 #define DMA_BUFFER1_COUNT 0x00000018
78 #define DMA_BAH_BIT 16
79 #define DMA_BAH_MASK (0x0f << DMA_BAH_BIT)
80 #define DMA_COUNT_BIT 0
81 #define DMA_COUNT_MASK (0xffff << DMA_COUNT_BIT)
83 /* DMA Device ID's follow */
104 /* DMA Device ID's for 2nd bank (AU1100) follow */
114 int dev_id; // this channel is allocated if >=0, free otherwise
119 unsigned int fifo_addr;
123 /* These are in arch/mips/au1000/common/dma.c */
124 extern struct dma_chan au1000_dma_table[];
125 extern int request_au1000_dma(int dev_id,
127 void (*irqhandler)(int, void *,
129 unsigned long irqflags,
131 extern void free_au1000_dma(unsigned int dmanr);
132 extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
133 int length, int *eof, void *data);
134 extern void dump_au1000_dma_channel(unsigned int dmanr);
135 extern spinlock_t au1000_dma_spin_lock;
138 static __inline__ struct dma_chan *get_dma_chan(unsigned int dmanr)
140 if (dmanr >= NUM_AU1000_DMA_CHANNELS
141 || au1000_dma_table[dmanr].dev_id < 0)
143 return &au1000_dma_table[dmanr];
146 static __inline__ unsigned long claim_dma_lock(void)
149 spin_lock_irqsave(&au1000_dma_spin_lock, flags);
153 static __inline__ void release_dma_lock(unsigned long flags)
155 spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
159 * Set the DMA buffer enable bits in the mode register.
161 static __inline__ void enable_dma_buffer0(unsigned int dmanr)
163 struct dma_chan *chan = get_dma_chan(dmanr);
166 au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
168 static __inline__ void enable_dma_buffer1(unsigned int dmanr)
170 struct dma_chan *chan = get_dma_chan(dmanr);
173 au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
175 static __inline__ void enable_dma_buffers(unsigned int dmanr)
177 struct dma_chan *chan = get_dma_chan(dmanr);
180 au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
183 static __inline__ void start_dma(unsigned int dmanr)
185 struct dma_chan *chan = get_dma_chan(dmanr);
189 au_writel(DMA_GO, chan->io + DMA_MODE_SET);
192 #define DMA_HALT_POLL 0x5000
194 static __inline__ void halt_dma(unsigned int dmanr)
196 struct dma_chan *chan = get_dma_chan(dmanr);
201 au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
203 for (i = 0; i < DMA_HALT_POLL; i++)
204 if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
206 if (i == DMA_HALT_POLL)
207 printk(KERN_INFO "halt_dma: HALT poll expired!\n");
211 static __inline__ void disable_dma(unsigned int dmanr)
213 struct dma_chan *chan = get_dma_chan(dmanr);
219 // now we can disable the buffers
220 au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
223 static __inline__ int dma_halted(unsigned int dmanr)
225 struct dma_chan *chan = get_dma_chan(dmanr);
228 return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
231 /* initialize a DMA channel */
232 static __inline__ void init_dma(unsigned int dmanr)
234 struct dma_chan *chan = get_dma_chan(dmanr);
241 // set device FIFO address
242 au_writel(PHYSADDR(chan->fifo_addr),
243 chan->io + DMA_PERIPHERAL_ADDR);
245 mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
249 au_writel(~mode, chan->io + DMA_MODE_CLEAR);
250 au_writel(mode, chan->io + DMA_MODE_SET);
254 * set mode for a specific DMA channel
256 static __inline__ void set_dma_mode(unsigned int dmanr, unsigned int mode)
258 struct dma_chan *chan = get_dma_chan(dmanr);
262 * set_dma_mode is only allowed to change endianess, direction,
263 * transfer size, device FIFO width, and coherency settings.
264 * Make sure anything else is masked off.
266 mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
267 chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
271 static __inline__ unsigned int get_dma_mode(unsigned int dmanr)
273 struct dma_chan *chan = get_dma_chan(dmanr);
279 static __inline__ int get_dma_active_buffer(unsigned int dmanr)
281 struct dma_chan *chan = get_dma_chan(dmanr);
284 return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
289 * set the device FIFO address for a specific DMA channel - only
290 * applicable to GPO4 and GPO5. All the other devices have fixed
293 static __inline__ void set_dma_fifo_addr(unsigned int dmanr,
296 struct dma_chan *chan = get_dma_chan(dmanr);
300 if (chan->mode & DMA_DS) /* second bank of device ids */
303 if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
306 au_writel(PHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
310 * Clear the DMA buffer done bits in the mode register.
312 static __inline__ void clear_dma_done0(unsigned int dmanr)
314 struct dma_chan *chan = get_dma_chan(dmanr);
317 au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
319 static __inline__ void clear_dma_done1(unsigned int dmanr)
321 struct dma_chan *chan = get_dma_chan(dmanr);
324 au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
328 * This does nothing - not applicable to Au1000 DMA.
330 static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
335 * Set Buffer 0 transfer address for specific DMA channel.
337 static __inline__ void set_dma_addr0(unsigned int dmanr, unsigned int a)
339 struct dma_chan *chan = get_dma_chan(dmanr);
342 au_writel(a, chan->io + DMA_BUFFER0_START);
346 * Set Buffer 1 transfer address for specific DMA channel.
348 static __inline__ void set_dma_addr1(unsigned int dmanr, unsigned int a)
350 struct dma_chan *chan = get_dma_chan(dmanr);
353 au_writel(a, chan->io + DMA_BUFFER1_START);
358 * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
360 static __inline__ void set_dma_count0(unsigned int dmanr,
363 struct dma_chan *chan = get_dma_chan(dmanr);
366 count &= DMA_COUNT_MASK;
367 au_writel(count, chan->io + DMA_BUFFER0_COUNT);
371 * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
373 static __inline__ void set_dma_count1(unsigned int dmanr,
376 struct dma_chan *chan = get_dma_chan(dmanr);
379 count &= DMA_COUNT_MASK;
380 au_writel(count, chan->io + DMA_BUFFER1_COUNT);
384 * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
386 static __inline__ void set_dma_count(unsigned int dmanr,
389 struct dma_chan *chan = get_dma_chan(dmanr);
392 count &= DMA_COUNT_MASK;
393 au_writel(count, chan->io + DMA_BUFFER0_COUNT);
394 au_writel(count, chan->io + DMA_BUFFER1_COUNT);
398 * Returns which buffer has its done bit set in the mode register.
399 * Returns -1 if neither or both done bits set.
401 static __inline__ unsigned int get_dma_buffer_done(unsigned int dmanr)
403 struct dma_chan *chan = get_dma_chan(dmanr);
407 return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
412 * Returns the DMA channel's Buffer Done IRQ number.
414 static __inline__ int get_dma_done_irq(unsigned int dmanr)
416 struct dma_chan *chan = get_dma_chan(dmanr);
424 * Get DMA residue count. Returns the number of _bytes_ left to transfer.
426 static __inline__ int get_dma_residue(unsigned int dmanr)
428 int curBufCntReg, count;
429 struct dma_chan *chan = get_dma_chan(dmanr);
433 curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
434 DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
436 count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
438 if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
440 else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
446 #endif /* __ASM_AU1000_DMA_H */