3 * BRIEF MODULE DESCRIPTION
4 * Include file for Alchemy Semiconductor's Au1550 Descriptor
5 * Based DMA Controller.
7 * Copyright 2004 Embedded Edge, LLC
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License as published by the
12 * Free Software Foundation; either version 2 of the License, or (at your
13 * option) any later version.
15 * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
17 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
21 * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
22 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * You should have received a copy of the GNU General Public License along
27 * with this program; if not, write to the Free Software Foundation, Inc.,
28 * 675 Mass Ave, Cambridge, MA 02139, USA.
31 /* Specifics for the Au1xxx Descriptor-Based DMA Controllers, first
32 * seen in the AU1550 part.
34 #ifndef _AU1000_DBDMA_H_
35 #define _AU1000_DBDMA_H_
37 #ifndef _LANGUAGE_ASSEMBLY
39 /* The DMA base addresses.
40 * The Channels are every 256 bytes (0x0100) from the channel 0 base.
41 * Interrupt status/enable is bits 15:0 for channels 15 to zero.
43 #define DDMA_GLOBAL_BASE 0xb4003000
44 #define DDMA_CHANNEL_BASE 0xb4002000
46 typedef struct dbdma_global {
53 /* General Configuration.
55 #define DDMA_CONFIG_AF (1 << 2)
56 #define DDMA_CONFIG_AH (1 << 1)
57 #define DDMA_CONFIG_AL (1 << 0)
59 #define DDMA_THROTTLE_EN (1 << 31)
61 /* The structure of a DMA Channel.
63 typedef struct au1xxx_dma_channel {
64 u32 ddma_cfg; /* See below */
65 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
66 u32 ddma_statptr; /* word aligned pointer to status word */
67 u32 ddma_dbell; /* A write activates channel operation */
68 u32 ddma_irq; /* If bit 0 set, interrupt pending */
69 u32 ddma_stat; /* See below */
70 u32 ddma_bytecnt; /* Byte count, valid only when chan idle */
71 /* Remainder, up to the 256 byte boundary, is reserved.
75 #define DDMA_CFG_SED (1 << 9) /* source DMA level/edge detect */
76 #define DDMA_CFG_SP (1 << 8) /* source DMA polarity */
77 #define DDMA_CFG_DED (1 << 7) /* destination DMA level/edge detect */
78 #define DDMA_CFG_DP (1 << 6) /* destination DMA polarity */
79 #define DDMA_CFG_SYNC (1 << 5) /* Sync static bus controller */
80 #define DDMA_CFG_PPR (1 << 4) /* PCI posted read/write control */
81 #define DDMA_CFG_DFN (1 << 3) /* Descriptor fetch non-coherent */
82 #define DDMA_CFG_SBE (1 << 2) /* Source big endian */
83 #define DDMA_CFG_DBE (1 << 1) /* Destination big endian */
84 #define DDMA_CFG_EN (1 << 0) /* Channel enable */
86 /* Always set when descriptor processing done, regardless of
87 * interrupt enable state. Reflected in global intstat, don't
88 * clear this until global intstat is read/used.
90 #define DDMA_IRQ_IN (1 << 0)
92 #define DDMA_STAT_DB (1 << 2) /* Doorbell pushed */
93 #define DDMA_STAT_V (1 << 1) /* Descriptor valid */
94 #define DDMA_STAT_H (1 << 0) /* Channel Halted */
96 /* "Standard" DDMA Descriptor.
97 * Must be 32-byte aligned.
99 typedef struct au1xxx_ddma_desc {
100 u32 dscr_cmd0; /* See below */
101 u32 dscr_cmd1; /* See below */
102 u32 dscr_source0; /* source phys address */
103 u32 dscr_source1; /* See below */
104 u32 dscr_dest0; /* Destination address */
105 u32 dscr_dest1; /* See below */
106 u32 dscr_stat; /* completion status */
107 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
110 #define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
111 #define DSCR_CMD0_MEM (1 << 30) /* mem-mem transfer */
112 #define DSCR_CMD0_SID_MASK (0x1f << 25) /* Source ID */
113 #define DSCR_CMD0_DID_MASK (0x1f << 20) /* Destination ID */
114 #define DSCR_CMD0_SW_MASK (0x3 << 18) /* Source Width */
115 #define DSCR_CMD0_DW_MASK (0x3 << 16) /* Destination Width */
116 #define DSCR_CMD0_ARB (0x1 << 15) /* Set for Hi Pri */
117 #define DSCR_CMD0_DT_MASK (0x3 << 13) /* Descriptor Type */
118 #define DSCR_CMD0_SN (0x1 << 12) /* Source non-coherent */
119 #define DSCR_CMD0_DN (0x1 << 11) /* Destination non-coherent */
120 #define DSCR_CMD0_SM (0x1 << 10) /* Stride mode */
121 #define DSCR_CMD0_IE (0x1 << 8) /* Interrupt Enable */
122 #define DSCR_CMD0_SP (0x1 << 4) /* Status pointer select */
123 #define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
124 #define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
126 /* Command 0 device IDs.
128 #ifdef CONFIG_SOC_AU1550
129 #define DSCR_CMD0_UART0_TX 0
130 #define DSCR_CMD0_UART0_RX 1
131 #define DSCR_CMD0_UART3_TX 2
132 #define DSCR_CMD0_UART3_RX 3
133 #define DSCR_CMD0_DMA_REQ0 4
134 #define DSCR_CMD0_DMA_REQ1 5
135 #define DSCR_CMD0_DMA_REQ2 6
136 #define DSCR_CMD0_DMA_REQ3 7
137 #define DSCR_CMD0_USBDEV_RX0 8
138 #define DSCR_CMD0_USBDEV_TX0 9
139 #define DSCR_CMD0_USBDEV_TX1 10
140 #define DSCR_CMD0_USBDEV_TX2 11
141 #define DSCR_CMD0_USBDEV_RX3 12
142 #define DSCR_CMD0_USBDEV_RX4 13
143 #define DSCR_CMD0_PSC0_TX 14
144 #define DSCR_CMD0_PSC0_RX 15
145 #define DSCR_CMD0_PSC1_TX 16
146 #define DSCR_CMD0_PSC1_RX 17
147 #define DSCR_CMD0_PSC2_TX 18
148 #define DSCR_CMD0_PSC2_RX 19
149 #define DSCR_CMD0_PSC3_TX 20
150 #define DSCR_CMD0_PSC3_RX 21
151 #define DSCR_CMD0_PCI_WRITE 22
152 #define DSCR_CMD0_NAND_FLASH 23
153 #define DSCR_CMD0_MAC0_RX 24
154 #define DSCR_CMD0_MAC0_TX 25
155 #define DSCR_CMD0_MAC1_RX 26
156 #define DSCR_CMD0_MAC1_TX 27
157 #endif /* CONFIG_SOC_AU1550 */
159 #ifdef CONFIG_SOC_AU1200
160 #define DSCR_CMD0_UART0_TX 0
161 #define DSCR_CMD0_UART0_RX 1
162 #define DSCR_CMD0_UART1_TX 2
163 #define DSCR_CMD0_UART1_RX 3
164 #define DSCR_CMD0_DMA_REQ0 4
165 #define DSCR_CMD0_DMA_REQ1 5
166 #define DSCR_CMD0_MAE_BE 6
167 #define DSCR_CMD0_MAE_FE 7
168 #define DSCR_CMD0_SDMS_TX0 8
169 #define DSCR_CMD0_SDMS_RX0 9
170 #define DSCR_CMD0_SDMS_TX1 10
171 #define DSCR_CMD0_SDMS_RX1 11
172 #define DSCR_CMD0_AES_TX 12
173 #define DSCR_CMD0_AES_RX 13
174 #define DSCR_CMD0_PSC0_TX 14
175 #define DSCR_CMD0_PSC0_RX 15
176 #define DSCR_CMD0_PSC1_TX 16
177 #define DSCR_CMD0_PSC1_RX 17
178 #define DSCR_CMD0_CIM_RXA 18
179 #define DSCR_CMD0_CIM_RXB 19
180 #define DSCR_CMD0_CIM_RXC 20
181 #define DSCR_CMD0_MAE_BOTH 21
182 #define DSCR_CMD0_LCD 22
183 #define DSCR_CMD0_NAND_FLASH 23
184 #define DSCR_CMD0_PSC0_SYNC 24
185 #define DSCR_CMD0_PSC1_SYNC 25
186 #define DSCR_CMD0_CIM_SYNC 26
187 #endif /* CONFIG_SOC_AU1200 */
189 #define DSCR_CMD0_THROTTLE 30
190 #define DSCR_CMD0_ALWAYS 31
191 #define DSCR_NDEV_IDS 32
193 #define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
194 #define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
196 /* Source/Destination transfer width.
198 #define DSCR_CMD0_BYTE 0
199 #define DSCR_CMD0_HALFWORD 1
200 #define DSCR_CMD0_WORD 2
202 #define DSCR_CMD0_SW(x) (((x) & 0x3) << 18)
203 #define DSCR_CMD0_DW(x) (((x) & 0x3) << 16)
205 /* DDMA Descriptor Type.
207 #define DSCR_CMD0_STANDARD 0
208 #define DSCR_CMD0_LITERAL 1
209 #define DSCR_CMD0_CMP_BRANCH 2
211 #define DSCR_CMD0_DT(x) (((x) & 0x3) << 13)
213 /* Status Instruction.
215 #define DSCR_CMD0_ST_NOCHANGE 0 /* Don't change */
216 #define DSCR_CMD0_ST_CURRENT 1 /* Write current status */
217 #define DSCR_CMD0_ST_CMD0 2 /* Write cmd0 with V cleared */
218 #define DSCR_CMD0_ST_BYTECNT 3 /* Write remaining byte count */
220 #define DSCR_CMD0_ST(x) (((x) & 0x3) << 0)
222 /* Descriptor Command 1
224 #define DSCR_CMD1_SUPTR_MASK (0xf << 28) /* upper 4 bits of src addr */
225 #define DSCR_CMD1_DUPTR_MASK (0xf << 24) /* upper 4 bits of dest addr */
226 #define DSCR_CMD1_FL_MASK (0x3 << 22) /* Flag bits */
227 #define DSCR_CMD1_BC_MASK (0x3fffff) /* Byte count */
231 #define DSCR_CMD1_FL_MEM_STRIDE0 0
232 #define DSCR_CMD1_FL_MEM_STRIDE1 1
233 #define DSCR_CMD1_FL_MEM_STRIDE2 2
235 #define DSCR_CMD1_FL(x) (((x) & 0x3) << 22)
237 /* Source1, 1-dimensional stride.
239 #define DSCR_SRC1_STS_MASK (3 << 30) /* Src xfer size */
240 #define DSCR_SRC1_SAM_MASK (3 << 28) /* Src xfer movement */
241 #define DSCR_SRC1_SB_MASK (0x3fff << 14) /* Block size */
242 #define DSCR_SRC1_SB(x) (((x) & 0x3fff) << 14)
243 #define DSCR_SRC1_SS_MASK (0x3fff << 0) /* Stride */
244 #define DSCR_SRC1_SS(x) (((x) & 0x3fff) << 0)
246 /* Dest1, 1-dimensional stride.
248 #define DSCR_DEST1_DTS_MASK (3 << 30) /* Dest xfer size */
249 #define DSCR_DEST1_DAM_MASK (3 << 28) /* Dest xfer movement */
250 #define DSCR_DEST1_DB_MASK (0x3fff << 14) /* Block size */
251 #define DSCR_DEST1_DB(x) (((x) & 0x3fff) << 14)
252 #define DSCR_DEST1_DS_MASK (0x3fff << 0) /* Stride */
253 #define DSCR_DEST1_DS(x) (((x) & 0x3fff) << 0)
255 #define DSCR_xTS_SIZE1 0
256 #define DSCR_xTS_SIZE2 1
257 #define DSCR_xTS_SIZE4 2
258 #define DSCR_xTS_SIZE8 3
259 #define DSCR_SRC1_STS(x) (((x) & 3) << 30)
260 #define DSCR_DEST1_DTS(x) (((x) & 3) << 30)
262 #define DSCR_xAM_INCREMENT 0
263 #define DSCR_xAM_DECREMENT 1
264 #define DSCR_xAM_STATIC 2
265 #define DSCR_xAM_BURST 3
266 #define DSCR_SRC1_SAM(x) (((x) & 3) << 28)
267 #define DSCR_DEST1_DAM(x) (((x) & 3) << 28)
269 /* The next descriptor pointer.
271 #define DSCR_NXTPTR_MASK (0x07ffffff)
272 #define DSCR_NXTPTR(x) ((x) >> 5)
273 #define DSCR_GET_NXTPTR(x) ((x) << 5)
274 #define DSCR_NXTPTR_MS (1 << 27)
276 /* The number of DBDMA channels.
278 #define NUM_DBDMA_CHANS 16
280 /* External functions for drivers to use.
282 /* Use this to allocate a dbdma channel. The device ids are one of the
283 * DSCR_CMD0 devices IDs, which is usually redefined to a more
284 * meaningful name. The 'callback' is called during dma completion
287 u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
288 void (*callback)(int, void *, struct pt_regs *), void *callparam);
290 #define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
292 /* Set the device width of a in/out fifo.
294 u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
296 /* Allocate a ring of descriptors for dbdma.
298 u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
300 /* Put buffers on source/destination descriptors.
302 u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes);
303 u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes);
305 /* Get a buffer from the destination descriptor.
307 u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
309 void au1xxx_dbdma_stop(u32 chanid);
310 void au1xxx_dbdma_start(u32 chanid);
311 void au1xxx_dbdma_reset(u32 chanid);
312 u32 au1xxx_get_dma_residue(u32 chanid);
314 void au1xxx_dbdma_chan_free(u32 chanid);
315 void au1xxx_dbdma_dump(u32 chanid);
317 #endif /* _LANGUAGE_ASSEMBLY */
318 #endif /* _AU1000_DBDMA_H_ */