2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
9 * Copyright (C) 2000 FSMLabs, Inc.
14 #include <linux/config.h>
15 #include <linux/pagemap.h>
16 #include <linux/types.h>
17 #include <asm/addrspace.h>
18 #include <asm/pgtable-bits.h>
19 #include <asm/byteorder.h>
21 #ifdef CONFIG_SGI_IP27
22 extern unsigned long bus_to_baddr[256];
24 #define bus_to_baddr(bus, addr) (bus_to_baddr[(bus)->number] + (addr))
25 #define baddr_to_bus(bus, addr) ((addr) - bus_to_baddr[(bus)->number])
26 #define __swizzle_addr_w(port) ((port) ^ 2)
28 #define bus_to_baddr(bus, addr) (addr)
29 #define baddr_to_bus(bus, addr) (addr)
30 #define __swizzle_addr_w(port) (port)
34 * Slowdown I/O port space accesses for antique hardware.
36 #undef CONF_SLOWDOWN_IO
39 * Sane hardware offers swapping of I/O space accesses in hardware; less
40 * sane hardware forces software to fiddle with this. Totally insane hardware
41 * introduces special cases like:
43 * IP22 seems braindead enough to swap 16-bits values in hardware, but not
44 * 32-bits. Go figure... Can't tell without documentation.
46 * We only do the swapping to keep the kernel config bits of bi-endian
47 * machines a bit saner.
49 #if defined(CONFIG_SWAP_IO_SPACE_W) && defined(__MIPSEB__)
50 #define __ioswab16(x) swab16(x)
52 #define __ioswab16(x) (x)
54 #if defined(CONFIG_SWAP_IO_SPACE_L) && defined(__MIPSEB__)
55 #define __ioswab32(x) swab32(x)
57 #define __ioswab32(x) (x)
61 * Change "struct page" to physical address.
63 #ifdef CONFIG_64BIT_PHYS_ADDR
64 #define page_to_phys(page) ((u64)(page - mem_map) << PAGE_SHIFT)
66 #define page_to_phys(page) ((page - mem_map) << PAGE_SHIFT)
69 #define IO_SPACE_LIMIT 0xffff
71 extern void * __ioremap(phys_t offset, phys_t size, unsigned long flags);
74 * ioremap - map bus memory into CPU space
75 * @offset: bus address of the memory
76 * @size: size of the resource to map
78 * ioremap performs a platform specific sequence of operations to
79 * make bus memory CPU accessible via the readb/readw/readl/writeb/
80 * writew/writel functions and the other mmio helpers. The returned
81 * address is not guaranteed to be usable directly as a virtual
85 #define ioremap(offset, size) \
86 __ioremap((offset), (size), _CACHE_UNCACHED)
89 * ioremap_nocache - map bus memory into CPU space
90 * @offset: bus address of the memory
91 * @size: size of the resource to map
93 * ioremap_nocache performs a platform specific sequence of operations to
94 * make bus memory CPU accessible via the readb/readw/readl/writeb/
95 * writew/writel functions and the other mmio helpers. The returned
96 * address is not guaranteed to be usable directly as a virtual
99 * This version of ioremap ensures that the memory is marked uncachable
100 * on the CPU as well as honouring existing caching rules from things like
101 * the PCI bus. Note that there are other caches and buffers on many
102 * busses. In paticular driver authors should read up on PCI writes
104 * It's useful if some control registers are in such an area and
105 * write combining or read caching is not desirable:
107 #define ioremap_nocache(offset, size) \
108 __ioremap((offset), (size), _CACHE_UNCACHED)
109 #define ioremap_cacheable_cow(offset, size) \
110 __ioremap((offset), (size), _CACHE_CACHABLE_COW)
111 #define ioremap_uncached_accelerated(offset, size) \
112 __ioremap((offset), (size), _CACHE_UNCACHED_ACCELERATED)
114 extern void iounmap(void *addr);
117 * XXX We need system specific versions of these to handle EISA address bits
119 * XXX more SNI hacks.
121 #define readb(addr) (*(volatile unsigned char *)(addr))
122 #define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
123 #define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
125 #define __raw_readb(addr) (*(volatile unsigned char *)(addr))
126 #define __raw_readw(addr) (*(volatile unsigned short *)(addr))
127 #define __raw_readl(addr) (*(volatile unsigned int *)(addr))
129 #define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
130 #define writew(b,addr) ((*(volatile unsigned short *)(addr)) = (__ioswab16(b)))
131 #define writel(b,addr) ((*(volatile unsigned int *)(addr)) = (__ioswab32(b)))
133 #define __raw_writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
134 #define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w))
135 #define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l))
138 * TODO: Should use variants that don't do prefetching.
140 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
141 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
142 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
145 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
146 * for the processor. This implies the assumption that there is only
147 * one of these busses.
149 extern unsigned long isa_slot_offset;
152 * ISA space is 'always mapped' on currently supported MIPS systems, no need
153 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
154 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
155 * are physical addresses. The following constant pointer can be
156 * used as the IO-area pointer (it can be iounmapped as well, so the
157 * analogy with PCI is quite large):
159 #define __ISA_IO_base ((char *)(isa_slot_offset))
161 #define isa_readb(a) readb(__ISA_IO_base + (a))
162 #define isa_readw(a) readw(__ISA_IO_base + (a))
163 #define isa_readl(a) readl(__ISA_IO_base + (a))
164 #define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
165 #define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
166 #define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
167 #define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
168 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
169 #define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
172 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
173 * just copy it. The net code will then do the checksum later.
175 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
176 #define isa_eth_io_copy_and_sum(a,b,c,d) eth_copy_and_sum((a),(b),(c),(d))
179 * check_signature - find BIOS signatures
180 * @io_addr: mmio address to check
181 * @signature: signature block
182 * @length: length of signature
184 * Perform a signature comparison with the mmio address io_addr. This
185 * address should have been obtained by ioremap.
186 * Returns 1 on a match.
188 static inline int check_signature(unsigned long io_addr,
189 const unsigned char *signature, int length)
193 if (readb(io_addr) != *signature)
205 * isa_check_signature - find BIOS signatures
206 * @io_addr: mmio address to check
207 * @signature: signature block
208 * @length: length of signature
210 * Perform a signature comparison with the ISA mmio address io_addr.
211 * Returns 1 on a match.
213 * This function is deprecated. New drivers should use ioremap and
217 static inline int isa_check_signature(unsigned long io_addr,
218 const unsigned char *signature, int length)
222 if (isa_readb(io_addr) != *signature)
234 * virt_to_phys - map virtual addresses to physical
235 * @address: address to remap
237 * The returned physical address is the physical (CPU) mapping for
238 * the memory address given. It is only valid to use this function on
239 * addresses directly mapped or allocated via kmalloc.
241 * This function does not give bus mappings for DMA transfers. In
242 * almost all conceivable cases a device driver should not be using
246 static inline unsigned long virt_to_phys(volatile void * address)
248 return (unsigned long)address - PAGE_OFFSET;
252 * phys_to_virt - map physical address to virtual
253 * @address: address to remap
255 * The returned virtual address is a current CPU mapping for
256 * the memory address given. It is only valid to use this function on
257 * addresses that have a kernel mapping
259 * This function does not handle bus mappings for DMA transfers. In
260 * almost all conceivable cases a device driver should not be using
264 static inline void * phys_to_virt(unsigned long address)
266 return (void *)(address + PAGE_OFFSET);
270 * IO bus memory addresses are also 1:1 with the physical address
272 static inline unsigned long virt_to_bus(volatile void * address)
274 return (unsigned long)address - PAGE_OFFSET;
277 static inline void * bus_to_virt(unsigned long address)
279 return (void *)(address + PAGE_OFFSET);
282 /* This is too simpleminded for more sophisticated than dumb hardware ... */
283 #define page_to_bus page_to_phys
286 * On MIPS I/O ports are memory mapped, so we access them using normal
287 * load/store instructions. mips_io_port_base is the virtual address to
288 * which all ports are being mapped. For sake of efficiency some code
289 * assumes that this is an address that can be loaded with a single lui
290 * instruction, so the lower 16 bits must be zero. Should be true on
291 * on any sane architecture; generic code does not use this assumption.
293 extern const unsigned long mips_io_port_base;
295 #define set_io_port_base(base) \
296 do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
298 #define __SLOW_DOWN_IO \
299 __asm__ __volatile__( \
301 : : "r" (mips_io_port_base));
303 #ifdef CONF_SLOWDOWN_IO
304 #ifdef REALLY_SLOW_IO
305 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
307 #define SLOW_DOWN_IO __SLOW_DOWN_IO
313 #define outb(val,port) \
315 *(volatile u8 *)(mips_io_port_base + (port)) = (val); \
318 #define outw(val,port) \
320 *(volatile u16 *)(mips_io_port_base + __swizzle_addr_w(port)) = \
324 #define outl(val,port) \
326 *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
329 #define outb_p(val,port) \
331 *(volatile u8 *)(mips_io_port_base + (port)) = (val); \
335 #define outw_p(val,port) \
337 *(volatile u16 *)(mips_io_port_base + __swizzle_addr_w(port)) = \
342 #define outl_p(val,port) \
344 *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
348 static inline unsigned char inb(unsigned long port)
350 return *(volatile u8 *)(mips_io_port_base + port);
353 static inline unsigned short inw(unsigned long port)
355 port = __swizzle_addr_w(port);
357 return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
360 static inline unsigned int inl(unsigned long port)
362 return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
365 static inline unsigned char inb_p(unsigned long port)
369 __val = *(volatile u8 *)(mips_io_port_base + port);
375 static inline unsigned short inw_p(unsigned long port)
379 port = __swizzle_addr_w(port);
380 __val = *(volatile u16 *)(mips_io_port_base + port);
383 return __ioswab16(__val);
386 static inline unsigned int inl_p(unsigned long port)
390 __val = *(volatile u32 *)(mips_io_port_base + port);
392 return __ioswab32(__val);
395 static inline void __outsb(unsigned long port, void *addr, unsigned int count)
398 outb(*(u8 *)addr, port);
403 static inline void __insb(unsigned long port, void *addr, unsigned int count)
406 *(u8 *)addr = inb(port);
411 static inline void __outsw(unsigned long port, void *addr, unsigned int count)
414 outw(*(u16 *)addr, port);
419 static inline void __insw(unsigned long port, void *addr, unsigned int count)
422 *(u16 *)addr = inw(port);
427 static inline void __outsl(unsigned long port, void *addr, unsigned int count)
430 outl(*(u32 *)addr, port);
435 static inline void __insl(unsigned long port, void *addr, unsigned int count)
438 *(u32 *)addr = inl(port);
443 #define outsb(port, addr, count) __outsb(port, addr, count)
444 #define insb(port, addr, count) __insb(port, addr, count)
445 #define outsw(port, addr, count) __outsw(port, addr, count)
446 #define insw(port, addr, count) __insw(port, addr, count)
447 #define outsl(port, addr, count) __outsl(port, addr, count)
448 #define insl(port, addr, count) __insl(port, addr, count)
451 * The caches on some architectures aren't dma-coherent and have need to
452 * handle this in software. There are three types of operations that
453 * can be applied to dma buffers.
455 * - dma_cache_wback_inv(start, size) makes caches and coherent by
456 * writing the content of the caches back to memory, if necessary.
457 * The function also invalidates the affected part of the caches as
458 * necessary before DMA transfers from outside to memory.
459 * - dma_cache_wback(start, size) makes caches and coherent by
460 * writing the content of the caches back to memory, if necessary.
461 * The function also invalidates the affected part of the caches as
462 * necessary before DMA transfers from outside to memory.
463 * - dma_cache_inv(start, size) invalidates the affected parts of the
464 * caches. Dirty lines of the caches may be written back or simply
465 * be discarded. This operation is necessary before dma operations
468 #ifdef CONFIG_NONCOHERENT_IO
470 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
471 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
472 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
474 #define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
475 #define dma_cache_wback(start,size) _dma_cache_wback(start,size)
476 #define dma_cache_inv(start,size) _dma_cache_inv(start,size)
478 #else /* Sane hardware */
480 #define dma_cache_wback_inv(start,size) \
481 do { (void) (start); (void) (size); } while (0)
482 #define dma_cache_wback(start,size) \
483 do { (void) (start); (void) (size); } while (0)
484 #define dma_cache_inv(start,size) \
485 do { (void) (start); (void) (size); } while (0)
487 #endif /* CONFIG_NONCOHERENT_IO */
489 #endif /* _ASM_IO_H */