include/asm-mips/mipsregs.h

   1 /*
   2  * This file is subject to the terms and conditions of the GNU General Public
   3  * License.  See the file "COPYING" in the main directory of this archive
   4  * for more details.
   5  *
   6  * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
   7  * Copyright (C) 2000 Silicon Graphics, Inc.
   8  * Modified for further R[236]000 support by Paul M. Antoine, 1996.
   9  * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  10  * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
  11  */
  12 #ifndef _ASM_MIPSREGS_H
  13 #define _ASM_MIPSREGS_H
  14
  15 #include <linux/config.h>
  16 #include <linux/linkage.h>
  17
  18 /*
  19  * The following macros are especially useful for __asm__
  20  * inline assembler.
  21  */
  22 #ifndef __STR
  23 #define __STR(x) #x
  24 #endif
  25 #ifndef STR
  26 #define STR(x) __STR(x)
  27 #endif
  28
  29 /*
  30  * Coprocessor 0 register names
  31  */
  32 #define CP0_INDEX $0
  33 #define CP0_RANDOM $1
  34 #define CP0_ENTRYLO0 $2
  35 #define CP0_ENTRYLO1 $3
  36 #define CP0_CONF $3
  37 #define CP0_CONTEXT $4
  38 #define CP0_PAGEMASK $5
  39 #define CP0_WIRED $6
  40 #define CP0_INFO $7
  41 #define CP0_BADVADDR $8
  42 #define CP0_COUNT $9
  43 #define CP0_ENTRYHI $10
  44 #define CP0_COMPARE $11
  45 #define CP0_STATUS $12
  46 #define CP0_CAUSE $13
  47 #define CP0_EPC $14
  48 #define CP0_PRID $15
  49 #define CP0_CONFIG $16
  50 #define CP0_LLADDR $17
  51 #define CP0_WATCHLO $18
  52 #define CP0_WATCHHI $19
  53 #define CP0_XCONTEXT $20
  54 #define CP0_FRAMEMASK $21
  55 #define CP0_DIAGNOSTIC $22
  56 #define CP0_DEBUG $23
  57 #define CP0_DEPC $24
  58 #define CP0_PERFORMANCE $25
  59 #define CP0_ECC $26
  60 #define CP0_CACHEERR $27
  61 #define CP0_TAGLO $28
  62 #define CP0_TAGHI $29
  63 #define CP0_ERROREPC $30
  64 #define CP0_DESAVE $31
  65
  66 /*
  67  * R4640/R4650 cp0 register names.  These registers are listed
  68  * here only for completeness; without MMU these CPUs are not useable
  69  * by Linux.  A future ELKS port might take make Linux run on them
  70  * though ...
  71  */
  72 #define CP0_IBASE $0
  73 #define CP0_IBOUND $1
  74 #define CP0_DBASE $2
  75 #define CP0_DBOUND $3
  76 #define CP0_CALG $17
  77 #define CP0_IWATCH $18
  78 #define CP0_DWATCH $19
  79
  80 /*
  81  * Coprocessor 0 Set 1 register names
  82  */
  83 #define CP0_S1_DERRADDR0  $26
  84 #define CP0_S1_DERRADDR1  $27
  85 #define CP0_S1_INTCONTROL $20
  86
  87 /*
  88  *  TX39 Series
  89  */
  90 #define CP0_TX39_CACHE  $7
  91
  92 /*
  93  * Coprocessor 1 (FPU) register names
  94  */
  95 #define CP1_REVISION   $0
  96 #define CP1_STATUS     $31
  97
  98 /*
  99  * FPU Status Register Values
 100  */
 101 /*
 102  * Status Register Values
 103  */
 104
 105 #define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
 106 #define FPU_CSR_COND    0x00800000      /* $fcc0 */
 107 #define FPU_CSR_COND0   0x00800000      /* $fcc0 */
 108 #define FPU_CSR_COND1   0x02000000      /* $fcc1 */
 109 #define FPU_CSR_COND2   0x04000000      /* $fcc2 */
 110 #define FPU_CSR_COND3   0x08000000      /* $fcc3 */
 111 #define FPU_CSR_COND4   0x10000000      /* $fcc4 */
 112 #define FPU_CSR_COND5   0x20000000      /* $fcc5 */
 113 #define FPU_CSR_COND6   0x40000000      /* $fcc6 */
 114 #define FPU_CSR_COND7   0x80000000      /* $fcc7 */
 115
 116 /*
 117  * X the exception cause indicator
 118  * E the exception enable
 119  * S the sticky/flag bit
 120 */
 121 #define FPU_CSR_ALL_X 0x0003f000
 122 #define FPU_CSR_UNI_X   0x00020000
 123 #define FPU_CSR_INV_X   0x00010000
 124 #define FPU_CSR_DIV_X   0x00008000
 125 #define FPU_CSR_OVF_X   0x00004000
 126 #define FPU_CSR_UDF_X   0x00002000
 127 #define FPU_CSR_INE_X   0x00001000
 128
 129 #define FPU_CSR_ALL_E   0x00000f80
 130 #define FPU_CSR_INV_E   0x00000800
 131 #define FPU_CSR_DIV_E   0x00000400
 132 #define FPU_CSR_OVF_E   0x00000200
 133 #define FPU_CSR_UDF_E   0x00000100
 134 #define FPU_CSR_INE_E   0x00000080
 135
 136 #define FPU_CSR_ALL_S   0x0000007c
 137 #define FPU_CSR_INV_S   0x00000040
 138 #define FPU_CSR_DIV_S   0x00000020
 139 #define FPU_CSR_OVF_S   0x00000010
 140 #define FPU_CSR_UDF_S   0x00000008
 141 #define FPU_CSR_INE_S   0x00000004
 142
 143 /* rounding mode */
 144 #define FPU_CSR_RN      0x0     /* nearest */
 145 #define FPU_CSR_RZ      0x1     /* towards zero */
 146 #define FPU_CSR_RU      0x2     /* towards +Infinity */
 147 #define FPU_CSR_RD      0x3     /* towards -Infinity */
 148
 149
 150 /*
 151  * Values for PageMask register
 152  */
 153 #ifdef CONFIG_CPU_VR41XX
 154
 155 /* Why doesn't stupidity hurt ... */
 156
 157 #define PM_1K           0x00000000
 158 #define PM_4K           0x00001800
 159 #define PM_16K          0x00007800
 160 #define PM_64K          0x0001f800
 161 #define PM_256K         0x0007f800
 162
 163 #else
 164
 165 #define PM_4K           0x00000000
 166 #define PM_16K          0x00006000
 167 #define PM_64K          0x0001e000
 168 #define PM_256K         0x0007e000
 169 #define PM_1M           0x001fe000
 170 #define PM_4M           0x007fe000
 171 #define PM_16M          0x01ffe000
 172 #define PM_64M          0x07ffe000
 173 #define PM_256M         0x1fffe000
 174
 175 #endif
 176
 177 /*
 178  * Values used for computation of new tlb entries
 179  */
 180 #define PL_4K           12
 181 #define PL_16K          14
 182 #define PL_64K          16
 183 #define PL_256K         18
 184 #define PL_1M           20
 185 #define PL_4M           22
 186 #define PL_16M          24
 187 #define PL_64M          26
 188 #define PL_256M         28
 189
 190 /*
 191  * R4x00 interrupt enable / cause bits
 192  */
 193 #define IE_SW0          (1<< 8)
 194 #define IE_SW1          (1<< 9)
 195 #define IE_IRQ0         (1<<10)
 196 #define IE_IRQ1         (1<<11)
 197 #define IE_IRQ2         (1<<12)
 198 #define IE_IRQ3         (1<<13)
 199 #define IE_IRQ4         (1<<14)
 200 #define IE_IRQ5         (1<<15)
 201
 202 /*
 203  * R4x00 interrupt cause bits
 204  */
 205 #define C_SW0           (1<< 8)
 206 #define C_SW1           (1<< 9)
 207 #define C_IRQ0          (1<<10)
 208 #define C_IRQ1          (1<<11)
 209 #define C_IRQ2          (1<<12)
 210 #define C_IRQ3          (1<<13)
 211 #define C_IRQ4          (1<<14)
 212 #define C_IRQ5          (1<<15)
 213
 214 /*
 215  * Bitfields in the R4xx0 cp0 status register
 216  */
 217 #define ST0_IE                  0x00000001
 218 #define ST0_EXL                 0x00000002
 219 #define ST0_ERL                 0x00000004
 220 #define ST0_KSU                 0x00000018
 221 #  define KSU_USER              0x00000010
 222 #  define KSU_SUPERVISOR        0x00000008
 223 #  define KSU_KERNEL            0x00000000
 224 #define ST0_UX                  0x00000020
 225 #define ST0_SX                  0x00000040
 226 #define ST0_KX                  0x00000080
 227 #define ST0_DE                  0x00010000
 228 #define ST0_CE                  0x00020000
 229
 230 /*
 231  * Bitfields in the R[23]000 cp0 status register.
 232  */
 233 #define ST0_IEC                 0x00000001
 234 #define ST0_KUC                 0x00000002
 235 #define ST0_IEP                 0x00000004
 236 #define ST0_KUP                 0x00000008
 237 #define ST0_IEO                 0x00000010
 238 #define ST0_KUO                 0x00000020
 239 /* bits 6 & 7 are reserved on R[23]000 */
 240 #define ST0_ISC                 0x00010000
 241 #define ST0_SWC                 0x00020000
 242 #define ST0_CM                  0x00080000
 243
 244 /*
 245  * Bits specific to the R4640/R4650
 246  */
 247 #define ST0_UM                 (1   <<  4)
 248 #define ST0_IL                 (1   << 23)
 249 #define ST0_DL                 (1   << 24)
 250
 251 /*
 252  * Bitfields in the TX39 family CP0 Configuration Register 3
 253  */
 254 #define TX39_CONF_ICS_SHIFT     19
 255 #define TX39_CONF_ICS_MASK      0x00380000
 256 #define TX39_CONF_ICS_1KB       0x00000000
 257 #define TX39_CONF_ICS_2KB       0x00080000
 258 #define TX39_CONF_ICS_4KB       0x00100000
 259 #define TX39_CONF_ICS_8KB       0x00180000
 260 #define TX39_CONF_ICS_16KB      0x00200000
 261
 262 #define TX39_CONF_DCS_SHIFT     16
 263 #define TX39_CONF_DCS_MASK      0x00070000
 264 #define TX39_CONF_DCS_1KB       0x00000000
 265 #define TX39_CONF_DCS_2KB       0x00010000
 266 #define TX39_CONF_DCS_4KB       0x00020000
 267 #define TX39_CONF_DCS_8KB       0x00030000
 268 #define TX39_CONF_DCS_16KB      0x00040000
 269
 270 #define TX39_CONF_CWFON         0x00004000
 271 #define TX39_CONF_WBON          0x00002000
 272 #define TX39_CONF_RF_SHIFT      10
 273 #define TX39_CONF_RF_MASK       0x00000c00
 274 #define TX39_CONF_DOZE          0x00000200
 275 #define TX39_CONF_HALT          0x00000100
 276 #define TX39_CONF_LOCK          0x00000080
 277 #define TX39_CONF_ICE           0x00000020
 278 #define TX39_CONF_DCE           0x00000010
 279 #define TX39_CONF_IRSIZE_SHIFT  2
 280 #define TX39_CONF_IRSIZE_MASK   0x0000000c
 281 #define TX39_CONF_DRSIZE_SHIFT  0
 282 #define TX39_CONF_DRSIZE_MASK   0x00000003
 283
 284 /*
 285  * Status register bits available in all MIPS CPUs.
 286  */
 287 #define ST0_IM                  0x0000ff00
 288 #define  STATUSB_IP0            8
 289 #define  STATUSF_IP0            (1   <<  8)
 290 #define  STATUSB_IP1            9
 291 #define  STATUSF_IP1            (1   <<  9)
 292 #define  STATUSB_IP2            10
 293 #define  STATUSF_IP2            (1   << 10)
 294 #define  STATUSB_IP3            11
 295 #define  STATUSF_IP3            (1   << 11)
 296 #define  STATUSB_IP4            12
 297 #define  STATUSF_IP4            (1   << 12)
 298 #define  STATUSB_IP5            13
 299 #define  STATUSF_IP5            (1   << 13)
 300 #define  STATUSB_IP6            14
 301 #define  STATUSF_IP6            (1   << 14)
 302 #define  STATUSB_IP7            15
 303 #define  STATUSF_IP7            (1   << 15)
 304 #define  STATUSB_IP8            0
 305 #define  STATUSF_IP8            (1   << 0)
 306 #define  STATUSB_IP9            1
 307 #define  STATUSF_IP9            (1   << 1)
 308 #define  STATUSB_IP10           2
 309 #define  STATUSF_IP10           (1   << 2)
 310 #define  STATUSB_IP11           3
 311 #define  STATUSF_IP11           (1   << 3)
 312 #define  STATUSB_IP12           4
 313 #define  STATUSF_IP12           (1   << 4)
 314 #define  STATUSB_IP13           5
 315 #define  STATUSF_IP13           (1   << 5)
 316 #define  STATUSB_IP14           6
 317 #define  STATUSF_IP14           (1   << 6)
 318 #define  STATUSB_IP15           7
 319 #define  STATUSF_IP15           (1   << 7)
 320 #define ST0_CH                  0x00040000
 321 #define ST0_SR                  0x00100000
 322 #define ST0_TS                  0x00200000
 323 #define ST0_BEV                 0x00400000
 324 #define ST0_RE                  0x02000000
 325 #define ST0_FR                  0x04000000
 326 #define ST0_CU                  0xf0000000
 327 #define ST0_CU0                 0x10000000
 328 #define ST0_CU1                 0x20000000
 329 #define ST0_CU2                 0x40000000
 330 #define ST0_CU3                 0x80000000
 331 #define ST0_XX                  0x80000000      /* MIPS IV naming */
 332
 333 /*
 334  * Bitfields and bit numbers in the coprocessor 0 cause register.
 335  *
 336  * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
 337  */
 338 #define  CAUSEB_EXCCODE         2
 339 #define  CAUSEF_EXCCODE         (31  <<  2)
 340 #define  CAUSEB_IP              8
 341 #define  CAUSEF_IP              (255 <<  8)
 342 #define  CAUSEB_IP0             8
 343 #define  CAUSEF_IP0             (1   <<  8)
 344 #define  CAUSEB_IP1             9
 345 #define  CAUSEF_IP1             (1   <<  9)
 346 #define  CAUSEB_IP2             10
 347 #define  CAUSEF_IP2             (1   << 10)
 348 #define  CAUSEB_IP3             11
 349 #define  CAUSEF_IP3             (1   << 11)
 350 #define  CAUSEB_IP4             12
 351 #define  CAUSEF_IP4             (1   << 12)
 352 #define  CAUSEB_IP5             13
 353 #define  CAUSEF_IP5             (1   << 13)
 354 #define  CAUSEB_IP6             14
 355 #define  CAUSEF_IP6             (1   << 14)
 356 #define  CAUSEB_IP7             15
 357 #define  CAUSEF_IP7             (1   << 15)
 358 #define  CAUSEB_IV              23
 359 #define  CAUSEF_IV              (1   << 23)
 360 #define  CAUSEB_CE              28
 361 #define  CAUSEF_CE              (3   << 28)
 362 #define  CAUSEB_BD              31
 363 #define  CAUSEF_BD              (1   << 31)
 364
 365 /*
 366  * Bits in the coprozessor 0 config register.
 367  */
 368 #define CONF_CM_CACHABLE_NO_WA          0
 369 #define CONF_CM_CACHABLE_WA             1
 370 #define CONF_CM_UNCACHED                2
 371 #define CONF_CM_CACHABLE_NONCOHERENT    3
 372 #define CONF_CM_CACHABLE_CE             4
 373 #define CONF_CM_CACHABLE_COW            5
 374 #define CONF_CM_CACHABLE_CUW            6
 375 #define CONF_CM_CACHABLE_ACCELERATED    7
 376 #define CONF_CM_CMASK                   7
 377 #define CONF_CU                         (1 <<  3)
 378 #define CONF_DB                         (1 <<  4)
 379 #define CONF_IB                         (1 <<  5)
 380 #define CONF_SE                         (1 << 12)
 381 #define CONF_SC                         (1 << 17)
 382 #define CONF_AC                         (1 << 23)
 383 #define CONF_HALT                       (1 << 25)
 384
 385 /*
 386  * Bits in the TX49 coprozessor 0 config register.
 387  */
 388 #define TX49_CONF_DC                    (1 << 16)
 389 #define TX49_CONF_IC                    (1 << 17)  /* conflict with CONF_SC */
 390 #define TX49_CONF_HALT                  (1 << 18)
 391 #define TX49_CONF_CWFON                 (1 << 27)
 392
 393 /*
 394  * R10000 performance counter definitions.
 395  *
 396  * FIXME: The R10000 performance counter opens a nice way to implement CPU
 397  *        time accounting with a precission of one cycle.  I don't have
 398  *        R10000 silicon but just a manual, so ...
 399  */
 400
 401 /*
 402  * Events counted by counter #0
 403  */
 404 #define CE0_CYCLES                      0
 405 #define CE0_INSN_ISSUED                 1
 406 #define CE0_LPSC_ISSUED                 2
 407 #define CE0_S_ISSUED                    3
 408 #define CE0_SC_ISSUED                   4
 409 #define CE0_SC_FAILED                   5
 410 #define CE0_BRANCH_DECODED              6
 411 #define CE0_QW_WB_SECONDARY             7
 412 #define CE0_CORRECTED_ECC_ERRORS        8
 413 #define CE0_ICACHE_MISSES               9
 414 #define CE0_SCACHE_I_MISSES             10
 415 #define CE0_SCACHE_I_WAY_MISSPREDICTED  11
 416 #define CE0_EXT_INTERVENTIONS_REQ       12
 417 #define CE0_EXT_INVALIDATE_REQ          13
 418 #define CE0_VIRTUAL_COHERENCY_COND      14
 419 #define CE0_INSN_GRADUATED              15
 420
 421 /*
 422  * Events counted by counter #1
 423  */
 424 #define CE1_CYCLES                      0
 425 #define CE1_INSN_GRADUATED              1
 426 #define CE1_LPSC_GRADUATED              2
 427 #define CE1_S_GRADUATED                 3
 428 #define CE1_SC_GRADUATED                4
 429 #define CE1_FP_INSN_GRADUATED           5
 430 #define CE1_QW_WB_PRIMARY               6
 431 #define CE1_TLB_REFILL                  7
 432 #define CE1_BRANCH_MISSPREDICTED        8
 433 #define CE1_DCACHE_MISS                 9
 434 #define CE1_SCACHE_D_MISSES             10
 435 #define CE1_SCACHE_D_WAY_MISSPREDICTED  11
 436 #define CE1_EXT_INTERVENTION_HITS       12
 437 #define CE1_EXT_INVALIDATE_REQ          13
 438 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS  14
 439 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
 440
 441 /*
 442  * These flags define in which priviledge mode the counters count events
 443  */
 444 #define CEB_USER        8       /* Count events in user mode, EXL = ERL = 0 */
 445 #define CEB_SUPERVISOR  4       /* Count events in supvervisor mode EXL = ERL = 0 */
 446 #define CEB_KERNEL      2       /* Count events in kernel mode EXL = ERL = 0 */
 447 #define CEB_EXL         1       /* Count events with EXL = 1, ERL = 0 */
 448
 449 #ifndef __ASSEMBLY__
 450
 451 /*
 452  * Functions to access the r10k performance counter and control registers
 453  */
 454 #define read_r10k_perf_cntr(counter)                            \
 455 ({ unsigned int __res;                                          \
 456         __asm__ __volatile__(                                   \
 457         "mfpc\t%0, "STR(counter)                                \
 458         : "=r" (__res));                                        \
 459         __res;})
 460
 461 #define write_r10k_perf_cntr(counter,val)                       \
 462         __asm__ __volatile__(                                   \
 463         "mtpc\t%0, "STR(counter)                                \
 464         : : "r" (val));
 465
 466 #define read_r10k_perf_cntl(counter)                            \
 467 ({ unsigned int __res;                                          \
 468         __asm__ __volatile__(                                   \
 469         "mfps\t%0, "STR(counter)                                \
 470         : "=r" (__res));                                        \
 471         __res;})
 472
 473 #define write_r10k_perf_cntl(counter,val)                       \
 474         __asm__ __volatile__(                                   \
 475         "mtps\t%0, "STR(counter)                                \
 476         : : "r" (val));
 477
 478 /*
 479  * Macros to access the system control coprocessor
 480  */
 481 #define read_32bit_cp0_register(source)                         \
 482 ({ int __res;                                                   \
 483         __asm__ __volatile__(                                   \
 484         ".set\tpush\n\t"                                        \
 485         ".set\treorder\n\t"                                     \
 486         "mfc0\t%0,"STR(source)"\n\t"                            \
 487         ".set\tpop"                                             \
 488         : "=r" (__res));                                        \
 489         __res;})
 490
 491 #define read_32bit_cp0_set1_register(source)                    \
 492 ({ int __res;                                                   \
 493         __asm__ __volatile__(                                   \
 494         ".set\tpush\n\t"                                        \
 495         ".set\treorder\n\t"                                     \
 496         "cfc0\t%0,"STR(source)"\n\t"                            \
 497         ".set\tpop"                                             \
 498         : "=r" (__res));                                        \
 499         __res;})
 500
 501 /*
 502  * For now use this only with interrupts disabled!
 503  */
 504 #define read_64bit_cp0_register(source)                         \
 505 ({ unsigned long __res;                                         \
 506         __asm__ __volatile__(                                   \
 507         ".set\tmips3\n\t"                                       \
 508         "dmfc0\t%0,"STR(source)"\n\t"                           \
 509         ".set\tmips0"                                           \
 510         : "=r" (__res));                                        \
 511         __res;})
 512
 513 #define write_32bit_cp0_register(register,value)                \
 514         __asm__ __volatile__(                                   \
 515         "mtc0\t%0,"STR(register)"\n\t"                          \
 516         "nop"                                                   \
 517         : : "r" (value));
 518
 519 #define write_32bit_cp0_set1_register(register,value)           \
 520         __asm__ __volatile__(                                   \
 521         "ctc0\t%0,"STR(register)"\n\t"                          \
 522         "nop"                                                   \
 523         : : "r" (value));
 524
 525 #define write_64bit_cp0_register(register,value)                \
 526         __asm__ __volatile__(                                   \
 527         ".set\tmips3\n\t"                                       \
 528         "dmtc0\t%0,"STR(register)"\n\t"                         \
 529         ".set\tmips0"                                           \
 530         : : "r" (value))
 531
 532 /*
 533  * This should be changed when we get a compiler that support the MIPS32 ISA.
 534  */
 535 #define read_mips32_cp0_config1()                               \
 536 ({ int __res;                                                   \
 537         __asm__ __volatile__(                                   \
 538         ".set\tnoreorder\n\t"                                   \
 539         ".set\tnoat\n\t"                                        \
 540         "#.set\tmips64\n\t"                                     \
 541         "#mfc0\t$1, $16, 1\n\t"                                 \
 542         "#.set\tmips0\n\t"                                      \
 543         ".word\t0x40018001\n\t"                                 \
 544         "move\t%0,$1\n\t"                                       \
 545         ".set\tat\n\t"                                          \
 546         ".set\treorder"                                         \
 547         :"=r" (__res));                                         \
 548         __res;})
 549
 550 /*
 551  * Macros to access the floating point coprocessor control registers
 552  */
 553 #define read_32bit_cp1_register(source)                         \
 554 ({ int __res;                                                   \
 555         __asm__ __volatile__(                                   \
 556         ".set\tpush\n\t"                                        \
 557         ".set\treorder\n\t"                                     \
 558         "cfc1\t%0,"STR(source)"\n\t"                            \
 559         ".set\tpop"                                             \
 560         : "=r" (__res));                                        \
 561         __res;})
 562
 563 /* TLB operations. */
 564 static inline void tlb_probe(void)
 565 {
 566         __asm__ __volatile__(
 567                 ".set push\n\t"
 568                 ".set reorder\n\t"
 569                 "tlbp\n\t"
 570                 ".set pop");
 571 }
 572
 573 static inline void tlb_read(void)
 574 {
 575         __asm__ __volatile__(
 576                 ".set push\n\t"
 577                 ".set reorder\n\t"
 578                 "tlbr\n\t"
 579                 ".set pop");
 580 }
 581
 582 static inline void tlb_write_indexed(void)
 583 {
 584         __asm__ __volatile__(
 585                 ".set push\n\t"
 586                 ".set reorder\n\t"
 587                 "tlbwi\n\t"
 588                 ".set pop");
 589 }
 590
 591 static inline void tlb_write_random(void)
 592 {
 593         __asm__ __volatile__(
 594                 ".set push\n\t"
 595                 ".set reorder\n\t"
 596                 "tlbwr\n\t"
 597                 ".set pop");
 598 }
 599
 600 /* Dealing with various CP0 mmu/cache related registers. */
 601
 602
 603 static inline unsigned long get_pagemask(void)
 604 {
 605         unsigned long val;
 606
 607         __asm__ __volatile__(
 608                 ".set push\n\t"
 609                 ".set reorder\n\t"
 610                 "mfc0 %0, $5\n\t"
 611                 ".set pop"
 612                 : "=r" (val));
 613         return val;
 614 }
 615
 616 static inline void set_pagemask(unsigned long val)
 617 {
 618         __asm__ __volatile__(
 619                 ".set push\n\t"
 620                 ".set reorder\n\t"
 621                 "mtc0 %z0, $5\n\t"
 622                 ".set pop"
 623                 : : "Jr" (val));
 624 }
 625
 626 #if defined(CONFIG_64BIT_PHYS_ADDR) && !defined(CONFIG_CPU_MIPS32)
 627
 628 #include <asm/system.h>
 629
 630 /*
 631  * These versions are only needed for systems with more than 38 bits of
 632  * physical address space.
 633  */
 634 static inline void set_entrylo0(unsigned long long val)
 635 {
 636         unsigned long flags;
 637
 638         __save_and_cli(flags);
 639         __asm__ __volatile__(
 640                 ".set\tmips3\n\t"
 641                 "dsll\t%L0, %L0, 32\n\t"
 642                 "dsrl\t%L0, %L0, 32\n\t"
 643                 "dsll\t%M0, %M0, 32\n\t"
 644                 "or\t%L0, %L0, %M0\n\t"
 645                 "dmtc0\t%L0, $2\n\t"
 646                 ".set\tmips0"
 647                 : : "r" (val));
 648         __restore_flags(flags);
 649 }
 650
 651 static inline void set_entrylo1(unsigned long long val)
 652 {
 653         unsigned long flags;
 654
 655         __save_and_cli(flags);
 656         __asm__ __volatile__(
 657                 ".set\tmips3\n\t"
 658                 "dsll\t%L0, %L0, 32\n\t"
 659                 "dsrl\t%L0, %L0, 32\n\t"
 660                 "dsll\t%M0, %M0, 32\n\t"
 661                 "or\t%L0, %L0, %M0\n\t"
 662                 "dmtc0\t%L0, $3\n\t"
 663                 ".set\tmips0"
 664                 : : "r" (val));
 665         __restore_flags(flags);
 666 }
 667
 668 static inline unsigned long long get_entrylo0(void)
 669 {
 670         unsigned long flags, val;
 671
 672         __save_and_cli(flags);
 673         __asm__ __volatile__(
 674                 ".set\tmips3\n\t"
 675                 "dmfc0\t%M0, $2\n\t"
 676                 "dsll\t%L0, %M0, 32\n\t"
 677                 "dsrl\t%M0, %M0, 32\n\t"
 678                 "dsrl\t%L0, %L0, 32\n\t"
 679                 ".set\tmips0"
 680                 : "=r" (val));
 681         __restore_flags(flags);
 682
 683         return val;
 684 }
 685
 686 static inline unsigned long long get_entrylo1(void)
 687 {
 688         unsigned long flags, val;
 689
 690         __save_and_cli(flags);
 691         __asm__ __volatile__(
 692                 ".set\tmips3\n\t"
 693                 "dmfc0\t%M0, $3\n\t"
 694                 "dsrl\t%L0, %M0, 32\n\t"
 695                 "dsrl\t%M0, %M0, 32\n\t"
 696                 "dsll\t%L0, %L0, 32\n\t"
 697                 ".set\tmips0"
 698                 : "=r" (val));
 699         __restore_flags(flags);
 700
 701         return val;
 702 }
 703
 704 #else
 705
 706 static inline void set_entrylo0(unsigned long val)
 707 {
 708         __asm__ __volatile__(
 709                 ".set push\n\t"
 710                 ".set reorder\n\t"
 711                 "mtc0 %z0, $2\n\t"
 712                 ".set pop"
 713                 : : "Jr" (val));
 714 }
 715
 716 static inline void set_entrylo1(unsigned long val)
 717 {
 718         __asm__ __volatile__(
 719                 ".set push\n\t"
 720                 ".set reorder\n\t"
 721                 "mtc0 %z0, $3\n\t"
 722                 ".set pop"
 723                 : : "Jr" (val));
 724 }
 725
 726 static inline unsigned long get_entrylo0(void)
 727 {
 728         unsigned long val;
 729
 730         __asm__ __volatile__(
 731                 ".set push\n\t"
 732                 ".set reorder\n\t"
 733                 "mfc0 %0, $2\n\t"
 734                 ".set pop" : "=r" (val));
 735
 736         return val;
 737 }
 738
 739 static inline unsigned long get_entrylo1(void)
 740 {
 741         unsigned long val;
 742
 743         __asm__ __volatile__(
 744                 ".set push\n\t"
 745                 ".set reorder\n\t"
 746                 "mfc0 %0, $3\n\t"
 747                 ".set pop" : "=r" (val));
 748
 749         return val;
 750 }
 751
 752 #endif
 753
 754 /* CP0_ENTRYHI register */
 755 static inline unsigned long get_entryhi(void)
 756 {
 757         unsigned long val;
 758
 759         __asm__ __volatile__(
 760                 ".set push\n\t"
 761                 ".set reorder\n\t"
 762                 "mfc0 %0, $10\n\t"
 763                 ".set pop"
 764                 : "=r" (val));
 765
 766         return val;
 767 }
 768
 769 static inline void set_entryhi(unsigned long val)
 770 {
 771         __asm__ __volatile__(
 772                 ".set push\n\t"
 773                 ".set reorder\n\t"
 774                 "mtc0 %z0, $10\n\t"
 775                 ".set pop"
 776                 : : "Jr" (val));
 777 }
 778
 779 /* CP0_INDEX register */
 780 static inline unsigned long get_index(void)
 781 {
 782         unsigned long val;
 783
 784         __asm__ __volatile__(
 785                 ".set push\n\t"
 786                 ".set reorder\n\t"
 787                 "mfc0 %0, $0\n\t"
 788                 ".set pop"
 789                 : "=r" (val));
 790         return val;
 791 }
 792
 793 static inline void set_index(unsigned long val)
 794 {
 795         __asm__ __volatile__(
 796                 ".set push\n\t"
 797                 ".set reorder\n\t"
 798                 "mtc0 %z0, $0\n\t"
 799                 ".set pop"
 800                 : : "Jr" (val));
 801 }
 802
 803 /* CP0_WIRED register */
 804 static inline unsigned long get_wired(void)
 805 {
 806         unsigned long val;
 807
 808         __asm__ __volatile__(
 809                 ".set push\n\t"
 810                 ".set reorder\n\t"
 811                 "mfc0 %0, $6\n\t"
 812                 ".set pop"
 813                 : "=r" (val));
 814         return val;
 815 }
 816
 817 static inline void set_wired(unsigned long val)
 818 {
 819         __asm__ __volatile__(
 820                 ".set push\n\t"
 821                 ".set reorder\n\t"
 822                 "mtc0 %z0, $6\n\t"
 823                 ".set pop"
 824                 : : "Jr" (val));
 825 }
 826
 827 /* CP0_STATUS register */
 828 static inline unsigned int get_status(void)
 829 {
 830         unsigned long val;
 831
 832         __asm__ __volatile__(
 833                 ".set push\n\t"
 834                 ".set reorder\n\t"
 835                 "mfc0 %0, $12\n\t"
 836                 ".set pop"
 837                 : "=r" (val));
 838         return val;
 839 }
 840
 841 static inline void set_status(unsigned long val)
 842 {
 843         __asm__ __volatile__(
 844                 ".set push\n\t"
 845                 ".set reorder\n\t"
 846                 "mtc0 %z0, $12\n\t"
 847                 ".set pop"
 848                 : : "Jr" (val));
 849 }
 850
 851 static inline unsigned long get_info(void)
 852 {
 853         unsigned long val;
 854
 855         __asm__(
 856                 ".set push\n\t"
 857                 ".set reorder\n\t"
 858                 "mfc0 %0, $7\n\t"
 859                 ".set pop"
 860                 : "=r" (val));
 861         return val;
 862 }
 863
 864 /* CP0_TAGLO and CP0_TAGHI registers */
 865 static inline unsigned long get_taglo(void)
 866 {
 867         unsigned long val;
 868
 869         __asm__ __volatile__(
 870                 ".set push\n\t"
 871                 ".set reorder\n\t"
 872                 "mfc0 %0, $28\n\t"
 873                 ".set pop"
 874                 : "=r" (val));
 875         return val;
 876 }
 877
 878 static inline void set_taglo(unsigned long val)
 879 {
 880         __asm__ __volatile__(
 881                 ".set push\n\t"
 882                 ".set reorder\n\t"
 883                 "mtc0 %z0, $28\n\t"
 884                 ".set pop"
 885                 : : "Jr" (val));
 886 }
 887
 888 static inline unsigned long get_taghi(void)
 889 {
 890         unsigned long val;
 891
 892         __asm__ __volatile__(
 893                 ".set push\n\t"
 894                 ".set reorder\n\t"
 895                 "mfc0 %0, $29\n\t"
 896                 ".set pop"
 897                 : "=r" (val));
 898         return val;
 899 }
 900
 901 static inline void set_taghi(unsigned long val)
 902 {
 903         __asm__ __volatile__(
 904                 ".set push\n\t"
 905                 ".set reorder\n\t"
 906                 "mtc0 %z0, $29\n\t"
 907                 ".set pop"
 908                 : : "Jr" (val));
 909 }
 910
 911 static inline unsigned long get_context(void)
 912 {
 913         unsigned long val;
 914
 915         __asm__ __volatile__(
 916                 ".set push\n\t"
 917                 ".set reorder\n\t"
 918                 "mfc0 %0, $4\n\t"
 919                 ".set pop"
 920                 : "=r" (val));
 921
 922         return val;
 923 }
 924
 925 static inline void set_context(unsigned long val)
 926 {
 927         __asm__ __volatile__(
 928                 ".set push\n\t"
 929                 ".set reorder\n\t"
 930                 "mtc0 %z0, $4\n\t"
 931                 ".set pop"
 932                 : : "Jr" (val));
 933 }
 934
 935 static inline unsigned long get_errorepc(void)
 936 {
 937         unsigned long val;
 938
 939         __asm__ __volatile__(
 940                 ".set push\n\t"
 941                 ".set reorder\n\t"
 942                 "mfc0 %0, $30\n\t"
 943                 ".set pop"
 944                 : "=r" (val));
 945
 946         return val;
 947 }
 948
 949 static inline void set_errorepc(unsigned long val)
 950 {
 951         __asm__ __volatile__(
 952                 ".set push\n\t"
 953                 ".set reorder\n\t"
 954                 "mtc0 %z0, $30\n\t"
 955                 ".set pop"
 956                 : : "Jr" (val));
 957 }
 958
 959 /*
 960  * Manipulate the status register.
 961  * Mostly used to access the interrupt bits.
 962  */
 963 #define __BUILD_SET_CP0(name,register)                          \
 964 static inline unsigned int                                      \
 965 set_cp0_##name(unsigned int set)                                \
 966 {                                                               \
 967         unsigned int res;                                       \
 968                                                                 \
 969         res = read_32bit_cp0_register(register);                \
 970         res |= set;                                             \
 971         write_32bit_cp0_register(register, res);                \
 972                                                                 \
 973         return res;                                             \
 974 }                                                               \
 975                                                                 \
 976 static inline unsigned int                                      \
 977 clear_cp0_##name(unsigned int clear)                            \
 978 {                                                               \
 979         unsigned int res;                                       \
 980                                                                 \
 981         res = read_32bit_cp0_register(register);                \
 982         res &= ~clear;                                          \
 983         write_32bit_cp0_register(register, res);                \
 984                                                                 \
 985         return res;                                             \
 986 }                                                               \
 987                                                                 \
 988 static inline unsigned int                                      \
 989 change_cp0_##name(unsigned int change, unsigned int new)        \
 990 {                                                               \
 991         unsigned int res;                                       \
 992                                                                 \
 993         res = read_32bit_cp0_register(register);                \
 994         res &= ~change;                                         \
 995         res |= (new & change);                                  \
 996         write_32bit_cp0_register(register, res);                \
 997                                                                 \
 998         return res;                                             \
 999 }
1000
1001 __BUILD_SET_CP0(status,CP0_STATUS)
1002 __BUILD_SET_CP0(cause,CP0_CAUSE)
1003 __BUILD_SET_CP0(config,CP0_CONFIG)
1004
1005 #define __enable_fpu()                                                  \
1006 do {                                                                    \
1007         set_cp0_status(ST0_CU1);                                        \
1008         asm("nop;nop;nop;nop");         /* max. hazard */               \
1009 } while (0)
1010
1011 #define __disable_fpu()                                                 \
1012 do {                                                                    \
1013         clear_cp0_status(ST0_CU1);                                      \
1014         /* We don't care about the cp0 hazard here  */                  \
1015 } while (0)
1016
1017 #define enable_fpu()                                                    \
1018 do {                                                                    \
1019         if (mips_cpu.options & MIPS_CPU_FPU)                            \
1020                 __enable_fpu();                                         \
1021 } while (0)
1022
1023 #define disable_fpu()                                                   \
1024 do {                                                                    \
1025         if (mips_cpu.options & MIPS_CPU_FPU)                            \
1026                 __disable_fpu();                                        \
1027 } while (0)
1028
1029 #endif /* !__ASSEMBLY__ */
1030
1031 #endif /* _ASM_MIPSREGS_H */