2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994 - 2002 by Ralf Baechle
7 * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
8 * Copyright (C) 2002 Maciej W. Rozycki
10 #ifndef _ASM_PGTABLE_BITS_H
11 #define _ASM_PGTABLE_BITS_H
13 #include <linux/config.h>
16 * Note that we shift the lower 32bits of each EntryLo[01] entry
17 * 6 bits to the left. That way we can convert the PFN into the
18 * physical address by a single 'and' operation and gain 6 additional
19 * bits for storing information which isn't present in a normal
22 * Similar to the Alpha port, we need to keep track of the ref
23 * and mod bits in software. We have a software "yeah you can read
24 * from this page" bit, and a hardware one which actually lets the
25 * process read from the page. On the same token we have a software
26 * writable bit and the real hardware one which actually lets the
27 * process write to the page, this keeps a mod bit via the hardware
30 * Certain revisions of the R4000 and R5000 have a bug where if a
31 * certain sequence occurs in the last 3 instructions of an executable
32 * page, and the following page is not mapped, the cpu can do
33 * unpredictable things. The code (when it is written) to deal with
34 * this problem will be in the update_mmu_cache() code for the r4k.
36 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
38 #define _PAGE_PRESENT (1<<6) /* implemented in software */
39 #define _PAGE_READ (1<<7) /* implemented in software */
40 #define _PAGE_WRITE (1<<8) /* implemented in software */
41 #define _PAGE_ACCESSED (1<<9) /* implemented in software */
42 #define _PAGE_MODIFIED (1<<10) /* implemented in software */
44 #define _PAGE_R4KBUG (1<<0) /* workaround for r4k bug */
45 #define _PAGE_GLOBAL (1<<0)
46 #define _PAGE_VALID (1<<1)
47 #define _PAGE_SILENT_READ (1<<1) /* synonym */
48 #define _PAGE_DIRTY (1<<2) /* The MIPS dirty bit */
49 #define _PAGE_SILENT_WRITE (1<<2)
50 #define _CACHE_MASK (7<<3)
52 #ifdef CONFIG_SOC_AU1X00
53 #define _CACHE_CACHABLE_COW (3<<3)
56 /* MIPS32 defines only values 2 and 3. The rest are implementation
59 #define _CACHE_UNCACHED (2<<3)
60 #define _CACHE_CACHABLE_NONCOHERENT (3<<3)
64 #define _PAGE_PRESENT (1<<0) /* implemented in software */
65 #define _PAGE_READ (1<<1) /* implemented in software */
66 #define _PAGE_WRITE (1<<2) /* implemented in software */
67 #define _PAGE_ACCESSED (1<<3) /* implemented in software */
68 #define _PAGE_MODIFIED (1<<4) /* implemented in software */
70 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
72 #define _PAGE_GLOBAL (1<<8)
73 #define _PAGE_VALID (1<<9)
74 #define _PAGE_SILENT_READ (1<<9) /* synonym */
75 #define _PAGE_DIRTY (1<<10) /* The MIPS dirty bit */
76 #define _PAGE_SILENT_WRITE (1<<10)
77 #define _CACHE_UNCACHED (1<<11)
78 #define _CACHE_MASK (1<<11)
79 #define _CACHE_CACHABLE_NONCOHERENT 0
82 #define _PAGE_R4KBUG (1<<5) /* workaround for r4k bug */
83 #define _PAGE_GLOBAL (1<<6)
84 #define _PAGE_VALID (1<<7)
85 #define _PAGE_SILENT_READ (1<<7) /* synonym */
86 #define _PAGE_DIRTY (1<<8) /* The MIPS dirty bit */
87 #define _PAGE_SILENT_WRITE (1<<8)
88 #define _CACHE_MASK (7<<9)
90 #if defined(CONFIG_CPU_SB1)
92 /* No penalty for being coherent on the SB1, so just
93 use it for "noncoherent" spaces, too. Shouldn't hurt. */
95 #define _CACHE_UNCACHED (2<<9)
96 #define _CACHE_CACHABLE_COW (5<<9)
97 #define _CACHE_CACHABLE_NONCOHERENT (5<<9)
98 #define _CACHE_UNCACHED_ACCELERATED (7<<9)
102 #define _CACHE_CACHABLE_NO_WA (0<<9) /* R4600 only */
103 #define _CACHE_CACHABLE_WA (1<<9) /* R4600 only */
104 #define _CACHE_UNCACHED (2<<9) /* R4[0246]00 */
105 #define _CACHE_CACHABLE_NONCOHERENT (3<<9) /* R4[0246]00 */
106 #define _CACHE_CACHABLE_CE (4<<9) /* R4[04]00MC only */
107 #define _CACHE_CACHABLE_COW (5<<9) /* R4[04]00MC only */
108 #define _CACHE_CACHABLE_CUW (6<<9) /* R4[04]00MC only */
109 #define _CACHE_UNCACHED_ACCELERATED (7<<9) /* R10000 only */
113 #endif /* defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR) */
115 #define __READABLE (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
116 #define __WRITEABLE (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
118 #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
120 #ifdef CONFIG_MIPS_UNCACHED
121 #define PAGE_CACHABLE_DEFAULT _CACHE_UNCACHED
122 #elif defined(CONFIG_NONCOHERENT_IO)
123 #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_NONCOHERENT
125 #define PAGE_CACHABLE_DEFAULT _CACHE_CACHABLE_COW
128 #if defined(CONFIG_CPU_MIPS32) && defined(CONFIG_64BIT_PHYS_ADDR)
129 #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 3)
131 #define CONF_CM_DEFAULT (PAGE_CACHABLE_DEFAULT >> 9)
134 #endif /* _ASM_PGTABLE_BITS_H */