2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle at alii
7 * Copyright (C) 1999 Silicon Graphics, Inc.
10 #define _ASM_PGTABLE_H
12 #include <linux/config.h>
13 #include <asm/addrspace.h>
16 #include <linux/linkage.h>
17 #include <asm/cachectl.h>
18 #include <asm/fixmap.h>
22 * - flush_cache_all() flushes entire cache
23 * - flush_cache_mm(mm) flushes the specified mm context's cache lines
24 * - flush_cache_page(mm, vmaddr) flushes a single page
25 * - flush_cache_range(mm, start, end) flushes a range of pages
26 * - flush_page_to_ram(page) write back kernel page to ram
27 * - flush_icache_range(start, end) flush a range of instructions
29 * - flush_cache_sigtramp() flush signal trampoline
30 * - flush_icache_all() flush the entire instruction cache
32 extern void (*_flush_cache_all)(void);
33 extern void (*___flush_cache_all)(void);
34 extern void (*_flush_cache_mm)(struct mm_struct *mm);
35 extern void (*_flush_cache_range)(struct mm_struct *mm, unsigned long start,
37 extern void (*_flush_cache_page)(struct vm_area_struct *vma,
39 extern void (*_flush_page_to_ram)(struct page * page);
40 extern void (*_flush_icache_range)(unsigned long start, unsigned long end);
41 extern void (*_flush_icache_page)(struct vm_area_struct *vma,
43 extern void (*_flush_cache_sigtramp)(unsigned long addr);
44 extern void (*_flush_icache_all)(void);
46 #define flush_dcache_page(page) do { } while (0)
48 #define flush_cache_all() _flush_cache_all()
49 #define __flush_cache_all() ___flush_cache_all()
50 #define flush_cache_mm(mm) _flush_cache_mm(mm)
51 #define flush_cache_range(mm,start,end) _flush_cache_range(mm,start,end)
52 #define flush_cache_page(vma,page) _flush_cache_page(vma, page)
53 #define flush_page_to_ram(page) _flush_page_to_ram(page)
55 #define flush_icache_range(start, end) _flush_icache_range(start,end)
56 #define flush_icache_user_range(vma, page, addr, len) \
57 _flush_icache_page((vma), (page))
58 #define flush_icache_page(vma, page) _flush_icache_page(vma, page)
60 #define flush_cache_sigtramp(addr) _flush_cache_sigtramp(addr)
61 #ifdef CONFIG_VTAG_ICACHE
62 #define flush_icache_all() _flush_icache_all()
64 #define flush_icache_all() do { } while(0)
68 * - add_wired_entry() add a fixed TLB entry, and move wired register
70 extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
71 unsigned long entryhi, unsigned long pagemask);
74 * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
75 * starting at the top and working down. This is for populating the
76 * TLB before trap_init() puts the TLB miss handler in place. It
77 * should be used only for entries matching the actual page tables,
78 * to prevent inconsistencies.
80 extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
81 unsigned long entryhi, unsigned long pagemask);
84 /* Basically we have the same two-level (which is the logical three level
85 * Linux page table layout folded) page tables as the i386. Some day
86 * when we have proper page coloring support we can have a 1% quicker
87 * tlb refill handling mechanism, but for now it is a bit slower but
88 * works even with the cache aliasing problem the R4k and above have.
91 /* PMD_SHIFT determines the size of the area a second-level page table can map */
92 #ifdef CONFIG_64BIT_PHYS_ADDR
97 #define PMD_SIZE (1UL << PMD_SHIFT)
98 #define PMD_MASK (~(PMD_SIZE-1))
100 /* PGDIR_SHIFT determines what a third-level page table entry can map */
101 #define PGDIR_SHIFT PMD_SHIFT
102 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
103 #define PGDIR_MASK (~(PGDIR_SIZE-1))
106 * Entries per page directory level: we use two-level, so
107 * we don't really have any PMD directory physically.
109 #ifdef CONFIG_64BIT_PHYS_ADDR
110 #define PTRS_PER_PTE 512
111 #define PTRS_PER_PMD 1
112 #define PTRS_PER_PGD 2048
115 #define PTRS_PER_PTE 1024
116 #define PTRS_PER_PMD 1
117 #define PTRS_PER_PGD 1024
121 #define USER_PTRS_PER_PGD (0x80000000UL/PGDIR_SIZE)
122 #define FIRST_USER_PGD_NR 0
124 #define VMALLOC_START KSEG2
125 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
128 # define VMALLOC_END (PKMAP_BASE-2*PAGE_SIZE)
130 # define VMALLOC_END (FIXADDR_START-2*PAGE_SIZE)
133 #include <asm/pgtable-bits.h>
135 #define PAGE_NONE __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
136 #define PAGE_SHARED __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
137 PAGE_CACHABLE_DEFAULT)
138 #define PAGE_COPY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
139 PAGE_CACHABLE_DEFAULT)
140 #define PAGE_READONLY __pgprot(_PAGE_PRESENT | _PAGE_READ | \
141 PAGE_CACHABLE_DEFAULT)
142 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
143 _PAGE_GLOBAL | PAGE_CACHABLE_DEFAULT)
144 #define PAGE_USERIO __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
145 PAGE_CACHABLE_DEFAULT)
146 #define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
147 __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
150 * MIPS can't do page protection for execute, and considers that the same like
151 * read. Also, write permissions imply read permissions. This is the closest
152 * we can get by reasonable means..
154 #define __P000 PAGE_NONE
155 #define __P001 PAGE_READONLY
156 #define __P010 PAGE_COPY
157 #define __P011 PAGE_COPY
158 #define __P100 PAGE_READONLY
159 #define __P101 PAGE_READONLY
160 #define __P110 PAGE_COPY
161 #define __P111 PAGE_COPY
163 #define __S000 PAGE_NONE
164 #define __S001 PAGE_READONLY
165 #define __S010 PAGE_SHARED
166 #define __S011 PAGE_SHARED
167 #define __S100 PAGE_READONLY
168 #define __S101 PAGE_READONLY
169 #define __S110 PAGE_SHARED
170 #define __S111 PAGE_SHARED
172 #ifdef CONFIG_64BIT_PHYS_ADDR
173 #define pte_ERROR(e) \
174 printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
176 #define pte_ERROR(e) \
177 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
179 #define pmd_ERROR(e) \
180 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
181 #define pgd_ERROR(e) \
182 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
184 extern unsigned long empty_zero_page;
185 extern unsigned long zero_page_mask;
187 #define ZERO_PAGE(vaddr) \
188 (virt_to_page(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask)))
190 extern void load_pgd(unsigned long pg_dir);
192 extern pmd_t invalid_pte_table[PAGE_SIZE/sizeof(pmd_t)];
195 * Conversion functions: convert a page and protection to a page entry,
196 * and a page entry and page directory to the page they refer to.
198 static inline unsigned long pmd_page(pmd_t pmd)
203 static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
205 pmd_val(*pmdp) = (((unsigned long) ptep) & PAGE_MASK);
208 static inline int pte_none(pte_t pte) { return !(pte_val(pte) & ~_PAGE_GLOBAL); }
209 static inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
211 /* Certain architectures need to do special things when pte's
212 * within a page table are directly modified. Thus, the following
213 * hook is made available.
215 static inline void set_pte(pte_t *ptep, pte_t pteval)
218 #if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
219 if (pte_val(pteval) & _PAGE_GLOBAL) {
220 pte_t *buddy = ptep_buddy(ptep);
222 * Make sure the buddy is global too (if it's !none,
223 * it better already be global)
225 if (pte_none(*buddy))
226 pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL;
231 static inline void pte_clear(pte_t *ptep)
233 #if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
234 /* Preserve global status for the pair */
235 if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
236 set_pte(ptep, __pte(_PAGE_GLOBAL));
239 set_pte(ptep, __pte(0));
243 * (pmds are folded into pgds so this doesn't get actually called,
244 * but the define is needed for a generic inline function.)
246 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
247 #define set_pgd(pgdptr, pgdval) (*(pgdptr) = pgdval)
250 * Empty pgd/pmd entries point to the invalid_pte_table.
252 static inline int pmd_none(pmd_t pmd)
254 return pmd_val(pmd) == (unsigned long) invalid_pte_table;
257 static inline int pmd_bad(pmd_t pmd)
259 return ((pmd_page(pmd) > (unsigned long) high_memory) ||
260 (pmd_page(pmd) < PAGE_OFFSET));
263 static inline int pmd_present(pmd_t pmd)
265 return (pmd_val(pmd) != (unsigned long) invalid_pte_table);
268 static inline void pmd_clear(pmd_t *pmdp)
270 pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
274 * The "pgd_xxx()" functions here are trivial for a folded two-level
275 * setup: the pgd is never bad, and a pmd always exists (as it's folded
276 * into the pgd entry)
278 static inline int pgd_none(pgd_t pgd) { return 0; }
279 static inline int pgd_bad(pgd_t pgd) { return 0; }
280 static inline int pgd_present(pgd_t pgd) { return 1; }
281 static inline void pgd_clear(pgd_t *pgdp) { }
284 * Permanent address of a page. Obviously must never be called on a highmem
287 #ifdef CONFIG_CPU_VR41XX
288 #define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> (PAGE_SHIFT + 2))))
290 #define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT)))
294 * The following only work if pte_present() is true.
295 * Undefined behaviour if not..
297 static inline int pte_read(pte_t pte) { return pte_val(pte) & _PAGE_READ; }
298 static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_WRITE; }
299 static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_MODIFIED; }
300 static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED; }
302 static inline pte_t pte_wrprotect(pte_t pte)
304 pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
308 static inline pte_t pte_rdprotect(pte_t pte)
310 pte_val(pte) &= ~(_PAGE_READ | _PAGE_SILENT_READ);
314 static inline pte_t pte_mkclean(pte_t pte)
316 pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
320 static inline pte_t pte_mkold(pte_t pte)
322 pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
326 static inline pte_t pte_mkwrite(pte_t pte)
328 pte_val(pte) |= _PAGE_WRITE;
329 if (pte_val(pte) & _PAGE_MODIFIED)
330 pte_val(pte) |= _PAGE_SILENT_WRITE;
334 static inline pte_t pte_mkread(pte_t pte)
336 pte_val(pte) |= _PAGE_READ;
337 if (pte_val(pte) & _PAGE_ACCESSED)
338 pte_val(pte) |= _PAGE_SILENT_READ;
342 static inline pte_t pte_mkdirty(pte_t pte)
344 pte_val(pte) |= _PAGE_MODIFIED;
345 if (pte_val(pte) & _PAGE_WRITE)
346 pte_val(pte) |= _PAGE_SILENT_WRITE;
351 * Macro to make mark a page protection value as "uncacheable". Note
352 * that "protection" is really a misnomer here as the protection value
353 * contains the memory attribute bits, dirty bits, and various other
356 #define pgprot_noncached pgprot_noncached
358 static inline pgprot_t pgprot_noncached(pgprot_t _prot)
360 unsigned long prot = pgprot_val(_prot);
362 prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
364 return __pgprot(prot);
367 static inline pte_t pte_mkyoung(pte_t pte)
369 pte_val(pte) |= _PAGE_ACCESSED;
370 if (pte_val(pte) & _PAGE_READ)
371 pte_val(pte) |= _PAGE_SILENT_READ;
376 * Conversion functions: convert a page and protection to a page entry,
377 * and a page entry and page directory to the page they refer to.
380 #ifdef CONFIG_CPU_VR41XX
381 #define mk_pte(page, pgprot) \
385 pte_val(__pte) = ((phys_t)(page - mem_map) << (PAGE_SHIFT + 2)) | \
386 pgprot_val(pgprot); \
391 #define mk_pte(page, pgprot) \
395 pte_val(__pte) = ((phys_t)(page - mem_map) << PAGE_SHIFT) | \
396 pgprot_val(pgprot); \
402 static inline pte_t mk_pte_phys(phys_t physpage, pgprot_t pgprot)
404 #ifdef CONFIG_CPU_VR41XX
405 return __pte((physpage << 2) | pgprot_val(pgprot));
407 return __pte(physpage | pgprot_val(pgprot));
411 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
413 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
416 #define page_pte(page) page_pte_prot(page, __pgprot(0))
418 #define __pgd_offset(address) pgd_index(address)
419 #define __pmd_offset(address) \
420 (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
422 /* to find an entry in a kernel page-table-directory */
423 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
425 #define pgd_index(address) ((address) >> PGDIR_SHIFT)
427 /* to find an entry in a page-table-directory */
428 static inline pgd_t *pgd_offset(struct mm_struct *mm, unsigned long address)
430 return mm->pgd + pgd_index(address);
433 /* Find an entry in the second-level page table.. */
434 static inline pmd_t *pmd_offset(pgd_t *dir, unsigned long address)
436 return (pmd_t *) dir;
439 /* Find an entry in the third-level page table.. */
440 static inline pte_t *pte_offset(pmd_t * dir, unsigned long address)
442 return (pte_t *) (pmd_page(*dir)) +
443 ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
446 extern int do_check_pgt_cache(int, int);
448 extern pgd_t swapper_pg_dir[1024];
449 extern void paging_init(void);
451 extern void update_mmu_cache(struct vm_area_struct *vma,
452 unsigned long address, pte_t pte);
454 /* Swap entries must have VALID and GLOBAL bits cleared. */
455 #if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
457 #define SWP_TYPE(x) (((x).val >> 1) & 0x7f)
458 #define SWP_OFFSET(x) ((x).val >> 10)
459 #define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 10) })
462 #define SWP_TYPE(x) (((x).val >> 1) & 0x1f)
463 #define SWP_OFFSET(x) ((x).val >> 8)
464 #define SWP_ENTRY(type,offset) ((swp_entry_t) { ((type) << 1) | ((offset) << 8) })
467 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
468 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
471 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
472 #define PageSkip(page) (0)
473 #define kern_addr_valid(addr) (1)
475 #include <asm-generic/pgtable.h>
478 * We provide our own get_unmapped area to cope with the virtual aliasing
479 * constraints placed on us by the cache architecture.
481 #define HAVE_ARCH_UNMAPPED_AREA
483 #define io_remap_page_range remap_page_range
486 * No page table caches to initialise
488 #define pgtable_cache_init() do { } while (0)
490 #endif /* _ASM_PGTABLE_H */