2 * This file is subject to the terms and conditions of the GNU General Public
3 * License. See the file "COPYING" in the main directory of this archive
6 * Copyright (C) 1994, 1995 Waldorf GmbH
7 * Copyright (C) 1994 - 2000 Ralf Baechle
8 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
13 #include <linux/config.h>
14 #include <asm/addrspace.h>
16 #include <asm/byteorder.h>
18 #ifdef CONFIG_MIPS_ATLAS
19 #include <asm/mips-boards/io.h>
22 #ifdef CONFIG_MIPS_MALTA
23 #include <asm/mips-boards/io.h>
26 #ifdef CONFIG_SGI_IP22
27 #include <asm/sgi/io.h>
30 #ifdef CONFIG_SGI_IP27
31 #include <asm/sn/io.h>
34 #ifdef CONFIG_SGI_IP32
35 #include <asm/ip32/io.h>
38 #ifdef CONFIG_SIBYTE_SB1250
39 #include <asm/sibyte/io.h>
42 #ifdef CONFIG_SGI_IP27
43 extern unsigned long bus_to_baddr[256];
45 #define bus_to_baddr(hwdev, addr) (bus_to_baddr[(hwdev)->bus->number] + (addr))
46 #define baddr_to_bus(hwdev, addr) ((addr) - bus_to_baddr[(hwdev)->bus->number])
48 #define bus_to_baddr(hwdev, addr) (addr)
49 #define baddr_to_bus(hwdev, addr) (addr)
53 * Slowdown I/O port space accesses for antique hardware.
55 #undef CONF_SLOWDOWN_IO
58 * Sane hardware offers swapping of I/O space accesses in hardware; less
59 * sane hardware forces software to fiddle with this ...
61 #if defined(CONFIG_SWAP_IO_SPACE) && defined(__MIPSEB__)
63 #define __ioswab8(x) (x)
64 #ifdef CONFIG_SGI_IP22
65 /* IP22 seems braindead enough to swap 16bits values in hardware, but
66 not 32bits. Go figure... Can't tell without documentation. */
67 #define __ioswab16(x) (x)
69 #define __ioswab16(x) swab16(x)
71 #define __ioswab32(x) swab32(x)
75 #define __ioswab8(x) (x)
76 #define __ioswab16(x) (x)
77 #define __ioswab32(x) (x)
82 * Change "struct page" to physical address.
84 #define page_to_phys(page) PAGE_TO_PA(page)
87 * ioremap - map bus memory into CPU space
88 * @offset: bus address of the memory
89 * @size: size of the resource to map
91 * ioremap performs a platform specific sequence of operations to
92 * make bus memory CPU accessible via the readb/readw/readl/writeb/
93 * writew/writel functions and the other mmio helpers. The returned
94 * address is not guaranteed to be usable directly as a virtual
97 static inline void * ioremap(unsigned long offset, unsigned long size)
99 return (void *) (IO_SPACE_BASE | offset);
103 * ioremap_nocache - map bus memory into CPU space
104 * @offset: bus address of the memory
105 * @size: size of the resource to map
107 * ioremap_nocache performs a platform specific sequence of operations to
108 * make bus memory CPU accessible via the readb/readw/readl/writeb/
109 * writew/writel functions and the other mmio helpers. The returned
110 * address is not guaranteed to be usable directly as a virtual
113 * This version of ioremap ensures that the memory is marked uncachable
114 * on the CPU as well as honouring existing caching rules from things like
115 * the PCI bus. Note that there are other caches and buffers on many
116 * busses. In paticular driver authors should read up on PCI writes
118 * It's useful if some control registers are in such an area and
119 * write combining or read caching is not desirable:
121 static inline void * ioremap_nocache (unsigned long offset, unsigned long size)
123 return (void *) (IO_SPACE_BASE | offset);
126 static inline void iounmap(void *addr)
130 #define readb(addr) (*(volatile unsigned char *)(addr))
131 #define readw(addr) __ioswab16((*(volatile unsigned short *)(addr)))
132 #define readl(addr) __ioswab32((*(volatile unsigned int *)(addr)))
134 #define __raw_readb(addr) (*(volatile unsigned char *)(addr))
135 #define __raw_readw(addr) (*(volatile unsigned short *)(addr))
136 #define __raw_readl(addr) (*(volatile unsigned int *)(addr))
138 #define writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (__ioswab8(b)))
139 #define writew(b,addr) ((*(volatile unsigned short *)(addr)) = (__ioswab16(b)))
140 #define writel(b,addr) ((*(volatile unsigned int *)(addr)) = (__ioswab32(b)))
142 #define __raw_writeb(b,addr) ((*(volatile unsigned char *)(addr)) = (b))
143 #define __raw_writew(w,addr) ((*(volatile unsigned short *)(addr)) = (w))
144 #define __raw_writel(l,addr) ((*(volatile unsigned int *)(addr)) = (l))
146 #define memset_io(a,b,c) memset((void *)(a),(b),(c))
147 #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c))
148 #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c))
150 /* The ISA versions are supplied by system specific code */
153 * On MIPS I/O ports are memory mapped, so we access them using normal
154 * load/store instructions. mips_io_port_base is the virtual address to
155 * which all ports are being mapped. For sake of efficiency some code
156 * assumes that this is an address that can be loaded with a single lui
157 * instruction, so the lower 16 bits must be zero. Should be true on
158 * on any sane architecture; generic code does not use this assumption.
160 extern const unsigned long mips_io_port_base;
162 #define set_io_port_base(base) \
163 do { * (unsigned long *) &mips_io_port_base = (base); } while (0)
165 #define __SLOW_DOWN_IO \
166 __asm__ __volatile__( \
168 : : "r" (mips_io_port_base));
170 #ifdef CONF_SLOWDOWN_IO
171 #ifdef REALLY_SLOW_IO
172 #define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
174 #define SLOW_DOWN_IO __SLOW_DOWN_IO
181 * virt_to_phys - map virtual addresses to physical
182 * @address: address to remap
184 * The returned physical address is the physical (CPU) mapping for
185 * the memory address given. It is only valid to use this function on
186 * addresses directly mapped or allocated via kmalloc.
188 * This function does not give bus mappings for DMA transfers. In
189 * almost all conceivable cases a device driver should not be using
193 static inline unsigned long virt_to_phys(volatile void * address)
195 return (unsigned long)address - PAGE_OFFSET;
199 * phys_to_virt - map physical address to virtual
200 * @address: address to remap
202 * The returned virtual address is a current CPU mapping for
203 * the memory address given. It is only valid to use this function on
204 * addresses that have a kernel mapping
206 * This function does not handle bus mappings for DMA transfers. In
207 * almost all conceivable cases a device driver should not be using
211 static inline void * phys_to_virt(unsigned long address)
213 return (void *)(address + PAGE_OFFSET);
217 * IO bus memory addresses are also 1:1 with the physical address
219 static inline unsigned long virt_to_bus(volatile void * address)
221 return (unsigned long)address - PAGE_OFFSET;
224 static inline void * bus_to_virt(unsigned long address)
226 return (void *)(address + PAGE_OFFSET);
230 /* This is too simpleminded for more sophisticated than dumb hardware ... */
231 #define page_to_bus page_to_phys
234 * isa_slot_offset is the address where E(ISA) busaddress 0 is mapped
235 * for the processor. This implies the assumption that there is only
236 * one of these busses.
238 extern unsigned long isa_slot_offset;
241 * ISA space is 'always mapped' on currently supported MIPS systems, no need
242 * to explicitly ioremap() it. The fact that the ISA IO space is mapped
243 * to PAGE_OFFSET is pure coincidence - it does not mean ISA values
244 * are physical addresses. The following constant pointer can be
245 * used as the IO-area pointer (it can be iounmapped as well, so the
246 * analogy with PCI is quite large):
248 #define __ISA_IO_base ((char *)(isa_slot_offset))
250 #define isa_readb(a) readb(__ISA_IO_base + (a))
251 #define isa_readw(a) readw(__ISA_IO_base + (a))
252 #define isa_readl(a) readl(__ISA_IO_base + (a))
253 #define isa_writeb(b,a) writeb(b,__ISA_IO_base + (a))
254 #define isa_writew(w,a) writew(w,__ISA_IO_base + (a))
255 #define isa_writel(l,a) writel(l,__ISA_IO_base + (a))
256 #define isa_memset_io(a,b,c) memset_io(__ISA_IO_base + (a),(b),(c))
257 #define isa_memcpy_fromio(a,b,c) memcpy_fromio((a),__ISA_IO_base + (b),(c))
258 #define isa_memcpy_toio(a,b,c) memcpy_toio(__ISA_IO_base + (a),(b),(c))
261 * We don't have csum_partial_copy_fromio() yet, so we cheat here and
262 * just copy it. The net code will then do the checksum later.
264 #define eth_io_copy_and_sum(skb,src,len,unused) memcpy_fromio((skb)->data,(src),(len))
267 * check_signature - find BIOS signatures
268 * @io_addr: mmio address to check
269 * @signature: signature block
270 * @length: length of signature
272 * Perform a signature comparison with the mmio address io_addr. This
273 * address should have been obtained by ioremap.
274 * Returns 1 on a match.
277 check_signature(unsigned long io_addr, const unsigned char *signature,
282 if (readb(io_addr) != *signature)
294 * isa_check_signature - find BIOS signatures
295 * @io_addr: mmio address to check
296 * @signature: signature block
297 * @length: length of signature
299 * Perform a signature comparison with the ISA mmio address io_addr.
300 * Returns 1 on a match.
302 * This function is deprecated. New drivers should use ioremap and
306 static inline int isa_check_signature(unsigned long io_addr,
307 const unsigned char *signature, int length)
311 if (isa_readb(io_addr) != *signature)
322 #define outb(val,port) \
324 *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
327 #define outw(val,port) \
329 *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
332 #define outl(val,port) \
334 *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
337 #define outb_p(val,port) \
339 *(volatile u8 *)(mips_io_port_base + (port)) = __ioswab8(val); \
343 #define outw_p(val,port) \
345 *(volatile u16 *)(mips_io_port_base + (port)) = __ioswab16(val);\
349 #define outl_p(val,port) \
351 *(volatile u32 *)(mips_io_port_base + (port)) = __ioswab32(val);\
355 static inline unsigned char inb(unsigned long port)
357 return __ioswab8(*(volatile u8 *)(mips_io_port_base + port));
360 static inline unsigned short inw(unsigned long port)
362 return __ioswab16(*(volatile u16 *)(mips_io_port_base + port));
365 static inline unsigned int inl(unsigned long port)
367 return __ioswab32(*(volatile u32 *)(mips_io_port_base + port));
370 static inline unsigned char inb_p(unsigned long port)
374 __val = *(volatile u8 *)(mips_io_port_base + port);
377 return __ioswab8(__val);
380 static inline unsigned short inw_p(unsigned long port)
384 __val = *(volatile u16 *)(mips_io_port_base + port);
387 return __ioswab16(__val);
390 static inline unsigned int inl_p(unsigned long port)
394 __val = *(volatile u32 *)(mips_io_port_base + port);
396 return __ioswab32(__val);
399 static inline void outsb(unsigned long port, void *addr, unsigned int count)
402 outb(*(u8 *)addr, port);
407 static inline void insb(unsigned long port, void *addr, unsigned int count)
410 *(u8 *)addr = inb(port);
415 static inline void outsw(unsigned long port, void *addr, unsigned int count)
418 outw(*(u16 *)addr, port);
423 static inline void insw(unsigned long port, void *addr, unsigned int count)
426 *(u16 *)addr = inw(port);
431 static inline void outsl(unsigned long port, void *addr, unsigned int count)
434 outl(*(u32 *)addr, port);
439 static inline void insl(unsigned long port, void *addr, unsigned int count)
442 *(u32 *)addr = inl(port);
448 * The caches on some architectures aren't dma-coherent and have need to
449 * handle this in software. There are three types of operations that
450 * can be applied to dma buffers.
452 * - dma_cache_wback_inv(start, size) makes caches and coherent by
453 * writing the content of the caches back to memory, if necessary.
454 * The function also invalidates the affected part of the caches as
455 * necessary before DMA transfers from outside to memory.
456 * - dma_cache_wback(start, size) makes caches and coherent by
457 * writing the content of the caches back to memory, if necessary.
458 * The function also invalidates the affected part of the caches as
459 * necessary before DMA transfers from outside to memory.
460 * - dma_cache_inv(start, size) invalidates the affected parts of the
461 * caches. Dirty lines of the caches may be written back or simply
462 * be discarded. This operation is necessary before dma operations
465 #ifdef CONFIG_NONCOHERENT_IO
467 extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
468 extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
469 extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
471 #define dma_cache_wback_inv(start,size) _dma_cache_wback_inv(start,size)
472 #define dma_cache_wback(start,size) _dma_cache_wback(start,size)
473 #define dma_cache_inv(start,size) _dma_cache_inv(start,size)
475 #else /* Sane hardware */
477 #define dma_cache_wback_inv(start,size) do { (start); (size); } while (0)
478 #define dma_cache_wback(start,size) do { (start); (size); } while (0)
479 #define dma_cache_inv(start,size) do { (start); (size); } while (0)
481 #endif /* CONFIG_NONCOHERENT_IO */
483 #endif /* _ASM_IO_H */