2 * Definitions for the SGI O2 Crime chip.
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
8 * Copyright (C) 2000 Harald Koerfgen
11 #ifndef __ASM_CRIME_H__
12 #define __ASM_CRIME_H__
14 #include <asm/addrspace.h>
20 #define CRIME_BASE KSEG1ADDR(0x14000000)
22 #define CRIME_BASE 0xffffffffb4000000
26 static inline u64 crime_read_64 (unsigned long __offset) {
27 return *((volatile u64 *) (CRIME_BASE + __offset));
29 static inline void crime_write_64 (unsigned long __offset, u64 __val) {
30 *((volatile u64 *) (CRIME_BASE + __offset)) = __val;
35 #define BIT(x) (1UL << (x))
37 /* All CRIME registers are 64 bits */
40 #define CRIME_ID_MASK 0xff
41 #define CRIME_ID_IDBITS 0xf0
42 #define CRIME_ID_IDVALUE 0xa0
43 #define CRIME_ID_REV 0x0f
45 #define CRIME_REV_PETTY 0x00
46 #define CRIME_REV_11 0x11
47 #define CRIME_REV_13 0x13
48 #define CRIME_REV_14 0x14
50 #define CRIME_CONTROL (0x00000008)
51 #define CRIME_CONTROL_MASK 0x3fff /* 14-bit registers */
53 /* CRIME_CONTROL register bits */
54 #define CRIME_CONTROL_TRITON_SYSADC 0x2000
55 #define CRIME_CONTROL_CRIME_SYSADC 0x1000
56 #define CRIME_CONTROL_HARD_RESET 0x0800
57 #define CRIME_CONTROL_SOFT_RESET 0x0400
58 #define CRIME_CONTROL_DOG_ENA 0x0200
59 #define CRIME_CONTROL_ENDIANESS 0x0100
61 #define CRIME_CONTROL_ENDIAN_BIG 0x0100
62 #define CRIME_CONTROL_ENDIAN_LITTLE 0x0000
64 #define CRIME_CONTROL_CQUEUE_HWM 0x000f
65 #define CRIME_CONTROL_CQUEUE_SHFT 0
66 #define CRIME_CONTROL_WBUF_HWM 0x00f0
67 #define CRIME_CONTROL_WBUF_SHFT 8
69 #define CRIME_INT_STAT (0x00000010)
70 #define CRIME_INT_MASK (0x00000018)
71 #define CRIME_SOFT_INT (0x00000020)
72 #define CRIME_HARD_INT (0x00000028)
74 /* Bits in CRIME_INT_XXX and CRIME_HARD_INT */
75 #define MACE_VID_IN1_INT BIT (0)
76 #define MACE_VID_IN2_INT BIT (1)
77 #define MACE_VID_OUT_INT BIT (2)
78 #define MACE_ETHERNET_INT BIT (3)
79 #define MACE_SUPERIO_INT BIT (4)
80 #define MACE_MISC_INT BIT (5)
81 #define MACE_AUDIO_INT BIT (6)
82 #define MACE_PCI_BRIDGE_INT BIT (7)
83 #define MACEPCI_SCSI0_INT BIT (8)
84 #define MACEPCI_SCSI1_INT BIT (9)
85 #define MACEPCI_SLOT0_INT BIT (10)
86 #define MACEPCI_SLOT1_INT BIT (11)
87 #define MACEPCI_SLOT2_INT BIT (12)
88 #define MACEPCI_SHARED0_INT BIT (13)
89 #define MACEPCI_SHARED1_INT BIT (14)
90 #define MACEPCI_SHARED2_INT BIT (15)
91 #define CRIME_GBE0_INT BIT (16)
92 #define CRIME_GBE1_INT BIT (17)
93 #define CRIME_GBE2_INT BIT (18)
94 #define CRIME_GBE3_INT BIT (19)
95 #define CRIME_CPUERR_INT BIT (20)
96 #define CRIME_MEMERR_INT BIT (21)
97 #define CRIME_RE_EMPTY_E_INT BIT (22)
98 #define CRIME_RE_FULL_E_INT BIT (23)
99 #define CRIME_RE_IDLE_E_INT BIT (24)
100 #define CRIME_RE_EMPTY_L_INT BIT (25)
101 #define CRIME_RE_FULL_L_INT BIT (26)
102 #define CRIME_RE_IDLE_L_INT BIT (27)
103 #define CRIME_SOFT0_INT BIT (28)
104 #define CRIME_SOFT1_INT BIT (29)
105 #define CRIME_SOFT2_INT BIT (30)
106 #define CRIME_SYSCORERR_INT CRIME_SOFT2_INT
107 #define CRIME_VICE_INT BIT (31)
109 /* Masks for deciding who handles the interrupt */
110 #define CRIME_MACE_INT_MASK 0x8f
111 #define CRIME_MACEISA_INT_MASK 0x70
112 #define CRIME_MACEPCI_INT_MASK 0xff00
113 #define CRIME_CRIME_INT_MASK 0xffff0000
118 #define CRIME_DOG (0x00000030)
119 /* We are word-play compatible but not misspelling compatible */
120 #define MC_GRUFF CRIME_DOG
121 #define CRIME_DOG_MASK (0x001fffff)
123 /* CRIME_DOG register bits */
124 #define CRIME_DOG_POWER_ON_RESET (0x00010000)
125 #define CRIME_DOG_WARM_RESET (0x00080000)
126 #define CRIME_DOG_TIMEOUT (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
127 #define CRIME_DOG_VALUE (0x00007fff) /* ??? */
129 #define CRIME_TIME (0x00000038)
130 #define CRIME_TIME_MASK (0x0000ffffffffffff)
135 #define CRIME_MASTER_FREQ 66666500 /* Crime upcounter frequency */
136 #define CRIME_NS_PER_TICK 15 /* for delay_calibrate */
138 #define CRIME_CPU_ERROR_ADDR (0x00000040)
139 #define CRIME_CPU_ERROR_ADDR_MASK (0x3ffffffff)
141 #define CRIME_CPU_ERROR_STAT (0x00000048)
142 /* REV_PETTY only! */
143 #define CRIME_CPU_ERROR_ENA (0x00000050)
146 * bit definitions for CRIME/VICE error status and enable registers
148 #define CRIME_CPU_ERROR_MASK 0x7UL /* cpu error stat is 3 bits */
149 #define CRIME_CPU_ERROR_CPU_ILL_ADDR 0x4
150 #define CRIME_CPU_ERROR_VICE_WRT_PRTY 0x2
151 #define CRIME_CPU_ERROR_CPU_WRT_PRTY 0x1
154 * these are the definitions for the error status/enable register in
155 * petty crime. Note that the enable register does not exist in crime
158 #define CRIME_CPU_ERROR_MASK_REV0 0x3ff /* cpu error stat is 9 bits */
159 #define CRIME_CPU_ERROR_CPU_INV_ADDR_RD 0x200
160 #define CRIME_CPU_ERROR_VICE_II 0x100
161 #define CRIME_CPU_ERROR_VICE_SYSAD 0x80
162 #define CRIME_CPU_ERROR_VICE_SYSCMD 0x40
163 #define CRIME_CPU_ERROR_VICE_INV_ADDR 0x20
164 #define CRIME_CPU_ERROR_CPU_II 0x10
165 #define CRIME_CPU_ERROR_CPU_SYSAD 0x8
166 #define CRIME_CPU_ERROR_CPU_SYSCMD 0x4
167 #define CRIME_CPU_ERROR_CPU_INV_ADDR_WR 0x2
168 #define CRIME_CPU_ERROR_CPU_INV_REG_ADDR 0x1
170 #define CRIME_VICE_ERROR_ADDR (0x00000058)
171 #define CRIME_VICE_ERROR_ADDR_MASK (0x3fffffff)
173 #define CRIME_MEM_CONTROL (0x00000200)
174 #define CRIME_MEM_CONTROL_MASK 0x3 /* 25 cent register */
175 #define CRIME_MEM_CONTROL_ECC_ENA 0x1
176 #define CRIME_MEM_CONTROL_USE_ECC_REPL 0x2
179 * macros for CRIME memory bank control registers.
181 #define CRIME_MEM_BANK_CONTROL(__bank) (0x00000208 + ((__bank) << 3))
182 #define CRIME_MEM_BANK_CONTROL_MSK 0x11f /* 9 bits 7:5 reserved */
183 #define CRIME_MEM_BANK_CONTROL_ADDR 0x01f
184 #define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE 0x100
185 #define CRIME_MEM_BANK_CONTROL_BANK_TO_ADDR(__bank) \
186 (((__bank) & CRIME_MEM_BANK_CONTROL_ADDR) << 25)
188 #define CRIME_MEM_REFRESH_COUNTER (0x00000248)
189 #define CRIME_MEM_REFRESH_COUNTER_MASK 0x7ff /* 11-bit register */
191 #define CRIME_MAXBANKS 8
194 * CRIME Memory error status register bit definitions
196 #define CRIME_MEM_ERROR_STAT (0x00000250)
197 #define CRIME_MEM_ERROR_STAT_MASK 0x0ff7ffff /* 28-bit register */
198 #define CRIME_MEM_ERROR_MACE_ID 0x0000007f
199 #define CRIME_MEM_ERROR_MACE_ACCESS 0x00000080
200 #define CRIME_MEM_ERROR_RE_ID 0x00007f00
201 #define CRIME_MEM_ERROR_RE_ACCESS 0x00008000
202 #define CRIME_MEM_ERROR_GBE_ACCESS 0x00010000
203 #define CRIME_MEM_ERROR_VICE_ACCESS 0x00020000
204 #define CRIME_MEM_ERROR_CPU_ACCESS 0x00040000
205 #define CRIME_MEM_ERROR_RESERVED 0x00080000
206 #define CRIME_MEM_ERROR_SOFT_ERR 0x00100000
207 #define CRIME_MEM_ERROR_HARD_ERR 0x00200000
208 #define CRIME_MEM_ERROR_MULTIPLE 0x00400000
209 #define CRIME_MEM_ERROR_MEM_ECC_RD 0x00800000
210 #define CRIME_MEM_ERROR_MEM_ECC_RMW 0x01000000
211 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
212 #define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
213 #define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
215 #define CRIME_MEM_ERROR_ADDR (0x00000258)
216 #define CRIME_MEM_ERROR_ADDR_MASK 0x3fffffff
218 #define CRIME_MEM_ERROR_ECC_SYN (0x00000260)
219 #define CRIME_MEM_ERROR_ECC_SYN_MASK 0xffffffff
221 #define CRIME_MEM_ERROR_ECC_CHK (0x00000268)
222 #define CRIME_MEM_ERROR_ECC_CHK_MASK 0xffffffff
224 #define CRIME_MEM_ERROR_ECC_REPL (0x00000270)
225 #define CRIME_MEM_ERROR_ECC_REPL_MASK 0xffffffff
227 #endif /* __ASM_CRIME_H__ */