2 * Carsten Langgaard, carstenl@mips.com
3 * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
5 * ########################################################################
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
20 * ########################################################################
22 * Defines of the MIPS boards specific address-MAP, registers, etc.
25 #ifndef _MIPS_GENERIC_H
26 #define _MIPS_GENERIC_H
28 #include <linux/config.h>
29 #include <asm/addrspace.h>
30 #include <asm/byteorder.h>
31 #include <asm/mips-boards/bonito64.h>
34 * Display register base.
36 #if defined(CONFIG_MIPS_SEAD)
37 #define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f0005c0))
39 #define ASCII_DISPLAY_WORD_BASE (KSEG1ADDR(0x1f000410))
40 #define ASCII_DISPLAY_POS_BASE (KSEG1ADDR(0x1f000418))
45 * Yamon Prom print address.
47 #define YAMON_PROM_PRINT_ADDR (KSEG1ADDR(0x1fc00504))
53 #if defined(CONFIG_MIPS_SEAD)
54 #define SOFTRES_REG (KSEG1ADDR(0x1e800050))
57 #define SOFTRES_REG (KSEG1ADDR(0x1f000500))
64 #define MIPS_REVISION_REG (KSEG1ADDR(0x1fc00010))
65 #define MIPS_REVISION_CORID_QED_RM5261 0
66 #define MIPS_REVISION_CORID_CORE_LV 1
67 #define MIPS_REVISION_CORID_BONITO64 2
68 #define MIPS_REVISION_CORID_CORE_20K 3
69 #define MIPS_REVISION_CORID_CORE_FPGA 4
70 #define MIPS_REVISION_CORID_CORE_MSC 5
72 #define MIPS_REVISION_CORID (((*(volatile u32 *)(MIPS_REVISION_REG)) >> 10) & 0x3f)
74 extern unsigned int mips_revision_corid;
78 * Galileo GT64120 system controller register base.
80 #define MIPS_GT_BASE (KSEG1ADDR(0x1be00000))
83 * Because of the way the internal register works on the Galileo chip,
84 * we need to swap the bytes when running bigendian.
86 #define GT_WRITE(ofs, data) \
87 *(volatile u32 *)(MIPS_GT_BASE+ofs) = cpu_to_le32(data)
88 #define GT_READ(ofs, data) \
89 data = le32_to_cpu(*(volatile u32 *)(MIPS_GT_BASE+ofs))
91 #define GT_PCI_WRITE(ofs, data) \
92 *(volatile u32 *)(MIPS_GT_BASE+ofs) = data
93 #define GT_PCI_READ(ofs, data) \
94 data = *(volatile u32 *)(MIPS_GT_BASE+ofs)
97 * Algorithmics Bonito64 system controller register base.
99 static char * const _bonito = (char *)KSEG1ADDR(BONITO_REG_BASE);
102 * MIPS System controller PCI register base.
104 #define MSC01_PCI_REG_BASE (KSEG1ADDR(0x1bd00000))
106 #define MSC_WRITE(reg, data) \
107 *(volatile u32 *)(reg) = data
108 #define MSC_READ(reg, data) \
109 data = *(volatile u32 *)(reg)
111 #endif /* !(_MIPS_GENERIC_H) */