1 /* *********************************************************************
2 * SB1250 Board Support Package
4 * SCD Constants and Macros File: sb1250_scd.h
6 * This module contains constants and macros useful for
7 * manipulating the System Control and Debug module on the 1250.
9 * SB1250 specification level: User's manual 1/02/02
11 * Author: Mitch Lichtenberg (mpl@broadcom.com)
13 *********************************************************************
16 * Broadcom Corporation. All rights reserved.
18 * This program is free software; you can redistribute it and/or
19 * modify it under the terms of the GNU General Public License as
20 * published by the Free Software Foundation; either version 2 of
21 * the License, or (at your option) any later version.
23 * This program is distributed in the hope that it will be useful,
24 * but WITHOUT ANY WARRANTY; without even the implied warranty of
25 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
26 * GNU General Public License for more details.
28 * You should have received a copy of the GNU General Public License
29 * along with this program; if not, write to the Free Software
30 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
32 ********************************************************************* */
37 #include "sb1250_defs.h"
39 /* *********************************************************************
40 * System control/debug registers
41 ********************************************************************* */
44 * System Revision Register (Table 4-1)
47 #define M_SYS_RESERVED _SB_MAKEMASK(8,0)
49 #define S_SYS_REVISION _SB_MAKE64(8)
50 #define M_SYS_REVISION _SB_MAKEMASK(8,S_SYS_REVISION)
51 #define V_SYS_REVISION(x) _SB_MAKEVALUE(x,S_SYS_REVISION)
52 #define G_SYS_REVISION(x) _SB_GETVALUE(x,S_SYS_REVISION,M_SYS_REVISION)
54 #define K_SYS_REVISION_PASS1 1
55 #define K_SYS_REVISION_PASS2 3
56 #define K_SYS_REVISION_PASS2_2 16
57 #define K_SYS_REVISION_PASS3 32
59 #define S_SYS_PART _SB_MAKE64(16)
60 #define M_SYS_PART _SB_MAKEMASK(16,S_SYS_PART)
61 #define V_SYS_PART(x) _SB_MAKEVALUE(x,S_SYS_PART)
62 #define G_SYS_PART(x) _SB_GETVALUE(x,S_SYS_PART,M_SYS_PART)
64 #define K_SYS_PART_SB1250 0x1250
65 #define K_SYS_PART_SB1125 0x1125
67 #define S_SYS_WID _SB_MAKE64(32)
68 #define M_SYS_WID _SB_MAKEMASK(32,S_SYS_WID)
69 #define V_SYS_WID(x) _SB_MAKEVALUE(x,S_SYS_WID)
70 #define G_SYS_WID(x) _SB_GETVALUE(x,S_SYS_WID,M_SYS_WID)
73 * System Config Register (Table 4-2)
74 * Register: SCD_SYSTEM_CFG
77 #define M_SYS_LDT_PLL_BYP _SB_MAKEMASK1(3)
78 #define M_SYS_PCI_SYNC_TEST_MODE _SB_MAKEMASK1(4)
79 #define M_SYS_IOB0_DIV _SB_MAKEMASK1(5)
80 #define M_SYS_IOB1_DIV _SB_MAKEMASK1(6)
82 #define S_SYS_PLL_DIV _SB_MAKE64(7)
83 #define M_SYS_PLL_DIV _SB_MAKEMASK(5,S_SYS_PLL_DIV)
84 #define V_SYS_PLL_DIV(x) _SB_MAKEVALUE(x,S_SYS_PLL_DIV)
85 #define G_SYS_PLL_DIV(x) _SB_GETVALUE(x,S_SYS_PLL_DIV,M_SYS_PLL_DIV)
87 #define M_SYS_SER0_ENABLE _SB_MAKEMASK1(12)
88 #define M_SYS_SER0_RSTB_EN _SB_MAKEMASK1(13)
89 #define M_SYS_SER1_ENABLE _SB_MAKEMASK1(14)
90 #define M_SYS_SER1_RSTB_EN _SB_MAKEMASK1(15)
91 #define M_SYS_PCMCIA_ENABLE _SB_MAKEMASK1(16)
93 #define S_SYS_BOOT_MODE _SB_MAKE64(17)
94 #define M_SYS_BOOT_MODE _SB_MAKEMASK(2,S_SYS_BOOT_MODE)
95 #define V_SYS_BOOT_MODE(x) _SB_MAKEVALUE(x,S_SYS_BOOT_MODE)
96 #define G_SYS_BOOT_MODE(x) _SB_GETVALUE(x,S_SYS_BOOT_MODE,M_SYS_BOOT_MODE)
97 #define K_SYS_BOOT_MODE_ROM32 0
98 #define K_SYS_BOOT_MODE_ROM8 1
99 #define K_SYS_BOOT_MODE_SMBUS_SMALL 2
100 #define K_SYS_BOOT_MODE_SMBUS_BIG 3
102 #define M_SYS_PCI_HOST _SB_MAKEMASK1(19)
103 #define M_SYS_PCI_ARBITER _SB_MAKEMASK1(20)
104 #define M_SYS_SOUTH_ON_LDT _SB_MAKEMASK1(21)
105 #define M_SYS_BIG_ENDIAN _SB_MAKEMASK1(22)
106 #define M_SYS_GENCLK_EN _SB_MAKEMASK1(23)
107 #define M_SYS_LDT_TEST_EN _SB_MAKEMASK1(24)
108 #define M_SYS_GEN_PARITY_EN _SB_MAKEMASK1(25)
110 #define S_SYS_CONFIG 26
111 #define M_SYS_CONFIG _SB_MAKEMASK(6,S_SYS_CONFIG)
112 #define V_SYS_CONFIG(x) _SB_MAKEVALUE(x,S_SYS_CONFIG)
113 #define G_SYS_CONFIG(x) _SB_GETVALUE(x,S_SYS_CONFIG,M_SYS_CONFIG)
115 /* The following bits are writeable by JTAG only. */
117 #define M_SYS_CLKSTOP _SB_MAKEMASK1(32)
118 #define M_SYS_CLKSTEP _SB_MAKEMASK1(33)
120 #define S_SYS_CLKCOUNT 34
121 #define M_SYS_CLKCOUNT _SB_MAKEMASK(8,S_SYS_CLKCOUNT)
122 #define V_SYS_CLKCOUNT(x) _SB_MAKEVALUE(x,S_SYS_CLKCOUNT)
123 #define G_SYS_CLKCOUNT(x) _SB_GETVALUE(x,S_SYS_CLKCOUNT,M_SYS_CLKCOUNT)
125 #define M_SYS_PLL_BYPASS _SB_MAKEMASK1(42)
127 #define S_SYS_PLL_IREF 43
128 #define M_SYS_PLL_IREF _SB_MAKEMASK(2,S_SYS_PLL_IREF)
130 #define S_SYS_PLL_VCO 45
131 #define M_SYS_PLL_VCO _SB_MAKEMASK(2,S_SYS_PLL_VCO)
133 #define S_SYS_PLL_VREG 47
134 #define M_SYS_PLL_VREG _SB_MAKEMASK(2,S_SYS_PLL_VREG)
136 #define M_SYS_MEM_RESET _SB_MAKEMASK1(49)
137 #define M_SYS_L2C_RESET _SB_MAKEMASK1(50)
138 #define M_SYS_IO_RESET_0 _SB_MAKEMASK1(51)
139 #define M_SYS_IO_RESET_1 _SB_MAKEMASK1(52)
140 #define M_SYS_SCD_RESET _SB_MAKEMASK1(53)
142 /* End of bits writable by JTAG only. */
144 #define M_SYS_CPU_RESET_0 _SB_MAKEMASK1(54)
145 #define M_SYS_CPU_RESET_1 _SB_MAKEMASK1(55)
147 #define M_SYS_UNICPU0 _SB_MAKEMASK1(56)
148 #define M_SYS_UNICPU1 _SB_MAKEMASK1(57)
150 #define M_SYS_SB_SOFTRES _SB_MAKEMASK1(58)
151 #define M_SYS_EXT_RESET _SB_MAKEMASK1(59)
152 #define M_SYS_SYSTEM_RESET _SB_MAKEMASK1(60)
154 #define M_SYS_MISR_MODE _SB_MAKEMASK1(61)
155 #define M_SYS_MISR_RESET _SB_MAKEMASK1(62)
157 #define M_SYS_SW_FLAG _SB_MAKEMASK1(63) /* PASS2 */
161 * Mailbox Registers (Table 4-3)
162 * Registers: SCD_MBOX_CPU_x
165 #define S_MBOX_INT_3 0
166 #define M_MBOX_INT_3 _SB_MAKEMASK(16,S_MBOX_INT_3)
167 #define S_MBOX_INT_2 16
168 #define M_MBOX_INT_2 _SB_MAKEMASK(16,S_MBOX_INT_2)
169 #define S_MBOX_INT_1 32
170 #define M_MBOX_INT_1 _SB_MAKEMASK(16,S_MBOX_INT_1)
171 #define S_MBOX_INT_0 48
172 #define M_MBOX_INT_0 _SB_MAKEMASK(16,S_MBOX_INT_0)
175 * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
176 * Registers: SCD_WDOG_INIT_CNT_x
179 #define V_SCD_WDOG_FREQ 1000000
181 #define S_SCD_WDOG_INIT 0
182 #define M_SCD_WDOG_INIT _SB_MAKEMASK(13,S_SCD_WDOG_INIT)
184 #define S_SCD_WDOG_CNT 0
185 #define M_SCD_WDOG_CNT _SB_MAKEMASK(13,S_SCD_WDOG_CNT)
187 #define M_SCD_WDOG_ENABLE _SB_MAKEMASK1(0)
190 * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
193 #define V_SCD_TIMER_FREQ 1000000
195 #define S_SCD_TIMER_INIT 0
196 #define M_SCD_TIMER_INIT _SB_MAKEMASK(20,S_SCD_TIMER_INIT)
197 #define V_SCD_TIMER_INIT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_INIT)
198 #define G_SCD_TIMER_INIT(x) _SB_GETVALUE(x,S_SCD_TIMER_INIT,M_SCD_TIMER_INIT)
200 #define S_SCD_TIMER_CNT 0
201 #define M_SCD_TIMER_CNT _SB_MAKEMASK(20,S_SCD_TIMER_CNT)
202 #define V_SCD_TIMER_CNT(x) _SB_MAKEVALUE(x,S_SCD_TIMER_CNT)
203 #define G_SCD_TIMER_CNT(x) _SB_GETVALUE(x,S_SCD_TIMER_CNT,M_SCD_TIMER_CNT)
205 #define M_SCD_TIMER_ENABLE _SB_MAKEMASK1(0)
206 #define M_SCD_TIMER_MODE _SB_MAKEMASK1(1)
207 #define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
210 * System Performance Counters
213 #define S_SPC_CFG_SRC0 0
214 #define M_SPC_CFG_SRC0 _SB_MAKEMASK(8,S_SPC_CFG_SRC0)
215 #define V_SPC_CFG_SRC0(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC0)
216 #define G_SPC_CFG_SRC0(x) _SB_GETVALUE(x,S_SPC_CFG_SRC0,M_SPC_CFG_SRC0)
218 #define S_SPC_CFG_SRC1 8
219 #define M_SPC_CFG_SRC1 _SB_MAKEMASK(8,S_SPC_CFG_SRC1)
220 #define V_SPC_CFG_SRC1(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC1)
221 #define G_SPC_CFG_SRC1(x) _SB_GETVALUE(x,S_SPC_CFG_SRC1,M_SPC_CFG_SRC1)
223 #define S_SPC_CFG_SRC2 16
224 #define M_SPC_CFG_SRC2 _SB_MAKEMASK(8,S_SPC_CFG_SRC2)
225 #define V_SPC_CFG_SRC2(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC2)
226 #define G_SPC_CFG_SRC2(x) _SB_GETVALUE(x,S_SPC_CFG_SRC2,M_SPC_CFG_SRC2)
228 #define S_SPC_CFG_SRC3 24
229 #define M_SPC_CFG_SRC3 _SB_MAKEMASK(8,S_SPC_CFG_SRC3)
230 #define V_SPC_CFG_SRC3(x) _SB_MAKEVALUE(x,S_SPC_CFG_SRC3)
231 #define G_SPC_CFG_SRC3(x) _SB_GETVALUE(x,S_SPC_CFG_SRC3,M_SPC_CFG_SRC3)
233 #define M_SPC_CFG_CLEAR _SB_MAKEMASK1(32)
234 #define M_SPC_CFG_ENABLE _SB_MAKEMASK1(33)
241 #define S_SCD_BERR_TID 8
242 #define M_SCD_BERR_TID _SB_MAKEMASK(10,S_SCD_BERR_TID)
243 #define V_SCD_BERR_TID(x) _SB_MAKEVALUE(x,S_SCD_BERR_TID)
244 #define G_SCD_BERR_TID(x) _SB_GETVALUE(x,S_SCD_BERR_TID,M_SCD_BERR_TID)
246 #define S_SCD_BERR_RID 18
247 #define M_SCD_BERR_RID _SB_MAKEMASK(4,S_SCD_BERR_RID)
248 #define V_SCD_BERR_RID(x) _SB_MAKEVALUE(x,S_SCD_BERR_RID)
249 #define G_SCD_BERR_RID(x) _SB_GETVALUE(x,S_SCD_BERR_RID,M_SCD_BERR_RID)
251 #define S_SCD_BERR_DCODE 22
252 #define M_SCD_BERR_DCODE _SB_MAKEMASK(3,S_SCD_BERR_DCODE)
253 #define V_SCD_BERR_DCODE(x) _SB_MAKEVALUE(x,S_SCD_BERR_DCODE)
254 #define G_SCD_BERR_DCODE(x) _SB_GETVALUE(x,S_SCD_BERR_DCODE,M_SCD_BERR_DCODE)
256 #define M_SCD_BERR_MULTERRS _SB_MAKEMASK1(30)
259 #define S_SCD_L2ECC_CORR_D 0
260 #define M_SCD_L2ECC_CORR_D _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_D)
261 #define V_SCD_L2ECC_CORR_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_D)
262 #define G_SCD_L2ECC_CORR_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_D,M_SCD_L2ECC_CORR_D)
264 #define S_SCD_L2ECC_BAD_D 8
265 #define M_SCD_L2ECC_BAD_D _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_D)
266 #define V_SCD_L2ECC_BAD_D(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_D)
267 #define G_SCD_L2ECC_BAD_D(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_D,M_SCD_L2ECC_BAD_D)
269 #define S_SCD_L2ECC_CORR_T 16
270 #define M_SCD_L2ECC_CORR_T _SB_MAKEMASK(8,S_SCD_L2ECC_CORR_T)
271 #define V_SCD_L2ECC_CORR_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_CORR_T)
272 #define G_SCD_L2ECC_CORR_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_CORR_T,M_SCD_L2ECC_CORR_T)
274 #define S_SCD_L2ECC_BAD_T 24
275 #define M_SCD_L2ECC_BAD_T _SB_MAKEMASK(8,S_SCD_L2ECC_BAD_T)
276 #define V_SCD_L2ECC_BAD_T(x) _SB_MAKEVALUE(x,S_SCD_L2ECC_BAD_T)
277 #define G_SCD_L2ECC_BAD_T(x) _SB_GETVALUE(x,S_SCD_L2ECC_BAD_T,M_SCD_L2ECC_BAD_T)
279 #define S_SCD_MEM_ECC_CORR 0
280 #define M_SCD_MEM_ECC_CORR _SB_MAKEMASK(8,S_SCD_MEM_ECC_CORR)
281 #define V_SCD_MEM_ECC_CORR(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_CORR)
282 #define G_SCD_MEM_ECC_CORR(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_CORR,M_SCD_MEM_ECC_CORR)
284 #define S_SCD_MEM_ECC_BAD 16
285 #define M_SCD_MEM_ECC_BAD _SB_MAKEMASK(8,S_SCD_MEM_ECC_BAD)
286 #define V_SCD_MEM_ECC_BAD(x) _SB_MAKEVALUE(x,S_SCD_MEM_ECC_BAD)
287 #define G_SCD_MEM_ECC_BAD(x) _SB_GETVALUE(x,S_SCD_MEM_ECC_BAD,M_SCD_MEM_ECC_BAD)
289 #define S_SCD_MEM_BUSERR 24
290 #define M_SCD_MEM_BUSERR _SB_MAKEMASK(8,S_SCD_MEM_BUSERR)
291 #define V_SCD_MEM_BUSERR(x) _SB_MAKEVALUE(x,S_SCD_MEM_BUSERR)
292 #define G_SCD_MEM_BUSERR(x) _SB_GETVALUE(x,S_SCD_MEM_BUSERR,M_SCD_MEM_BUSERR)
296 * Address Trap Registers
299 #define M_ATRAP_INDEX _SB_MAKEMASK(4,0)
300 #define M_ATRAP_ADDRESS _SB_MAKEMASK(40,0)
302 #define S_ATRAP_CFG_CNT 0
303 #define M_ATRAP_CFG_CNT _SB_MAKEMASK(3,S_ATRAP_CFG_CNT)
304 #define V_ATRAP_CFG_CNT(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CNT)
305 #define G_ATRAP_CFG_CNT(x) _SB_GETVALUE(x,S_ATRAP_CFG_CNT,M_ATRAP_CFG_CNT)
307 #define M_ATRAP_CFG_WRITE _SB_MAKEMASK1(3)
308 #define M_ATRAP_CFG_ALL _SB_MAKEMASK1(4)
309 #define M_ATRAP_CFG_INV _SB_MAKEMASK1(5)
310 #define M_ATRAP_CFG_USESRC _SB_MAKEMASK1(6)
311 #define M_ATRAP_CFG_SRCINV _SB_MAKEMASK1(7)
313 #define S_ATRAP_CFG_AGENTID 8
314 #define M_ATRAP_CFG_AGENTID _SB_MAKEMASK(4,S_ATRAP_CFG_AGENTID)
315 #define V_ATRAP_CFG_AGENTID(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_AGENTID)
316 #define G_ATRAP_CFG_AGENTID(x) _SB_GETVALUE(x,S_ATRAP_CFG_AGENTID,M_ATRAP_CFG_AGENTID)
318 #define K_BUS_AGENT_CPU0 0
319 #define K_BUS_AGENT_CPU1 1
320 #define K_BUS_AGENT_IOB0 2
321 #define K_BUS_AGENT_IOB1 3
322 #define K_BUS_AGENT_SCD 4
323 #define K_BUS_AGENT_RESERVED 5
324 #define K_BUS_AGENT_L2C 6
325 #define K_BUS_AGENT_MC 7
327 #define S_ATRAP_CFG_CATTR 12
328 #define M_ATRAP_CFG_CATTR _SB_MAKEMASK(3,S_ATRAP_CFG_CATTR)
329 #define V_ATRAP_CFG_CATTR(x) _SB_MAKEVALUE(x,S_ATRAP_CFG_CATTR)
330 #define G_ATRAP_CFG_CATTR(x) _SB_GETVALUE(x,S_ATRAP_CFG_CATTR,M_ATRAP_CFG_CATTR)
332 #define K_ATRAP_CFG_CATTR_IGNORE 0
333 #define K_ATRAP_CFG_CATTR_UNC 1
334 #define K_ATRAP_CFG_CATTR_CACHEABLE 2
335 #define K_ATRAP_CFG_CATTR_NONCOH 3
336 #define K_ATRAP_CFG_CATTR_COHERENT 4
337 #define K_ATRAP_CFG_CATTR_NOTUNC 5
338 #define K_ATRAP_CFG_CATTR_NOTNONCOH 6
339 #define K_ATRAP_CFG_CATTR_NOTCOHERENT 7
342 * Trace Buffer Config register
345 #define M_SCD_TRACE_CFG_RESET _SB_MAKEMASK1(0)
346 #define M_SCD_TRACE_CFG_START_READ _SB_MAKEMASK1(1)
347 #define M_SCD_TRACE_CFG_START _SB_MAKEMASK1(2)
348 #define M_SCD_TRACE_CFG_STOP _SB_MAKEMASK1(3)
349 #define M_SCD_TRACE_CFG_FREEZE _SB_MAKEMASK1(4)
350 #define M_SCD_TRACE_CFG_FREEZE_FULL _SB_MAKEMASK1(5)
351 #define M_SCD_TRACE_CFG_DEBUG_FULL _SB_MAKEMASK1(6)
352 #define M_SCD_TRACE_CFG_FULL _SB_MAKEMASK1(7)
353 #define M_SCD_TRACE_CFG_FORCECNT _SB_MAKEMASK1(8) /* PASS2 */
355 #define S_SCD_TRACE_CFG_CUR_ADDR 10
356 #define M_SCD_TRACE_CFG_CUR_ADDR _SB_MAKEMASK(8,S_SCD_TRACE_CFG_CUR_ADDR)
357 #define V_SCD_TRACE_CFG_CUR_ADDR(x) _SB_MAKEVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR)
358 #define G_SCD_TRACE_CFG_CUR_ADDR(x) _SB_GETVALUE(x,S_SCD_TRACE_CFG_CUR_ADDR,M_SCD_TRACE_CFG_CUR_ADDR)
361 * Trace Event registers
364 #define S_SCD_TREVT_ADDR_MATCH 0
365 #define M_SCD_TREVT_ADDR_MATCH _SB_MAKEMASK(4,S_SCD_TREVT_ADDR_MATCH)
366 #define V_SCD_TREVT_ADDR_MATCH(x) _SB_MAKEVALUE(x,S_SCD_TREVT_ADDR_MATCH)
367 #define G_SCD_TREVT_ADDR_MATCH(x) _SB_GETVALUE(x,S_SCD_TREVT_ADDR_MATCH,M_SCD_TREVT_ADDR_MATCH)
369 #define M_SCD_TREVT_REQID_MATCH _SB_MAKEMASK1(4)
370 #define M_SCD_TREVT_DATAID_MATCH _SB_MAKEMASK1(5)
371 #define M_SCD_TREVT_RESPID_MATCH _SB_MAKEMASK1(6)
372 #define M_SCD_TREVT_INTERRUPT _SB_MAKEMASK1(7)
373 #define M_SCD_TREVT_DEBUG_PIN _SB_MAKEMASK1(9)
374 #define M_SCD_TREVT_WRITE _SB_MAKEMASK1(10)
375 #define M_SCD_TREVT_READ _SB_MAKEMASK1(11)
377 #define S_SCD_TREVT_REQID 12
378 #define M_SCD_TREVT_REQID _SB_MAKEMASK(4,S_SCD_TREVT_REQID)
379 #define V_SCD_TREVT_REQID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_REQID)
380 #define G_SCD_TREVT_REQID(x) _SB_GETVALUE(x,S_SCD_TREVT_REQID,M_SCD_TREVT_REQID)
382 #define S_SCD_TREVT_RESPID 16
383 #define M_SCD_TREVT_RESPID _SB_MAKEMASK(4,S_SCD_TREVT_RESPID)
384 #define V_SCD_TREVT_RESPID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_RESPID)
385 #define G_SCD_TREVT_RESPID(x) _SB_GETVALUE(x,S_SCD_TREVT_RESPID,M_SCD_TREVT_RESPID)
387 #define S_SCD_TREVT_DATAID 20
388 #define M_SCD_TREVT_DATAID _SB_MAKEMASK(4,S_SCD_TREVT_DATAID)
389 #define V_SCD_TREVT_DATAID(x) _SB_MAKEVALUE(x,S_SCD_TREVT_DATAID)
390 #define G_SCD_TREVT_DATAID(x) _SB_GETVALUE(x,S_SCD_TREVT_DATAID,M_SCD_TREVT_DATID)
392 #define S_SCD_TREVT_COUNT 24
393 #define M_SCD_TREVT_COUNT _SB_MAKEMASK(8,S_SCD_TREVT_COUNT)
394 #define V_SCD_TREVT_COUNT(x) _SB_MAKEVALUE(x,S_SCD_TREVT_COUNT)
395 #define G_SCD_TREVT_COUNT(x) _SB_GETVALUE(x,S_SCD_TREVT_COUNT,M_SCD_TREVT_COUNT)
398 * Trace Sequence registers
401 #define S_SCD_TRSEQ_EVENT4 0
402 #define M_SCD_TRSEQ_EVENT4 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT4)
403 #define V_SCD_TRSEQ_EVENT4(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT4)
404 #define G_SCD_TRSEQ_EVENT4(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT4,M_SCD_TRSEQ_EVENT4)
406 #define S_SCD_TRSEQ_EVENT3 4
407 #define M_SCD_TRSEQ_EVENT3 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT3)
408 #define V_SCD_TRSEQ_EVENT3(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT3)
409 #define G_SCD_TRSEQ_EVENT3(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT3,M_SCD_TRSEQ_EVENT3)
411 #define S_SCD_TRSEQ_EVENT2 8
412 #define M_SCD_TRSEQ_EVENT2 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT2)
413 #define V_SCD_TRSEQ_EVENT2(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT2)
414 #define G_SCD_TRSEQ_EVENT2(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT2,M_SCD_TRSEQ_EVENT2)
416 #define S_SCD_TRSEQ_EVENT1 12
417 #define M_SCD_TRSEQ_EVENT1 _SB_MAKEMASK(4,S_SCD_TRSEQ_EVENT1)
418 #define V_SCD_TRSEQ_EVENT1(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_EVENT1)
419 #define G_SCD_TRSEQ_EVENT1(x) _SB_GETVALUE(x,S_SCD_TRSEQ_EVENT1,M_SCD_TRSEQ_EVENT1)
421 #define K_SCD_TRSEQ_E0 0
422 #define K_SCD_TRSEQ_E1 1
423 #define K_SCD_TRSEQ_E2 2
424 #define K_SCD_TRSEQ_E3 3
425 #define K_SCD_TRSEQ_E0_E1 4
426 #define K_SCD_TRSEQ_E1_E2 5
427 #define K_SCD_TRSEQ_E2_E3 6
428 #define K_SCD_TRSEQ_E0_E1_E2 7
429 #define K_SCD_TRSEQ_E0_E1_E2_E3 8
430 #define K_SCD_TRSEQ_E0E1 9
431 #define K_SCD_TRSEQ_E0E1E2 10
432 #define K_SCD_TRSEQ_E0E1E2E3 11
433 #define K_SCD_TRSEQ_E0E1_E2 12
434 #define K_SCD_TRSEQ_E0E1_E2E3 13
435 #define K_SCD_TRSEQ_E0E1_E2_E3 14
436 #define K_SCD_TRSEQ_IGNORED 15
438 #define K_SCD_TRSEQ_TRIGGER_ALL (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
439 V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
440 V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
441 V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
443 #define S_SCD_TRSEQ_FUNCTION 16
444 #define M_SCD_TRSEQ_FUNCTION _SB_MAKEMASK(4,S_SCD_TRSEQ_FUNCTION)
445 #define V_SCD_TRSEQ_FUNCTION(x) _SB_MAKEVALUE(x,S_SCD_TRSEQ_FUNCTION)
446 #define G_SCD_TRSEQ_FUNCTION(x) _SB_GETVALUE(x,S_SCD_TRSEQ_FUNCTION,M_SCD_TRSEQ_FUNCTION)
448 #define K_SCD_TRSEQ_FUNC_NOP 0
449 #define K_SCD_TRSEQ_FUNC_START 1
450 #define K_SCD_TRSEQ_FUNC_STOP 2
451 #define K_SCD_TRSEQ_FUNC_FREEZE 3
453 #define V_SCD_TRSEQ_FUNC_NOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
454 #define V_SCD_TRSEQ_FUNC_START V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
455 #define V_SCD_TRSEQ_FUNC_STOP V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
456 #define V_SCD_TRSEQ_FUNC_FREEZE V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
458 #define M_SCD_TRSEQ_ASAMPLE _SB_MAKEMASK1(18)
459 #define M_SCD_TRSEQ_DSAMPLE _SB_MAKEMASK1(19)
460 #define M_SCD_TRSEQ_DEBUGPIN _SB_MAKEMASK1(20)
461 #define M_SCD_TRSEQ_DEBUGCPU _SB_MAKEMASK1(21)
462 #define M_SCD_TRSEQ_CLEARUSE _SB_MAKEMASK1(22)