2 * include/asm-ppc/gt64260_defs.h
4 * Register definitions for the Marvell/Galileo GT64260 host bridge.
6 * Author: Mark A. Greer <mgreer@mvista.com>
8 * 2001-2002 (c) MontaVista, Software, Inc. This file is licensed under
9 * the terms of the GNU General Public License version 2.1. This program
10 * is licensed "as is" without any warranty of any kind, whether express
13 #ifndef __ASMPPC_GT64260_DEFS_H
14 #define __ASMPPC_GT64260_DEFS_H
17 * Define a macro to represent the supported version of the 64260.
22 /* Minimum window size supported by 64260 is 1MB */
23 #define GT64260_WINDOW_SIZE_MIN 0x00100000
26 *****************************************************************************
28 * CPU Interface Registers
30 *****************************************************************************
33 /* CPU physical address of 64260's registers */
34 #define GT64260_INTERNAL_SPACE_DECODE 0x0068
35 #define GT64260_INTERNAL_SPACE_SIZE 0x10000
36 #define GT64260_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000
38 /* CPU Memory Controller Window Registers (4 windows) */
39 #define GT64260_CPU_SCS_DECODE_WINDOWS 4
41 #define GT64260_CPU_SCS_DECODE_0_BOT 0x0008
42 #define GT64260_CPU_SCS_DECODE_0_TOP 0x0010
43 #define GT64260_CPU_SCS_DECODE_1_BOT 0x0208
44 #define GT64260_CPU_SCS_DECODE_1_TOP 0x0210
45 #define GT64260_CPU_SCS_DECODE_2_BOT 0x0018
46 #define GT64260_CPU_SCS_DECODE_2_TOP 0x0020
47 #define GT64260_CPU_SCS_DECODE_3_BOT 0x0218
48 #define GT64260_CPU_SCS_DECODE_3_TOP 0x0220
50 /* CPU Device Controller Window Registers (4 windows) */
51 #define GT64260_CPU_CS_DECODE_WINDOWS 4
53 #define GT64260_CPU_CS_DECODE_0_BOT 0x0028
54 #define GT64260_CPU_CS_DECODE_0_TOP 0x0030
55 #define GT64260_CPU_CS_DECODE_1_BOT 0x0228
56 #define GT64260_CPU_CS_DECODE_1_TOP 0x0230
57 #define GT64260_CPU_CS_DECODE_2_BOT 0x0248
58 #define GT64260_CPU_CS_DECODE_2_TOP 0x0250
59 #define GT64260_CPU_CS_DECODE_3_BOT 0x0038
60 #define GT64260_CPU_CS_DECODE_3_TOP 0x0040
62 #define GT64260_CPU_BOOT_CS_DECODE_0_BOT 0x0238
63 #define GT64260_CPU_BOOT_CS_DECODE_0_TOP 0x0240
65 /* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */
66 #define GT64260_PCI_BUSES 2
67 #define GT64260_PCI_IO_WINDOWS_PER_BUS 1
68 #define GT64260_PCI_MEM_WINDOWS_PER_BUS 4
70 #define GT64260_CPU_PCI_SWAP_BYTE 0x00000000
71 #define GT64260_CPU_PCI_SWAP_NONE 0x01000000
72 #define GT64260_CPU_PCI_SWAP_BYTE_WORD 0x02000000
73 #define GT64260_CPU_PCI_SWAP_WORD 0x03000000
74 #define GT64260_CPU_PCI_SWAP_MASK 0x07000000
76 #define GT64260_CPU_PCI_MEM_REQ64 (1<<27)
78 #define GT64260_CPU_PCI_0_IO_DECODE_BOT 0x0048
79 #define GT64260_CPU_PCI_0_IO_DECODE_TOP 0x0050
80 #define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT 0x0058
81 #define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP 0x0060
82 #define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT 0x0080
83 #define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP 0x0088
84 #define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT 0x0258
85 #define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP 0x0260
86 #define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT 0x0280
87 #define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP 0x0288
89 #define GT64260_CPU_PCI_0_IO_REMAP 0x00f0
90 #define GT64260_CPU_PCI_0_MEM_0_REMAP_LO 0x00f8
91 #define GT64260_CPU_PCI_0_MEM_0_REMAP_HI 0x0320
92 #define GT64260_CPU_PCI_0_MEM_1_REMAP_LO 0x0100
93 #define GT64260_CPU_PCI_0_MEM_1_REMAP_HI 0x0328
94 #define GT64260_CPU_PCI_0_MEM_2_REMAP_LO 0x02f8
95 #define GT64260_CPU_PCI_0_MEM_2_REMAP_HI 0x0330
96 #define GT64260_CPU_PCI_0_MEM_3_REMAP_LO 0x0300
97 #define GT64260_CPU_PCI_0_MEM_3_REMAP_HI 0x0338
99 #define GT64260_CPU_PCI_1_IO_DECODE_BOT 0x0090
100 #define GT64260_CPU_PCI_1_IO_DECODE_TOP 0x0098
101 #define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT 0x00a0
102 #define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP 0x00a8
103 #define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT 0x00b0
104 #define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP 0x00b8
105 #define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT 0x02a0
106 #define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP 0x02a8
107 #define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT 0x02b0
108 #define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP 0x02b8
110 #define GT64260_CPU_PCI_1_IO_REMAP 0x0108
111 #define GT64260_CPU_PCI_1_MEM_0_REMAP_LO 0x0110
112 #define GT64260_CPU_PCI_1_MEM_0_REMAP_HI 0x0340
113 #define GT64260_CPU_PCI_1_MEM_1_REMAP_LO 0x0118
114 #define GT64260_CPU_PCI_1_MEM_1_REMAP_HI 0x0348
115 #define GT64260_CPU_PCI_1_MEM_2_REMAP_LO 0x0310
116 #define GT64260_CPU_PCI_1_MEM_2_REMAP_HI 0x0350
117 #define GT64260_CPU_PCI_1_MEM_3_REMAP_LO 0x0318
118 #define GT64260_CPU_PCI_1_MEM_3_REMAP_HI 0x0358
120 /* CPU Control Registers */
121 #define GT64260_CPU_CONFIG 0x0000
122 #define GT64260_CPU_MODE 0x0120
123 #define GT64260_CPU_MASTER_CNTL 0x0160
124 #define GT64260_CPU_XBAR_CNTL_LO 0x0150
125 #define GT64260_CPU_XBAR_CNTL_HI 0x0158
126 #define GT64260_CPU_XBAR_TO 0x0168
127 #define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170
128 #define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178
130 /* CPU Sync Barrier Registers */
131 #define GT64260_CPU_SYNC_BARRIER_PCI_0 0x00c0
132 #define GT64260_CPU_SYNC_BARRIER_PCI_1 0x00c8
134 /* CPU Access Protection Registers */
135 #define GT64260_CPU_PROT_WINDOWS 8
137 #define GT64260_CPU_PROT_ACCPROTECT (1<<16)
138 #define GT64260_CPU_PROT_WRPROTECT (1<<17)
139 #define GT64260_CPU_PROT_CACHEPROTECT (1<<18)
141 #define GT64260_CPU_PROT_BASE_0 0x0180
142 #define GT64260_CPU_PROT_TOP_0 0x0188
143 #define GT64260_CPU_PROT_BASE_1 0x0190
144 #define GT64260_CPU_PROT_TOP_1 0x0198
145 #define GT64260_CPU_PROT_BASE_2 0x01a0
146 #define GT64260_CPU_PROT_TOP_2 0x01a8
147 #define GT64260_CPU_PROT_BASE_3 0x01b0
148 #define GT64260_CPU_PROT_TOP_3 0x01b8
149 #define GT64260_CPU_PROT_BASE_4 0x01c0
150 #define GT64260_CPU_PROT_TOP_4 0x01c8
151 #define GT64260_CPU_PROT_BASE_5 0x01d0
152 #define GT64260_CPU_PROT_TOP_5 0x01d8
153 #define GT64260_CPU_PROT_BASE_6 0x01e0
154 #define GT64260_CPU_PROT_TOP_6 0x01e8
155 #define GT64260_CPU_PROT_BASE_7 0x01f0
156 #define GT64260_CPU_PROT_TOP_7 0x01f8
158 /* CPU Snoop Control Registers */
159 #define GT64260_CPU_SNOOP_WINDOWS 4
161 #define GT64260_CPU_SNOOP_NONE 0x00000000
162 #define GT64260_CPU_SNOOP_WT 0x00010000
163 #define GT64260_CPU_SNOOP_WB 0x00020000
164 #define GT64260_CPU_SNOOP_MASK 0x00030000
165 #define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK
167 #define GT64260_CPU_SNOOP_BASE_0 0x0380
168 #define GT64260_CPU_SNOOP_TOP_0 0x0388
169 #define GT64260_CPU_SNOOP_BASE_1 0x0390
170 #define GT64260_CPU_SNOOP_TOP_1 0x0398
171 #define GT64260_CPU_SNOOP_BASE_2 0x03a0
172 #define GT64260_CPU_SNOOP_TOP_2 0x03a8
173 #define GT64260_CPU_SNOOP_BASE_3 0x03b0
174 #define GT64260_CPU_SNOOP_TOP_3 0x03b8
176 /* CPU Error Report Registers */
177 #define GT64260_CPU_ERR_ADDR_LO 0x0070
178 #define GT64260_CPU_ERR_ADDR_HI 0x0078
179 #define GT64260_CPU_ERR_DATA_LO 0x0128
180 #define GT64260_CPU_ERR_DATA_HI 0x0130
181 #define GT64260_CPU_ERR_PARITY 0x0138
182 #define GT64260_CPU_ERR_CAUSE 0x0140
183 #define GT64260_CPU_ERR_MASK 0x0148
187 *****************************************************************************
189 * SDRAM Cotnroller Registers
191 *****************************************************************************
194 /* SDRAM Config Registers */
195 #define GT64260_SDRAM_CONFIG 0x0448
196 #define GT64260_SDRAM_OPERATION_MODE 0x0474
197 #define GT64260_SDRAM_ADDR_CNTL 0x047c
198 #define GT64260_SDRAM_TIMING_PARAMS 0x04b4
199 #define GT64260_SDRAM_UMA_CNTL 0x04a4
200 #define GT64260_SDRAM_XBAR_CNTL_LO 0x04a8
201 #define GT64260_SDRAM_XBAR_CNTL_HI 0x04ac
202 #define GT64260_SDRAM_XBAR_CNTL_TO 0x04b0
204 /* SDRAM Banks Parameters Registers */
205 #define GT64260_SDRAM_BANK_PARAMS_0 0x044c
206 #define GT64260_SDRAM_BANK_PARAMS_1 0x0450
207 #define GT64260_SDRAM_BANK_PARAMS_2 0x0454
208 #define GT64260_SDRAM_BANK_PARAMS_3 0x0458
210 /* SDRAM Error Report Registers */
211 #define GT64260_SDRAM_ERR_DATA_LO 0x0484
212 #define GT64260_SDRAM_ERR_DATA_HI 0x0480
213 #define GT64260_SDRAM_ERR_ADDR 0x0490
214 #define GT64260_SDRAM_ERR_ECC_RCVD 0x0488
215 #define GT64260_SDRAM_ERR_ECC_CALC 0x048c
216 #define GT64260_SDRAM_ERR_ECC_CNTL 0x0494
217 #define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498
221 *****************************************************************************
223 * Device/BOOT Cotnroller Registers
225 *****************************************************************************
228 /* Device Control Registers */
229 #define GT64260_DEV_BANK_PARAMS_0 0x045c
230 #define GT64260_DEV_BANK_PARAMS_1 0x0460
231 #define GT64260_DEV_BANK_PARAMS_2 0x0464
232 #define GT64260_DEV_BANK_PARAMS_3 0x0468
233 #define GT64260_DEV_BOOT_PARAMS 0x046c
234 #define GT64260_DEV_IF_CNTL 0x04c0
235 #define GT64260_DEV_IF_XBAR_CNTL_LO 0x04c8
236 #define GT64260_DEV_IF_XBAR_CNTL_HI 0x04cc
237 #define GT64260_DEV_IF_XBAR_CNTL_TO 0x04c4
239 /* Device Interrupt Registers */
240 #define GT64260_DEV_INTR_CAUSE 0x04d0
241 #define GT64260_DEV_INTR_MASK 0x04d4
242 #define GT64260_DEV_INTR_ERR_ADDR 0x04d8
246 *****************************************************************************
248 * PCI Bridge Interface Registers
250 *****************************************************************************
253 /* PCI Configuration Access Registers */
254 #define GT64260_PCI_0_CONFIG_ADDR 0x0cf8
255 #define GT64260_PCI_0_CONFIG_DATA 0x0cfc
256 #define GT64260_PCI_0_IACK 0x0c34
258 #define GT64260_PCI_1_CONFIG_ADDR 0x0c78
259 #define GT64260_PCI_1_CONFIG_DATA 0x0c7c
260 #define GT64260_PCI_1_IACK 0x0cb4
262 /* PCI Control Registers */
263 #define GT64260_PCI_0_CMD 0x0c00
264 #define GT64260_PCI_0_MODE 0x0d00
265 #define GT64260_PCI_0_TO_RETRY 0x0c04
266 #define GT64260_PCI_0_RD_BUF_DISCARD_TIMER 0x0d04
267 #define GT64260_PCI_0_MSI_TRIGGER_TIMER 0x0c38
268 #define GT64260_PCI_0_ARBITER_CNTL 0x1d00
269 #define GT64260_PCI_0_XBAR_CNTL_LO 0x1d08
270 #define GT64260_PCI_0_XBAR_CNTL_HI 0x1d0c
271 #define GT64260_PCI_0_XBAR_CNTL_TO 0x1d04
272 #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO 0x1d18
273 #define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI 0x1d1c
274 #define GT64260_PCI_0_SYNC_BARRIER 0x1d10
275 #define GT64260_PCI_0_P2P_CONFIG 0x1d14
276 #define GT64260_PCI_0_P2P_SWAP_CNTL 0x1d54
278 #define GT64260_PCI_1_CMD 0x0c80
279 #define GT64260_PCI_1_MODE 0x0d80
280 #define GT64260_PCI_1_TO_RETRY 0x0c84
281 #define GT64260_PCI_1_RD_BUF_DISCARD_TIMER 0x0d84
282 #define GT64260_PCI_1_MSI_TRIGGER_TIMER 0x0cb8
283 #define GT64260_PCI_1_ARBITER_CNTL 0x1d80
284 #define GT64260_PCI_1_XBAR_CNTL_LO 0x1d88
285 #define GT64260_PCI_1_XBAR_CNTL_HI 0x1d8c
286 #define GT64260_PCI_1_XBAR_CNTL_TO 0x1d84
287 #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO 0x1d98
288 #define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI 0x1d9c
289 #define GT64260_PCI_1_SYNC_BARRIER 0x1d90
290 #define GT64260_PCI_1_P2P_CONFIG 0x1d94
291 #define GT64260_PCI_1_P2P_SWAP_CNTL 0x1dd4
293 /* PCI Access Control Regions Registers */
294 #define GT64260_PCI_ACC_CNTL_WINDOWS 8
296 #define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12)
297 #define GT64260_PCI_ACC_CNTL_DREADEN (1<<13)
298 #define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16)
299 #define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17)
300 #define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18)
301 #define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS 0x00000000
302 #define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS 0x00100000
303 #define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS 0x00200000
304 #define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000
305 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000
306 #define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000
307 #define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000
308 #define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000
309 #define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000
310 #define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28)
311 #define GT64260_PCI_ACC_CNTL_WRPROT (1<<29)
313 #define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \
314 GT64260_PCI_ACC_CNTL_DREADEN | \
315 GT64260_PCI_ACC_CNTL_RDPREFETCH | \
316 GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\
317 GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \
318 GT64260_PCI_ACC_CNTL_MBURST_MASK | \
319 GT64260_PCI_ACC_CNTL_SWAP_MASK | \
320 GT64260_PCI_ACC_CNTL_ACCPROT| \
321 GT64260_PCI_ACC_CNTL_WRPROT)
323 #define GT64260_PCI_0_ACC_CNTL_0_BASE_LO 0x1e00
324 #define GT64260_PCI_0_ACC_CNTL_0_BASE_HI 0x1e04
325 #define GT64260_PCI_0_ACC_CNTL_0_TOP 0x1e08
326 #define GT64260_PCI_0_ACC_CNTL_1_BASE_LO 0x1e10
327 #define GT64260_PCI_0_ACC_CNTL_1_BASE_HI 0x1e14
328 #define GT64260_PCI_0_ACC_CNTL_1_TOP 0x1e18
329 #define GT64260_PCI_0_ACC_CNTL_2_BASE_LO 0x1e20
330 #define GT64260_PCI_0_ACC_CNTL_2_BASE_HI 0x1e24
331 #define GT64260_PCI_0_ACC_CNTL_2_TOP 0x1e28
332 #define GT64260_PCI_0_ACC_CNTL_3_BASE_LO 0x1e30
333 #define GT64260_PCI_0_ACC_CNTL_3_BASE_HI 0x1e34
334 #define GT64260_PCI_0_ACC_CNTL_3_TOP 0x1e38
335 #define GT64260_PCI_0_ACC_CNTL_4_BASE_LO 0x1e40
336 #define GT64260_PCI_0_ACC_CNTL_4_BASE_HI 0x1e44
337 #define GT64260_PCI_0_ACC_CNTL_4_TOP 0x1e48
338 #define GT64260_PCI_0_ACC_CNTL_5_BASE_LO 0x1e50
339 #define GT64260_PCI_0_ACC_CNTL_5_BASE_HI 0x1e54
340 #define GT64260_PCI_0_ACC_CNTL_5_TOP 0x1e58
341 #define GT64260_PCI_0_ACC_CNTL_6_BASE_LO 0x1e60
342 #define GT64260_PCI_0_ACC_CNTL_6_BASE_HI 0x1e64
343 #define GT64260_PCI_0_ACC_CNTL_6_TOP 0x1e68
344 #define GT64260_PCI_0_ACC_CNTL_7_BASE_LO 0x1e70
345 #define GT64260_PCI_0_ACC_CNTL_7_BASE_HI 0x1e74
346 #define GT64260_PCI_0_ACC_CNTL_7_TOP 0x1e78
348 #define GT64260_PCI_1_ACC_CNTL_0_BASE_LO 0x1e80
349 #define GT64260_PCI_1_ACC_CNTL_0_BASE_HI 0x1e84
350 #define GT64260_PCI_1_ACC_CNTL_0_TOP 0x1e88
351 #define GT64260_PCI_1_ACC_CNTL_1_BASE_LO 0x1e90
352 #define GT64260_PCI_1_ACC_CNTL_1_BASE_HI 0x1e94
353 #define GT64260_PCI_1_ACC_CNTL_1_TOP 0x1e98
354 #define GT64260_PCI_1_ACC_CNTL_2_BASE_LO 0x1ea0
355 #define GT64260_PCI_1_ACC_CNTL_2_BASE_HI 0x1ea4
356 #define GT64260_PCI_1_ACC_CNTL_2_TOP 0x1ea8
357 #define GT64260_PCI_1_ACC_CNTL_3_BASE_LO 0x1eb0
358 #define GT64260_PCI_1_ACC_CNTL_3_BASE_HI 0x1eb4
359 #define GT64260_PCI_1_ACC_CNTL_3_TOP 0x1eb8
360 #define GT64260_PCI_1_ACC_CNTL_4_BASE_LO 0x1ec0
361 #define GT64260_PCI_1_ACC_CNTL_4_BASE_HI 0x1ec4
362 #define GT64260_PCI_1_ACC_CNTL_4_TOP 0x1ec8
363 #define GT64260_PCI_1_ACC_CNTL_5_BASE_LO 0x1ed0
364 #define GT64260_PCI_1_ACC_CNTL_5_BASE_HI 0x1ed4
365 #define GT64260_PCI_1_ACC_CNTL_5_TOP 0x1ed8
366 #define GT64260_PCI_1_ACC_CNTL_6_BASE_LO 0x1ee0
367 #define GT64260_PCI_1_ACC_CNTL_6_BASE_HI 0x1ee4
368 #define GT64260_PCI_1_ACC_CNTL_6_TOP 0x1ee8
369 #define GT64260_PCI_1_ACC_CNTL_7_BASE_LO 0x1ef0
370 #define GT64260_PCI_1_ACC_CNTL_7_BASE_HI 0x1ef4
371 #define GT64260_PCI_1_ACC_CNTL_7_TOP 0x1ef8
373 /* PCI Snoop Control Registers */
374 #define GT64260_PCI_SNOOP_WINDOWS 4
376 #define GT64260_PCI_SNOOP_NONE 0x00000000
377 #define GT64260_PCI_SNOOP_WT 0x00001000
378 #define GT64260_PCI_SNOOP_WB 0x00002000
380 #define GT64260_PCI_0_SNOOP_0_BASE_LO 0x1f00
381 #define GT64260_PCI_0_SNOOP_0_BASE_HI 0x1f04
382 #define GT64260_PCI_0_SNOOP_0_TOP 0x1f08
383 #define GT64260_PCI_0_SNOOP_1_BASE_LO 0x1f10
384 #define GT64260_PCI_0_SNOOP_1_BASE_HI 0x1f14
385 #define GT64260_PCI_0_SNOOP_1_TOP 0x1f18
386 #define GT64260_PCI_0_SNOOP_2_BASE_LO 0x1f20
387 #define GT64260_PCI_0_SNOOP_2_BASE_HI 0x1f24
388 #define GT64260_PCI_0_SNOOP_2_TOP 0x1f28
389 #define GT64260_PCI_0_SNOOP_3_BASE_LO 0x1f30
390 #define GT64260_PCI_0_SNOOP_3_BASE_HI 0x1f34
391 #define GT64260_PCI_0_SNOOP_3_TOP 0x1f38
393 #define GT64260_PCI_1_SNOOP_0_BASE_LO 0x1f80
394 #define GT64260_PCI_1_SNOOP_0_BASE_HI 0x1f84
395 #define GT64260_PCI_1_SNOOP_0_TOP 0x1f88
396 #define GT64260_PCI_1_SNOOP_1_BASE_LO 0x1f90
397 #define GT64260_PCI_1_SNOOP_1_BASE_HI 0x1f94
398 #define GT64260_PCI_1_SNOOP_1_TOP 0x1f98
399 #define GT64260_PCI_1_SNOOP_2_BASE_LO 0x1fa0
400 #define GT64260_PCI_1_SNOOP_2_BASE_HI 0x1fa4
401 #define GT64260_PCI_1_SNOOP_2_TOP 0x1fa8
402 #define GT64260_PCI_1_SNOOP_3_BASE_LO 0x1fb0
403 #define GT64260_PCI_1_SNOOP_3_BASE_HI 0x1fb4
404 #define GT64260_PCI_1_SNOOP_3_TOP 0x1fb8
406 /* PCI Error Report Registers */
407 #define GT64260_PCI_0_ERR_SERR_MASK 0x0c28
408 #define GT64260_PCI_0_ERR_ADDR_LO 0x1d40
409 #define GT64260_PCI_0_ERR_ADDR_HI 0x1d44
410 #define GT64260_PCI_0_ERR_DATA_LO 0x1d48
411 #define GT64260_PCI_0_ERR_DATA_HI 0x1d4c
412 #define GT64260_PCI_0_ERR_CMD 0x1d50
413 #define GT64260_PCI_0_ERR_CAUSE 0x1d58
414 #define GT64260_PCI_0_ERR_MASK 0x1d5c
416 #define GT64260_PCI_1_ERR_SERR_MASK 0x0ca8
417 #define GT64260_PCI_1_ERR_ADDR_LO 0x1dc0
418 #define GT64260_PCI_1_ERR_ADDR_HI 0x1dc4
419 #define GT64260_PCI_1_ERR_DATA_LO 0x1dc8
420 #define GT64260_PCI_1_ERR_DATA_HI 0x1dcc
421 #define GT64260_PCI_1_ERR_CMD 0x1dd0
422 #define GT64260_PCI_1_ERR_CAUSE 0x1dd8
423 #define GT64260_PCI_1_ERR_MASK 0x1ddc
425 /* PCI Slave Address Decoding Registers */
426 #define GT64260_PCI_SCS_WINDOWS 4
427 #define GT64260_PCI_CS_WINDOWS 4
428 #define GT64260_PCI_BOOT_WINDOWS 1
429 #define GT64260_PCI_P2P_MEM_WINDOWS 2
430 #define GT64260_PCI_P2P_IO_WINDOWS 1
431 #define GT64260_PCI_DAC_SCS_WINDOWS 4
432 #define GT64260_PCI_DAC_CS_WINDOWS 4
433 #define GT64260_PCI_DAC_BOOT_WINDOWS 1
434 #define GT64260_PCI_DAC_P2P_MEM_WINDOWS 2
436 #define GT64260_PCI_0_SLAVE_SCS_0_SIZE 0x0c08
437 #define GT64260_PCI_0_SLAVE_SCS_1_SIZE 0x0d08
438 #define GT64260_PCI_0_SLAVE_SCS_2_SIZE 0x0c0c
439 #define GT64260_PCI_0_SLAVE_SCS_3_SIZE 0x0d0c
440 #define GT64260_PCI_0_SLAVE_CS_0_SIZE 0x0c10
441 #define GT64260_PCI_0_SLAVE_CS_1_SIZE 0x0d10
442 #define GT64260_PCI_0_SLAVE_CS_2_SIZE 0x0d18
443 #define GT64260_PCI_0_SLAVE_CS_3_SIZE 0x0c14
444 #define GT64260_PCI_0_SLAVE_BOOT_SIZE 0x0d14
445 #define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE 0x0d1c
446 #define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE 0x0d20
447 #define GT64260_PCI_0_SLAVE_P2P_IO_SIZE 0x0d24
448 #define GT64260_PCI_0_SLAVE_CPU_SIZE 0x0d28
450 #define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE 0x0e00
451 #define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE 0x0e04
452 #define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE 0x0e08
453 #define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE 0x0e0c
454 #define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE 0x0e10
455 #define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE 0x0e14
456 #define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE 0x0e18
457 #define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE 0x0e1c
458 #define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE 0x0e20
459 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE 0x0e24
460 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE 0x0e28
461 #define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE 0x0e2c
463 #define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE 0x0d2c
465 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0 (1<<0)
466 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1 (1<<1)
467 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2 (1<<2)
468 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3 (1<<3)
469 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0 (1<<4)
470 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1 (1<<5)
471 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2 (1<<6)
472 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3 (1<<7)
473 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT (1<<8)
474 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM (1<<9)
475 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO (1<<10)
476 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0 (1<<11)
477 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1 (1<<12)
478 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO (1<<13)
479 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU (1<<14)
480 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0 (1<<15)
481 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1 (1<<16)
482 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2 (1<<17)
483 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3 (1<<18)
484 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0 (1<<19)
485 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1 (1<<20)
486 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2 (1<<21)
487 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3 (1<<22)
488 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT (1<<23)
489 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24)
490 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25)
491 #define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU (1<<26)
493 #define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES 0x0c3c
494 #define GT64260_PCI_0_SLAVE_SCS_0_REMAP 0x0c48
495 #define GT64260_PCI_0_SLAVE_SCS_1_REMAP 0x0d48
496 #define GT64260_PCI_0_SLAVE_SCS_2_REMAP 0x0c4c
497 #define GT64260_PCI_0_SLAVE_SCS_3_REMAP 0x0d4c
498 #define GT64260_PCI_0_SLAVE_CS_0_REMAP 0x0c50
499 #define GT64260_PCI_0_SLAVE_CS_1_REMAP 0x0d50
500 #define GT64260_PCI_0_SLAVE_CS_2_REMAP 0x0d58
501 #define GT64260_PCI_0_SLAVE_CS_3_REMAP 0x0c54
502 #define GT64260_PCI_0_SLAVE_BOOT_REMAP 0x0d54
503 #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c
504 #define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60
505 #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64
506 #define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68
507 #define GT64260_PCI_0_SLAVE_P2P_IO_REMAP 0x0d6c
508 #define GT64260_PCI_0_SLAVE_CPU_REMAP 0x0d70
510 #define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP 0x0f00
511 #define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP 0x0f04
512 #define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP 0x0f08
513 #define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP 0x0f0c
514 #define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP 0x0f10
515 #define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP 0x0f14
516 #define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP 0x0f18
517 #define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP 0x0f1c
518 #define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP 0x0f20
519 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24
520 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28
521 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c
522 #define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30
523 #define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP 0x0f34
525 #define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP 0x0f38
526 #define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL 0x0d3c
528 #define GT64260_PCI_1_SLAVE_SCS_0_SIZE 0x0c88
529 #define GT64260_PCI_1_SLAVE_SCS_1_SIZE 0x0d88
530 #define GT64260_PCI_1_SLAVE_SCS_2_SIZE 0x0c8c
531 #define GT64260_PCI_1_SLAVE_SCS_3_SIZE 0x0d8c
532 #define GT64260_PCI_1_SLAVE_CS_0_SIZE 0x0c90
533 #define GT64260_PCI_1_SLAVE_CS_1_SIZE 0x0d90
534 #define GT64260_PCI_1_SLAVE_CS_2_SIZE 0x0d98
535 #define GT64260_PCI_1_SLAVE_CS_3_SIZE 0x0c94
536 #define GT64260_PCI_1_SLAVE_BOOT_SIZE 0x0d94
537 #define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE 0x0d9c
538 #define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE 0x0da0
539 #define GT64260_PCI_1_SLAVE_P2P_IO_SIZE 0x0da4
540 #define GT64260_PCI_1_SLAVE_CPU_SIZE 0x0da8
542 #define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE 0x0e80
543 #define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE 0x0e84
544 #define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE 0x0e88
545 #define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE 0x0e8c
546 #define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE 0x0e90
547 #define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE 0x0e94
548 #define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE 0x0e98
549 #define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE 0x0e9c
550 #define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE 0x0ea0
551 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4
552 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8
553 #define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE 0x0eac
555 #define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE 0x0dac
557 #define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES 0x0cbc
558 #define GT64260_PCI_1_SLAVE_SCS_0_REMAP 0x0cc8
559 #define GT64260_PCI_1_SLAVE_SCS_1_REMAP 0x0dc8
560 #define GT64260_PCI_1_SLAVE_SCS_2_REMAP 0x0ccc
561 #define GT64260_PCI_1_SLAVE_SCS_3_REMAP 0x0dcc
562 #define GT64260_PCI_1_SLAVE_CS_0_REMAP 0x0cd0
563 #define GT64260_PCI_1_SLAVE_CS_1_REMAP 0x0dd0
564 #define GT64260_PCI_1_SLAVE_CS_2_REMAP 0x0dd8
565 #define GT64260_PCI_1_SLAVE_CS_3_REMAP 0x0cd4
566 #define GT64260_PCI_1_SLAVE_BOOT_REMAP 0x0dd4
567 #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc
568 #define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0
569 #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4
570 #define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8
571 #define GT64260_PCI_1_SLAVE_P2P_IO_REMAP 0x0dec
572 #define GT64260_PCI_1_SLAVE_CPU_REMAP 0x0df0
574 #define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP 0x0f80
575 #define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP 0x0f84
576 #define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP 0x0f88
577 #define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP 0x0f8c
578 #define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP 0x0f90
579 #define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP 0x0f94
580 #define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP 0x0f98
581 #define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP 0x0f9c
582 #define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP 0x0fa0
583 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4
584 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8
585 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac
586 #define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0
587 #define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP 0x0fb4
589 #define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP 0x0fb8
590 #define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL 0x0dbc
594 *****************************************************************************
596 * I2O Controller Interface Registers
598 *****************************************************************************
606 *****************************************************************************
608 * DMA Controller Interface Registers
610 *****************************************************************************
617 *****************************************************************************
619 * Timer/Counter Interface Registers
621 *****************************************************************************
624 #define GT64260_TIMR_CNTR_0 0x0850
625 #define GT64260_TIMR_CNTR_1 0x0854
626 #define GT64260_TIMR_CNTR_2 0x0858
627 #define GT64260_TIMR_CNTR_3 0x085c
628 #define GT64260_TIMR_CNTR_4 0x0950
629 #define GT64260_TIMR_CNTR_5 0x0954
630 #define GT64260_TIMR_CNTR_6 0x0958
631 #define GT64260_TIMR_CNTR_7 0x095c
632 #define GT64260_TIMR_CNTR_0_3_CNTL 0x0864
633 #define GT64260_TIMR_CNTR_0_3_INTR_CAUSE 0x0868
634 #define GT64260_TIMR_CNTR_0_3_INTR_MASK 0x086c
635 #define GT64260_TIMR_CNTR_4_7_CNTL 0x0964
636 #define GT64260_TIMR_CNTR_4_7_INTR_CAUSE 0x0968
637 #define GT64260_TIMR_CNTR_4_7_INTR_MASK 0x096c
641 *****************************************************************************
643 * Communications Controller (Enet, Serial, etc.) Interface Registers
645 *****************************************************************************
648 #define GT64260_ENET_0_CNTL_LO 0xf200
649 #define GT64260_ENET_0_CNTL_HI 0xf204
650 #define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI 0xf208
651 #define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI 0xf20c
652 #define GT64260_ENET_0_RX_DESC_ADDR_HI 0xf210
653 #define GT64260_ENET_0_TX_DESC_ADDR_HI 0xf214
654 #define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI 0xf218
655 #define GT64260_ENET_1_CNTL_LO 0xf220
656 #define GT64260_ENET_1_CNTL_HI 0xf224
657 #define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI 0xf228
658 #define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI 0xf22c
659 #define GT64260_ENET_1_RX_DESC_ADDR_HI 0xf230
660 #define GT64260_ENET_1_TX_DESC_ADDR_HI 0xf234
661 #define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI 0xf238
662 #define GT64260_ENET_2_CNTL_LO 0xf240
663 #define GT64260_ENET_2_CNTL_HI 0xf244
664 #define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI 0xf248
665 #define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI 0xf24c
666 #define GT64260_ENET_2_RX_DESC_ADDR_HI 0xf250
667 #define GT64260_ENET_2_TX_DESC_ADDR_HI 0xf254
668 #define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI 0xf258
670 #define GT64260_MPSC_0_CNTL_LO 0xf280
671 #define GT64260_MPSC_0_CNTL_HI 0xf284
672 #define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI 0xf288
673 #define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI 0xf28c
674 #define GT64260_MPSC_0_RX_DESC_ADDR_HI 0xf290
675 #define GT64260_MPSC_0_TX_DESC_ADDR_HI 0xf294
676 #define GT64260_MPSC_1_CNTL_LO 0xf2c0
677 #define GT64260_MPSC_1_CNTL_HI 0xf2c4
678 #define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI 0xf2c8
679 #define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI 0xf2cc
680 #define GT64260_MPSC_1_RX_DESC_ADDR_HI 0xf2d0
681 #define GT64260_MPSC_1_TX_DESC_ADDR_HI 0xf2d4
683 #define GT64260_SER_INIT_PCI_ADDR_HI 0xf320
684 #define GT64260_SER_INIT_LAST_DATA 0xf324
685 #define GT64260_SER_INIT_CONTROL 0xf328
686 #define GT64260_SER_INIT_STATUS 0xf32c
688 #define GT64260_COMM_ARBITER_CNTL 0xf300
689 #define GT64260_COMM_CONFIG 0xb40c
690 #define GT64260_COMM_XBAR_TO 0xf304
691 #define GT64260_COMM_INTR_CAUSE 0xf310
692 #define GT64260_COMM_INTR_MASK 0xf314
693 #define GT64260_COMM_ERR_ADDR 0xf318
697 *****************************************************************************
699 * Fast Ethernet Controller Interface Registers
701 *****************************************************************************
704 #define GT64260_ENET_PHY_ADDR 0x2000
705 #define GT64260_ENET_ESMIR 0x2010
707 #define GT64260_ENET_E0PCR 0x2400
708 #define GT64260_ENET_E0PCXR 0x2408
709 #define GT64260_ENET_E0PCMR 0x2410
710 #define GT64260_ENET_E0PSR 0x2418
711 #define GT64260_ENET_E0SPR 0x2420
712 #define GT64260_ENET_E0HTPR 0x2428
713 #define GT64260_ENET_E0FCSAL 0x2430
714 #define GT64260_ENET_E0FCSAH 0x2438
715 #define GT64260_ENET_E0SDCR 0x2440
716 #define GT64260_ENET_E0SDCMR 0x2448
717 #define GT64260_ENET_E0ICR 0x2450
718 #define GT64260_ENET_E0IMR 0x2458
719 #define GT64260_ENET_E0FRDP0 0x2480
720 #define GT64260_ENET_E0FRDP1 0x2484
721 #define GT64260_ENET_E0FRDP2 0x2488
722 #define GT64260_ENET_E0FRDP3 0x248c
723 #define GT64260_ENET_E0CRDP0 0x24a0
724 #define GT64260_ENET_E0CRDP1 0x24a4
725 #define GT64260_ENET_E0CRDP2 0x24a8
726 #define GT64260_ENET_E0CRDP3 0x24ac
727 #define GT64260_ENET_E0CTDP0 0x24e0
728 #define GT64260_ENET_E0CTDP1 0x24e4
729 #define GT64260_ENET_0_DSCP2P0L 0x2460
730 #define GT64260_ENET_0_DSCP2P0H 0x2464
731 #define GT64260_ENET_0_DSCP2P1L 0x2468
732 #define GT64260_ENET_0_DSCP2P1H 0x246c
733 #define GT64260_ENET_0_VPT2P 0x2470
734 #define GT64260_ENET_0_MIB_CTRS 0x2500
736 #define GT64260_ENET_E1PCR 0x2800
737 #define GT64260_ENET_E1PCXR 0x2808
738 #define GT64260_ENET_E1PCMR 0x2810
739 #define GT64260_ENET_E1PSR 0x2818
740 #define GT64260_ENET_E1SPR 0x2820
741 #define GT64260_ENET_E1HTPR 0x2828
742 #define GT64260_ENET_E1FCSAL 0x2830
743 #define GT64260_ENET_E1FCSAH 0x2838
744 #define GT64260_ENET_E1SDCR 0x2840
745 #define GT64260_ENET_E1SDCMR 0x2848
746 #define GT64260_ENET_E1ICR 0x2850
747 #define GT64260_ENET_E1IMR 0x2858
748 #define GT64260_ENET_E1FRDP0 0x2880
749 #define GT64260_ENET_E1FRDP1 0x2884
750 #define GT64260_ENET_E1FRDP2 0x2888
751 #define GT64260_ENET_E1FRDP3 0x288c
752 #define GT64260_ENET_E1CRDP0 0x28a0
753 #define GT64260_ENET_E1CRDP1 0x28a4
754 #define GT64260_ENET_E1CRDP2 0x28a8
755 #define GT64260_ENET_E1CRDP3 0x28ac
756 #define GT64260_ENET_E1CTDP0 0x28e0
757 #define GT64260_ENET_E1CTDP1 0x28e4
758 #define GT64260_ENET_1_DSCP2P0L 0x2860
759 #define GT64260_ENET_1_DSCP2P0H 0x2864
760 #define GT64260_ENET_1_DSCP2P1L 0x2868
761 #define GT64260_ENET_1_DSCP2P1H 0x286c
762 #define GT64260_ENET_1_VPT2P 0x2870
763 #define GT64260_ENET_1_MIB_CTRS 0x2900
765 #define GT64260_ENET_E2PCR 0x2c00
766 #define GT64260_ENET_E2PCXR 0x2c08
767 #define GT64260_ENET_E2PCMR 0x2c10
768 #define GT64260_ENET_E2PSR 0x2c18
769 #define GT64260_ENET_E2SPR 0x2c20
770 #define GT64260_ENET_E2HTPR 0x2c28
771 #define GT64260_ENET_E2FCSAL 0x2c30
772 #define GT64260_ENET_E2FCSAH 0x2c38
773 #define GT64260_ENET_E2SDCR 0x2c40
774 #define GT64260_ENET_E2SDCMR 0x2c48
775 #define GT64260_ENET_E2ICR 0x2c50
776 #define GT64260_ENET_E2IMR 0x2c58
777 #define GT64260_ENET_E2FRDP0 0x2c80
778 #define GT64260_ENET_E2FRDP1 0x2c84
779 #define GT64260_ENET_E2FRDP2 0x2c88
780 #define GT64260_ENET_E2FRDP3 0x2c8c
781 #define GT64260_ENET_E2CRDP0 0x2ca0
782 #define GT64260_ENET_E2CRDP1 0x2ca4
783 #define GT64260_ENET_E2CRDP2 0x2ca8
784 #define GT64260_ENET_E2CRDP3 0x2cac
785 #define GT64260_ENET_E2CTDP0 0x2ce0
786 #define GT64260_ENET_E2CTDP1 0x2ce4
787 #define GT64260_ENET_2_DSCP2P0L 0x2c60
788 #define GT64260_ENET_2_DSCP2P0H 0x2c64
789 #define GT64260_ENET_2_DSCP2P1L 0x2c68
790 #define GT64260_ENET_2_DSCP2P1H 0x2c6c
791 #define GT64260_ENET_2_VPT2P 0x2c70
792 #define GT64260_ENET_2_MIB_CTRS 0x2d00
796 *****************************************************************************
798 * Multi-Protocol Serial Controller Interface Registers
800 *****************************************************************************
804 #define GT64260_MPSC_MRR 0xb400
805 #define GT64260_MPSC_RCRR 0xb404
806 #define GT64260_MPSC_TCRR 0xb408
808 /* Main Configuratino Registers */
809 #define GT64260_MPSC_0_MMCRL 0x8000
810 #define GT64260_MPSC_0_MMCRH 0x8004
811 #define GT64260_MPSC_0_MPCR 0x8008
812 #define GT64260_MPSC_0_CHR_1 0x800c
813 #define GT64260_MPSC_0_CHR_2 0x8010
814 #define GT64260_MPSC_0_CHR_3 0x8014
815 #define GT64260_MPSC_0_CHR_4 0x8018
816 #define GT64260_MPSC_0_CHR_5 0x801c
817 #define GT64260_MPSC_0_CHR_6 0x8020
818 #define GT64260_MPSC_0_CHR_7 0x8024
819 #define GT64260_MPSC_0_CHR_8 0x8028
820 #define GT64260_MPSC_0_CHR_9 0x802c
821 #define GT64260_MPSC_0_CHR_10 0x8030
822 #define GT64260_MPSC_0_CHR_11 0x8034
824 #define GT64260_MPSC_1_MMCRL 0x9000
825 #define GT64260_MPSC_1_MMCRH 0x9004
826 #define GT64260_MPSC_1_MPCR 0x9008
827 #define GT64260_MPSC_1_CHR_1 0x900c
828 #define GT64260_MPSC_1_CHR_2 0x9010
829 #define GT64260_MPSC_1_CHR_3 0x9014
830 #define GT64260_MPSC_1_CHR_4 0x9018
831 #define GT64260_MPSC_1_CHR_5 0x901c
832 #define GT64260_MPSC_1_CHR_6 0x9020
833 #define GT64260_MPSC_1_CHR_7 0x9024
834 #define GT64260_MPSC_1_CHR_8 0x9028
835 #define GT64260_MPSC_1_CHR_9 0x902c
836 #define GT64260_MPSC_1_CHR_10 0x9030
837 #define GT64260_MPSC_1_CHR_11 0x9034
839 #define GT64260_MPSC_0_INTR_CAUSE 0xb804
840 #define GT64260_MPSC_0_INTR_MASK 0xb884
841 #define GT64260_MPSC_1_INTR_CAUSE 0xb80c
842 #define GT64260_MPSC_1_INTR_MASK 0xb88c
844 #define GT64260_MPSC_UART_CR_TEV (1<<1)
845 #define GT64260_MPSC_UART_CR_TA (1<<7)
846 #define GT64260_MPSC_UART_CR_TTCS (1<<9)
847 #define GT64260_MPSC_UART_CR_REV (1<<17)
848 #define GT64260_MPSC_UART_CR_RA (1<<23)
849 #define GT64260_MPSC_UART_CR_CRD (1<<25)
850 #define GT64260_MPSC_UART_CR_EH (1<<31)
852 #define GT64260_MPSC_UART_ESR_CTS (1<<0)
853 #define GT64260_MPSC_UART_ESR_CD (1<<1)
854 #define GT64260_MPSC_UART_ESR_TIDLE (1<<3)
855 #define GT64260_MPSC_UART_ESR_RHS (1<<5)
856 #define GT64260_MPSC_UART_ESR_RLS (1<<7)
857 #define GT64260_MPSC_UART_ESR_RLIDL (1<<11)
861 *****************************************************************************
863 * IDMA Controller Interface Registers
865 *****************************************************************************
868 #define GT64260_IDMA_0_BYTE_COUNT 0x0800
869 #define GT64260_IDMA_1_BYTE_COUNT 0x0804
870 #define GT64260_IDMA_2_BYTE_COUNT 0x0808
871 #define GT64260_IDMA_3_BYTE_COUNT 0x080c
872 #define GT64260_IDMA_4_BYTE_COUNT 0x0900
873 #define GT64260_IDMA_5_BYTE_COUNT 0x0904
874 #define GT64260_IDMA_6_BYTE_COUNT 0x0908
875 #define GT64260_IDMA_7_BYTE_COUNT 0x090c
877 #define GT64260_IDMA_0_SRC_ADDR 0x0810
878 #define GT64260_IDMA_1_SRC_ADDR 0x0814
879 #define GT64260_IDMA_2_SRC_ADDR 0x0818
880 #define GT64260_IDMA_3_SRC_ADDR 0x081c
881 #define GT64260_IDMA_4_SRC_ADDR 0x0910
882 #define GT64260_IDMA_5_SRC_ADDR 0x0914
883 #define GT64260_IDMA_6_SRC_ADDR 0x0918
884 #define GT64260_IDMA_7_SRC_ADDR 0x091c
886 #define GT64260_IDMA_0_DST_ADDR 0x0820
887 #define GT64260_IDMA_1_DST_ADDR 0x0824
888 #define GT64260_IDMA_2_DST_ADDR 0x0828
889 #define GT64260_IDMA_3_DST_ADDR 0x082c
890 #define GT64260_IDMA_4_DST_ADDR 0x0920
891 #define GT64260_IDMA_5_DST_ADDR 0x0924
892 #define GT64260_IDMA_6_DST_ADDR 0x0928
893 #define GT64260_IDMA_7_DST_ADDR 0x092c
895 #define GT64260_IDMA_0_NEXT_DESC 0x0830
896 #define GT64260_IDMA_1_NEXT_DESC 0x0834
897 #define GT64260_IDMA_2_NEXT_DESC 0x0838
898 #define GT64260_IDMA_3_NEXT_DESC 0x083c
899 #define GT64260_IDMA_4_NEXT_DESC 0x0930
900 #define GT64260_IDMA_5_NEXT_DESC 0x0934
901 #define GT64260_IDMA_6_NEXT_DESC 0x0938
902 #define GT64260_IDMA_7_NEXT_DESC 0x093c
904 #define GT64260_IDMA_0_CUR_DESC 0x0870
905 #define GT64260_IDMA_1_CUR_DESC 0x0874
906 #define GT64260_IDMA_2_CUR_DESC 0x0878
907 #define GT64260_IDMA_3_CUR_DESC 0x087c
908 #define GT64260_IDMA_4_CUR_DESC 0x0970
909 #define GT64260_IDMA_5_CUR_DESC 0x0974
910 #define GT64260_IDMA_6_CUR_DESC 0x0978
911 #define GT64260_IDMA_7_CUR_DESC 0x097c
913 #define GT64260_IDMA_0_SRC_PCI_ADDR_HI 0x0890
914 #define GT64260_IDMA_1_SRC_PCI_ADDR_HI 0x0894
915 #define GT64260_IDMA_2_SRC_PCI_ADDR_HI 0x0898
916 #define GT64260_IDMA_3_SRC_PCI_ADDR_HI 0x089c
917 #define GT64260_IDMA_4_SRC_PCI_ADDR_HI 0x0990
918 #define GT64260_IDMA_5_SRC_PCI_ADDR_HI 0x0994
919 #define GT64260_IDMA_6_SRC_PCI_ADDR_HI 0x0998
920 #define GT64260_IDMA_7_SRC_PCI_ADDR_HI 0x099c
922 #define GT64260_IDMA_0_DST_PCI_ADDR_HI 0x08a0
923 #define GT64260_IDMA_1_DST_PCI_ADDR_HI 0x08a4
924 #define GT64260_IDMA_2_DST_PCI_ADDR_HI 0x08a8
925 #define GT64260_IDMA_3_DST_PCI_ADDR_HI 0x08ac
926 #define GT64260_IDMA_4_DST_PCI_ADDR_HI 0x09a0
927 #define GT64260_IDMA_5_DST_PCI_ADDR_HI 0x09a4
928 #define GT64260_IDMA_6_DST_PCI_ADDR_HI 0x09a8
929 #define GT64260_IDMA_7_DST_PCI_ADDR_HI 0x09ac
931 #define GT64260_IDMA_0_NEXT_DESC_PCI_ADDR_HI 0x08b0
932 #define GT64260_IDMA_1_NEXT_DESC_PCI_ADDR_HI 0x08b4
933 #define GT64260_IDMA_2_NEXT_DESC_PCI_ADDR_HI 0x08b8
934 #define GT64260_IDMA_3_NEXT_DESC_PCI_ADDR_HI 0x08bc
935 #define GT64260_IDMA_4_NEXT_DESC_PCI_ADDR_HI 0x09b0
936 #define GT64260_IDMA_5_NEXT_DESC_PCI_ADDR_HI 0x09b4
937 #define GT64260_IDMA_6_NEXT_DESC_PCI_ADDR_HI 0x09b8
938 #define GT64260_IDMA_7_NEXT_DESC_PCI_ADDR_HI 0x09bc
940 #define GT64260_IDMA_0_CONTROL_LO 0x0840
941 #define GT64260_IDMA_0_CONTROL_HI 0x0880
942 #define GT64260_IDMA_1_CONTROL_LO 0x0844
943 #define GT64260_IDMA_1_CONTROL_HI 0x0884
944 #define GT64260_IDMA_2_CONTROL_LO 0x0848
945 #define GT64260_IDMA_2_CONTROL_HI 0x0888
946 #define GT64260_IDMA_3_CONTROL_LO 0x084c
947 #define GT64260_IDMA_3_CONTROL_HI 0x088c
948 #define GT64260_IDMA_4_CONTROL_LO 0x0940
949 #define GT64260_IDMA_4_CONTROL_HI 0x0980
950 #define GT64260_IDMA_5_CONTROL_LO 0x0944
951 #define GT64260_IDMA_5_CONTROL_HI 0x0984
952 #define GT64260_IDMA_6_CONTROL_LO 0x0948
953 #define GT64260_IDMA_6_CONTROL_HI 0x0988
954 #define GT64260_IDMA_7_CONTROL_LO 0x094c
955 #define GT64260_IDMA_7_CONTROL_HI 0x098c
957 #define GT64260_IDMA_0_3_ARBITER_CNTL 0x0860
958 #define GT64260_IDMA_4_7_ARBITER_CNTL 0x0960
960 #define GT64260_IDMA_0_3_XBAR_TO 0x08d0
961 #define GT64260_IDMA_4_7_XBAR_TO 0x09d0
963 #define GT64260_IDMA_0_3_INTR_CAUSE 0x08c0
964 #define GT64260_IDMA_0_3_INTR_MASK 0x08c4
965 #define GT64260_IDMA_0_3_ERROR_ADDR 0x08c8
966 #define GT64260_IDMA_0_3_ERROR_SELECT 0x08cc
967 #define GT64260_IDMA_4_7_INTR_CAUSE 0x09c0
968 #define GT64260_IDMA_4_7_INTR_MASK 0x09c4
969 #define GT64260_IDMA_4_7_ERROR_ADDR 0x09c8
970 #define GT64260_IDMA_4_7_ERROR_SELECT 0x09cc
973 *****************************************************************************
975 * Serial DMA Controller Interface Registers
977 *****************************************************************************
980 #define GT64260_SDMA_0_SDC 0x4000
981 #define GT64260_SDMA_0_SDCM 0x4008
982 #define GT64260_SDMA_0_RX_DESC 0x4800
983 #define GT64260_SDMA_0_RX_BUF_PTR 0x4808
984 #define GT64260_SDMA_0_SCRDP 0x4810
985 #define GT64260_SDMA_0_TX_DESC 0x4c00
986 #define GT64260_SDMA_0_SCTDP 0x4c10
987 #define GT64260_SDMA_0_SFTDP 0x4c14
989 #define GT64260_SDMA_1_SDC 0x6000
990 #define GT64260_SDMA_1_SDCM 0x6008
991 #define GT64260_SDMA_1_RX_DESC 0x6800
992 #define GT64260_SDMA_1_RX_BUF_PTR 0x6808
993 #define GT64260_SDMA_1_SCRDP 0x6810
994 #define GT64260_SDMA_1_TX_DESC 0x6c00
995 #define GT64260_SDMA_1_SCTDP 0x6c10
996 #define GT64260_SDMA_1_SFTDP 0x6c14
998 #define GT64260_SDMA_INTR_CAUSE 0xb800
999 #define GT64260_SDMA_INTR_MASK 0xb880
1001 #define GT64260_SDMA_DESC_CMDSTAT_PE (1<<0)
1002 #define GT64260_SDMA_DESC_CMDSTAT_CDL (1<<1)
1003 #define GT64260_SDMA_DESC_CMDSTAT_FR (1<<3)
1004 #define GT64260_SDMA_DESC_CMDSTAT_OR (1<<6)
1005 #define GT64260_SDMA_DESC_CMDSTAT_BR (1<<9)
1006 #define GT64260_SDMA_DESC_CMDSTAT_MI (1<<10)
1007 #define GT64260_SDMA_DESC_CMDSTAT_A (1<<11)
1008 #define GT64260_SDMA_DESC_CMDSTAT_AM (1<<12)
1009 #define GT64260_SDMA_DESC_CMDSTAT_CT (1<<13)
1010 #define GT64260_SDMA_DESC_CMDSTAT_C (1<<14)
1011 #define GT64260_SDMA_DESC_CMDSTAT_ES (1<<15)
1012 #define GT64260_SDMA_DESC_CMDSTAT_L (1<<16)
1013 #define GT64260_SDMA_DESC_CMDSTAT_F (1<<17)
1014 #define GT64260_SDMA_DESC_CMDSTAT_P (1<<18)
1015 #define GT64260_SDMA_DESC_CMDSTAT_EI (1<<23)
1016 #define GT64260_SDMA_DESC_CMDSTAT_O (1<<31)
1018 #define GT64260_SDMA_SDC_RFT (1<<0)
1019 #define GT64260_SDMA_SDC_SFM (1<<1)
1020 #define GT64260_SDMA_SDC_BLMR (1<<6)
1021 #define GT64260_SDMA_SDC_BLMT (1<<7)
1022 #define GT64260_SDMA_SDC_POVR (1<<8)
1023 #define GT64260_SDMA_SDC_RIFB (1<<9)
1025 #define GT64260_SDMA_SDCM_ERD (1<<7)
1026 #define GT64260_SDMA_SDCM_AR (1<<15)
1027 #define GT64260_SDMA_SDCM_STD (1<<16)
1028 #define GT64260_SDMA_SDCM_TXD (1<<23)
1029 #define GT64260_SDMA_SDCM_AT (1<<31)
1031 #define GT64260_SDMA_0_CAUSE_RXBUF (1<<0)
1032 #define GT64260_SDMA_0_CAUSE_RXERR (1<<1)
1033 #define GT64260_SDMA_0_CAUSE_TXBUF (1<<2)
1034 #define GT64260_SDMA_0_CAUSE_TXEND (1<<3)
1035 #define GT64260_SDMA_1_CAUSE_RXBUF (1<<8)
1036 #define GT64260_SDMA_1_CAUSE_RXERR (1<<9)
1037 #define GT64260_SDMA_1_CAUSE_TXBUF (1<<10)
1038 #define GT64260_SDMA_1_CAUSE_TXEND (1<<11)
1042 *****************************************************************************
1044 * Baud Rate Generator Interface Registers
1046 *****************************************************************************
1049 #define GT64260_BRG_0_BCR 0xb200
1050 #define GT64260_BRG_0_BTR 0xb204
1051 #define GT64260_BRG_1_BCR 0xb208
1052 #define GT64260_BRG_1_BTR 0xb20c
1053 #define GT64260_BRG_2_BCR 0xb210
1054 #define GT64260_BRG_2_BTR 0xb214
1056 #define GT64260_BRG_INTR_CAUSE 0xb834
1057 #define GT64260_BRG_INTR_MASK 0xb8b4
1061 *****************************************************************************
1063 * Watchdog Timer Interface Registers
1065 *****************************************************************************
1068 #define GT64260_WDT_WDC 0xb410
1069 #define GT64260_WDT_WDV 0xb414
1073 *****************************************************************************
1075 * General Purpose Pins Controller Interface Registers
1077 *****************************************************************************
1080 #define GT64260_GPP_IO_CNTL 0xf100
1081 #define GT64260_GPP_LEVEL_CNTL 0xf110
1082 #define GT64260_GPP_VALUE 0xf104
1083 #define GT64260_GPP_INTR_CAUSE 0xf108
1084 #define GT64260_GPP_INTR_MASK 0xf10c
1088 *****************************************************************************
1090 * Multi-Purpose Pins Controller Interface Registers
1092 *****************************************************************************
1095 #define GT64260_MPP_CNTL_0 0xf000
1096 #define GT64260_MPP_CNTL_1 0xf004
1097 #define GT64260_MPP_CNTL_2 0xf008
1098 #define GT64260_MPP_CNTL_3 0xf00c
1099 #define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010
1103 *****************************************************************************
1105 * I2C Controller Interface Registers
1107 *****************************************************************************
1110 /* FIXME: fill in */
1114 *****************************************************************************
1116 * Interrupt Controller Interface Registers
1118 *****************************************************************************
1121 #define GT64260_IC_MAIN_CAUSE_LO 0x0c18
1122 #define GT64260_IC_MAIN_CAUSE_HI 0x0c68
1123 #define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c
1124 #define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c
1125 #define GT64260_IC_CPU_SELECT_CAUSE 0x0c70
1126 #define GT64260_IC_PCI_0_INTR_MASK_LO 0x0c24
1127 #define GT64260_IC_PCI_0_INTR_MASK_HI 0x0c64
1128 #define GT64260_IC_PCI_0_SELECT_CAUSE 0x0c74
1129 #define GT64260_IC_PCI_1_INTR_MASK_LO 0x0ca4
1130 #define GT64260_IC_PCI_1_INTR_MASK_HI 0x0ce4
1131 #define GT64260_IC_PCI_1_SELECT_CAUSE 0x0cf4
1132 #define GT64260_IC_CPU_INT_0_MASK 0x0e60
1133 #define GT64260_IC_CPU_INT_1_MASK 0x0e64
1134 #define GT64260_IC_CPU_INT_2_MASK 0x0e68
1135 #define GT64260_IC_CPU_INT_3_MASK 0x0e6c
1138 #endif /* __ASMPPC_GT64260_DEFS_H */