2 * BK Id: SCCS/s.pci-bridge.h 1.21 09/13/02 11:39:44 mporter
5 #ifndef _ASM_PCI_BRIDGE_H
6 #define _ASM_PCI_BRIDGE_H
8 #include <linux/ioport.h>
12 struct pci_controller;
15 * pci_io_base returns the memory address at which you can access
16 * the I/O space for PCI bus number `bus' (or NULL on error).
18 extern void *pci_bus_io_base(unsigned int bus);
19 extern unsigned long pci_bus_io_base_phys(unsigned int bus);
20 extern unsigned long pci_bus_mem_base_phys(unsigned int bus);
22 /* Allocate a new PCI host bridge structure */
23 extern struct pci_controller* pcibios_alloc_controller(void);
25 /* Helper function for setting up resources */
26 extern void pci_init_resource(struct resource *res, unsigned long start,
27 unsigned long end, int flags, char *name);
30 * PCI <-> OF matching functions
32 extern int pci_device_from_OF_node(struct device_node *node,
34 extern struct device_node* pci_device_to_OF_node(struct pci_dev *);
35 extern void pci_create_OF_bus_map(void);
37 /* Get the PCI host controller for a bus */
38 extern struct pci_controller* pci_bus_to_hose(int bus);
40 /* Get the PCI host controller for an OF device */
41 extern struct pci_controller*
42 pci_find_hose_for_OF_device(struct device_node* node);
44 /* Fill up host controller resources from the OF node */
46 pci_process_bridge_OF_ranges(struct pci_controller *hose,
47 struct device_node *dev, int primary);
50 * Structure of a PCI controller (host bridge)
52 struct pci_controller {
53 int index; /* used for pci_controller_num */
54 struct pci_controller *next;
63 unsigned long io_base_phys;
65 /* Some machines (PReP) have a non 1:1 mapping of
66 * the PCI memory space in the CPU bus space
68 unsigned long pci_mem_offset;
71 volatile unsigned int *cfg_addr;
72 volatile unsigned char *cfg_data;
74 * If set, indirect method will set the cfg_type bit as
75 * needed to generate type 1 configuration transactions.
79 /* Currently, we limit ourselves to 1 IO range and 3 mem
80 * ranges since the common pci_bus structure can't handle more
82 struct resource io_resource;
83 struct resource mem_resources[3];
84 int mem_resource_count;
86 /* Host bridge I/O and Memory space
87 * Used for BAR placement algorithms
89 struct resource io_space;
90 struct resource mem_space;
93 /* These are used for config access before all the PCI probing
95 int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn,
97 int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn,
99 int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn,
100 int where, u32 *val);
101 int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn,
103 int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn,
105 int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn,
108 extern void setup_indirect_pci(struct pci_controller* hose,
109 u32 cfg_addr, u32 cfg_data);
110 extern void setup_grackle(struct pci_controller *hose);
112 extern unsigned char common_swizzle(struct pci_dev *, unsigned char *);
115 * The following code swizzles for exactly one bridge. The routine
116 * common_swizzle below handles multiple bridges. But there are a
117 * some boards that don't follow the PCI spec's suggestion so we
118 * break this piece out separately.
120 static inline unsigned char bridge_swizzle(unsigned char pin,
123 return (((pin-1) + idsel) % 4) + 1;
127 * The following macro is used to lookup irqs in a standard table
128 * format for those PPC systems that do not already have PCI
129 * interrupts properly routed.
131 /* FIXME - double check this */
132 #define PCI_IRQ_TABLE_LOOKUP \
133 ({ long _ctl_ = -1; \
134 if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \
135 _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \
139 * Scan the buses below a given PCI host bridge and assign suitable
140 * resources to all devices found.
142 extern int pciauto_bus_scan(struct pci_controller *, int);
145 #endif /* __KERNEL__ */