2 * linux/include/asm/dma.h: Defines for using and allocating dma channels.
3 * Written by Hennus Bergman, 1992.
4 * High DMA channel support & info by Hannu Savolainen
5 * and John Boyd, Nov. 1992.
6 * Changes for ppc sound by Christoph Nadig
8 * changed name to ppc_isa_dma.h so that dma.h could be more generic. -
14 #include <linux/config.h>
15 #include <linux/spinlock.h>
16 #include <linux/sched.h>
17 #include <asm/system.h>
20 * Note: Adapted for PowerPC by Gary Thomas
21 * Modified by Cort Dougan <cort@cs.nmt.edu>
23 * None of this really applies for Power Macintoshes. There is
24 * basically just enough here to get kernel/dma.c to compile.
26 * There may be some comments or restrictions made here which are
27 * not valid for the PReP platform. Take what you read
28 * with a grain of salt.
31 #ifndef __ASM_PPC_ISA_DMA_H__
32 #define __ASM_PPC_ISA_DMA_H__
35 * NOTES about DMA transfers:
37 * controller 1: channels 0-3, byte operations, ports 00-1F
38 * controller 2: channels 4-7, word operations, ports C0-DF
40 * - ALL registers are 8 bits only, regardless of transfer size
41 * - channel 4 is not used - cascades 1 into 2.
42 * - channels 0-3 are byte - addresses/counts are for physical bytes
43 * - channels 5-7 are word - addresses/counts are for physical words
44 * - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
45 * - transfer count loaded to registers is 1 less than actual count
46 * - controller 2 offsets are all even (2x offsets for controller 1)
47 * - page registers for 5-7 don't use data bit 0, represent 128K pages
48 * - page registers for 0-3 use bit 0, represent 64K pages
50 * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory.
51 * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing.
52 * Note that addresses loaded into registers must be _physical_ addresses,
53 * not logical addresses (which may differ if paging is active).
55 * Address mapping for channels 0-3:
57 * A23 ... A16 A15 ... A8 A7 ... A0 (Physical addresses)
58 * | ... | | ... | | ... |
59 * | ... | | ... | | ... |
60 * | ... | | ... | | ... |
61 * P7 ... P0 A7 ... A0 A7 ... A0
62 * | Page | Addr MSB | Addr LSB | (DMA registers)
64 * Address mapping for channels 5-7:
66 * A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0 (Physical addresses)
67 * | ... | \ \ ... \ \ \ ... \ \
68 * | ... | \ \ ... \ \ \ ... \ (not used)
69 * | ... | \ \ ... \ \ \ ... \
70 * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
71 * | Page | Addr MSB | Addr LSB | (DMA registers)
73 * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
74 * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
75 * the hardware level, so odd-byte transfers aren't possible).
77 * Transfer count (_not # bytes_) is limited to 64K, represented as actual
78 * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
79 * and up to 128K bytes may be transferred on channels 5-7 in one operation.
83 /* see prep_setup_arch() for detailed informations */
84 #if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_ALL_PPC)
85 extern long ppc_cs4232_dma, ppc_cs4232_dma2;
86 #define SND_DMA1 ppc_cs4232_dma
87 #define SND_DMA2 ppc_cs4232_dma2
93 /* 8237 DMA controllers */
94 #define IO_DMA1_BASE 0x00 /* 8 bit slave DMA, channels 0..3 */
95 #define IO_DMA2_BASE 0xC0 /* 16 bit master DMA, ch 4(=slave input)..7 */
97 /* DMA controller registers */
98 #define DMA1_CMD_REG 0x08 /* command register (w) */
99 #define DMA1_STAT_REG 0x08 /* status register (r) */
100 #define DMA1_REQ_REG 0x09 /* request register (w) */
101 #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */
102 #define DMA1_MODE_REG 0x0B /* mode register (w) */
103 #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */
104 #define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */
105 #define DMA1_RESET_REG 0x0D /* Master Clear (w) */
106 #define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */
107 #define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */
109 #define DMA2_CMD_REG 0xD0 /* command register (w) */
110 #define DMA2_STAT_REG 0xD0 /* status register (r) */
111 #define DMA2_REQ_REG 0xD2 /* request register (w) */
112 #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */
113 #define DMA2_MODE_REG 0xD6 /* mode register (w) */
114 #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */
115 #define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */
116 #define DMA2_RESET_REG 0xDA /* Master Clear (w) */
117 #define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */
118 #define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */
120 #define DMA_ADDR_0 0x00 /* DMA address registers */
121 #define DMA_ADDR_1 0x02
122 #define DMA_ADDR_2 0x04
123 #define DMA_ADDR_3 0x06
124 #define DMA_ADDR_4 0xC0
125 #define DMA_ADDR_5 0xC4
126 #define DMA_ADDR_6 0xC8
127 #define DMA_ADDR_7 0xCC
129 #define DMA_CNT_0 0x01 /* DMA count registers */
130 #define DMA_CNT_1 0x03
131 #define DMA_CNT_2 0x05
132 #define DMA_CNT_3 0x07
133 #define DMA_CNT_4 0xC2
134 #define DMA_CNT_5 0xC6
135 #define DMA_CNT_6 0xCA
136 #define DMA_CNT_7 0xCE
138 #define DMA_LO_PAGE_0 0x87 /* DMA page registers */
139 #define DMA_LO_PAGE_1 0x83
140 #define DMA_LO_PAGE_2 0x81
141 #define DMA_LO_PAGE_3 0x82
142 #define DMA_LO_PAGE_5 0x8B
143 #define DMA_LO_PAGE_6 0x89
144 #define DMA_LO_PAGE_7 0x8A
146 #define DMA_HI_PAGE_0 0x487 /* DMA page registers */
147 #define DMA_HI_PAGE_1 0x483
148 #define DMA_HI_PAGE_2 0x481
149 #define DMA_HI_PAGE_3 0x482
150 #define DMA_HI_PAGE_5 0x48B
151 #define DMA_HI_PAGE_6 0x489
152 #define DMA_HI_PAGE_7 0x48A
154 #define DMA1_EXT_REG 0x40B
155 #define DMA2_EXT_REG 0x4D6
157 #define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */
158 #define DMA_AUTOINIT 0x10
160 extern spinlock_t dma_spin_lock;
162 static __inline__ unsigned long
166 spin_lock_irqsave(&dma_spin_lock, flags);
170 static __inline__ void
171 release_dma_lock(unsigned long flags)
173 spin_unlock_irqrestore(&dma_spin_lock, flags);
176 /* enable/disable a specific DMA channel */
177 static __inline__ void
178 enable_dma(unsigned int dmanr)
180 unsigned char ucDmaCmd = 0x00;
183 dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */
184 dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */
187 dma_outb(dmanr, DMA1_MASK_REG);
188 dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */
190 dma_outb(dmanr & 3, DMA2_MASK_REG);
193 static __inline__ void
194 disable_dma(unsigned int dmanr)
197 dma_outb(dmanr | 4, DMA1_MASK_REG);
199 dma_outb((dmanr & 3) | 4, DMA2_MASK_REG);
202 /* Clear the 'DMA Pointer Flip Flop'.
203 * Write 0 for LSB/MSB, 1 for MSB/LSB access.
204 * Use this once to initialize the FF to a known state.
205 * After that, keep track of it. :-)
206 * --- In order to do that, the DMA routines below should ---
207 * --- only be used while interrupts are disabled! ---
209 static __inline__ void
210 clear_dma_ff(unsigned int dmanr)
213 dma_outb(0, DMA1_CLEAR_FF_REG);
215 dma_outb(0, DMA2_CLEAR_FF_REG);
218 /* set mode (above) for a specific DMA channel */
219 static __inline__ void
220 set_dma_mode(unsigned int dmanr, char mode)
223 dma_outb(mode | dmanr, DMA1_MODE_REG);
225 dma_outb(mode | (dmanr & 3), DMA2_MODE_REG);
228 /* Set only the page register bits of the transfer address.
229 * This is used for successive transfers when we know the contents of
230 * the lower 16 bits of the DMA current address register, but a 64k boundary
231 * may have been crossed.
233 static __inline__ void
234 set_dma_page(unsigned int dmanr, int pagenr)
238 dma_outb(pagenr, DMA_LO_PAGE_0);
239 dma_outb(pagenr >> 8, DMA_HI_PAGE_0);
242 dma_outb(pagenr, DMA_LO_PAGE_1);
243 dma_outb(pagenr >> 8, DMA_HI_PAGE_1);
246 dma_outb(pagenr, DMA_LO_PAGE_2);
247 dma_outb(pagenr >> 8, DMA_HI_PAGE_2);
250 dma_outb(pagenr, DMA_LO_PAGE_3);
251 dma_outb(pagenr >> 8, DMA_HI_PAGE_3);
254 if (SND_DMA1 == 5 || SND_DMA2 == 5)
255 dma_outb(pagenr, DMA_LO_PAGE_5);
257 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5);
258 dma_outb(pagenr >> 8, DMA_HI_PAGE_5);
261 if (SND_DMA1 == 6 || SND_DMA2 == 6)
262 dma_outb(pagenr, DMA_LO_PAGE_6);
264 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6);
265 dma_outb(pagenr >> 8, DMA_HI_PAGE_6);
268 if (SND_DMA1 == 7 || SND_DMA2 == 7)
269 dma_outb(pagenr, DMA_LO_PAGE_7);
271 dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7);
272 dma_outb(pagenr >> 8, DMA_HI_PAGE_7);
277 /* Set transfer address & page bits for specific DMA channel.
278 * Assumes dma flipflop is clear.
280 static __inline__ void
281 set_dma_addr(unsigned int dmanr, unsigned int phys)
284 dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
285 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE);
286 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
287 dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
288 dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
289 dma_outb((dmanr & 3), DMA2_EXT_REG);
291 dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
292 dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE);
294 set_dma_page(dmanr, phys >> 16);
297 /* Set transfer size (max 64k for DMA1..3, 128k for DMA5..7) for
298 * a specific DMA channel.
299 * You must ensure the parameters are valid.
300 * NOTE: from a manual: "the number of transfers is one more
301 * than the initial word count"! This is taken into account.
302 * Assumes dma flip-flop is clear.
303 * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
305 static __inline__ void
306 set_dma_count(unsigned int dmanr, unsigned int count)
310 dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE);
311 dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 +
313 } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) {
314 dma_outb(count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE);
315 dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 +
318 dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 +
320 dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 +
325 /* Get DMA residue count. After a DMA transfer, this
326 * should return zero. Reading this while a DMA transfer is
327 * still in progress will return unpredictable results.
328 * If called before the channel has been used, it may return 1.
329 * Otherwise, it returns the number of _bytes_ left to transfer.
331 * Assumes DMA flip-flop is clear.
333 static __inline__ int
334 get_dma_residue(unsigned int dmanr)
336 unsigned int io_port = (dmanr <= 3) ?
337 ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE
338 : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE;
340 /* using short to get 16-bit wrap around */
341 unsigned short count;
343 count = 1 + dma_inb(io_port);
344 count += dma_inb(io_port) << 8;
346 return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2)
347 ? count : (count << 1);
351 /* These are in kernel/dma.c: */
353 /* reserve a DMA channel */
354 extern int request_dma(unsigned int dmanr, const char *device_id);
355 /* release it again */
356 extern void free_dma(unsigned int dmanr);
358 #endif /* __ASM_PPC_ISA_DMA_H__ */
359 #endif /* __KERNEL__ */