2 * BK Id: SCCS/s.processor.h 1.78 01/29/03 07:46:20 trini
5 #ifndef __ASM_PPC_PROCESSOR_H
6 #define __ASM_PPC_PROCESSOR_H
9 * The Book E definitions are hacked into here for 440 right
10 * now. This whole thing needs regorganized (maybe two files)
11 * so that it becomes readable. -Matt
15 * Default implementation of macro that returns current
16 * instruction pointer ("program counter").
18 #define current_text_addr() ({ __label__ _l; _l: &&_l;})
20 #include <linux/config.h>
21 #include <linux/stringify.h>
23 #include <asm/ptrace.h>
24 #include <asm/types.h>
25 #include <asm/mpc8xx.h>
27 /* Machine State Register (MSR) Fields */
29 #ifdef CONFIG_PPC64BRIDGE
30 #define MSR_SF (1<<63)
31 #define MSR_ISF (1<<61)
32 #endif /* CONFIG_PPC64BRIDGE */
33 #define MSR_VEC (1<<25) /* Enable AltiVec */
34 #define MSR_POW (1<<18) /* Enable Power Management */
35 #define MSR_WE (1<<18) /* Wait State Enable */
36 #define MSR_TGPR (1<<17) /* TLB Update registers in use */
37 #define MSR_CE (1<<17) /* Critical Interrupt Enable */
38 #define MSR_ILE (1<<16) /* Interrupt Little Endian */
39 #define MSR_EE (1<<15) /* External Interrupt Enable */
40 #define MSR_PR (1<<14) /* Problem State / Privilege Level */
41 #define MSR_FP (1<<13) /* Floating Point enable */
42 #define MSR_ME (1<<12) /* Machine Check Enable */
43 #define MSR_FE0 (1<<11) /* Floating Exception mode 0 */
44 #define MSR_SE (1<<10) /* Single Step */
45 #define MSR_DWE (1<<10) /* Debug Wait Enable (4xx) */
46 #define MSR_BE (1<<9) /* Branch Trace */
47 #define MSR_DE (1<<9) /* Debug Exception Enable */
48 #define MSR_FE1 (1<<8) /* Floating Exception mode 1 */
49 #define MSR_IP (1<<6) /* Exception prefix 0x000/0xFFF */
50 #define MSR_IR (1<<5) /* Instruction Relocate */
51 #define MSR_DR (1<<4) /* Data Relocate */
52 #define MSR_PE (1<<3) /* Protection Enable */
53 #define MSR_PX (1<<2) /* Protection Exclusive Mode */
54 #define MSR_RI (1<<1) /* Recoverable Exception */
55 #define MSR_LE (1<<0) /* Little Endian */
58 #define MSR_IS MSR_IR /* Instruction Space */
59 #define MSR_DS MSR_DR /* Data Space */
62 #ifdef CONFIG_APUS_FAST_EXCEPT
63 #define MSR_ MSR_ME|MSR_IP|MSR_RI
65 #define MSR_ MSR_ME|MSR_RI
67 #define MSR_KERNEL MSR_|MSR_IR|MSR_DR
68 #define MSR_USER MSR_KERNEL|MSR_PR|MSR_EE
70 /* Floating Point Status and Control Register (FPSCR) Fields */
72 #define FPSCR_FX 0x80000000 /* FPU exception summary */
73 #define FPSCR_FEX 0x40000000 /* FPU enabled exception summary */
74 #define FPSCR_VX 0x20000000 /* Invalid operation summary */
75 #define FPSCR_OX 0x10000000 /* Overflow exception summary */
76 #define FPSCR_UX 0x08000000 /* Underflow exception summary */
77 #define FPSCR_ZX 0x04000000 /* Zero-devide exception summary */
78 #define FPSCR_XX 0x02000000 /* Inexact exception summary */
79 #define FPSCR_VXSNAN 0x01000000 /* Invalid op for SNaN */
80 #define FPSCR_VXISI 0x00800000 /* Invalid op for Inv - Inv */
81 #define FPSCR_VXIDI 0x00400000 /* Invalid op for Inv / Inv */
82 #define FPSCR_VXZDZ 0x00200000 /* Invalid op for Zero / Zero */
83 #define FPSCR_VXIMZ 0x00100000 /* Invalid op for Inv * Zero */
84 #define FPSCR_VXVC 0x00080000 /* Invalid op for Compare */
85 #define FPSCR_FR 0x00040000 /* Fraction rounded */
86 #define FPSCR_FI 0x00020000 /* Fraction inexact */
87 #define FPSCR_FPRF 0x0001f000 /* FPU Result Flags */
88 #define FPSCR_FPCC 0x0000f000 /* FPU Condition Codes */
89 #define FPSCR_VXSOFT 0x00000400 /* Invalid op for software request */
90 #define FPSCR_VXSQRT 0x00000200 /* Invalid op for square root */
91 #define FPSCR_VXCVI 0x00000100 /* Invalid op for integer convert */
92 #define FPSCR_VE 0x00000080 /* Invalid op exception enable */
93 #define FPSCR_OE 0x00000040 /* IEEE overflow exception enable */
94 #define FPSCR_UE 0x00000020 /* IEEE underflow exception enable */
95 #define FPSCR_ZE 0x00000010 /* IEEE zero divide exception enable */
96 #define FPSCR_XE 0x00000008 /* FP inexact exception enable */
97 #define FPSCR_NI 0x00000004 /* FPU non IEEE-Mode */
98 #define FPSCR_RN 0x00000003 /* FPU rounding control */
100 /* Special Purpose Registers (SPRNs)*/
102 #define SPRN_CCR0 0x3B3 /* Core Configuration Register (4xx) */
103 #define SPRN_CDBCR 0x3D7 /* Cache Debug Control Register */
104 #define SPRN_CTR 0x009 /* Count Register */
105 #define SPRN_DABR 0x3F5 /* Data Address Breakpoint Register */
107 #define SPRN_DAC1 0x3F6 /* Data Address Compare 1 */
108 #define SPRN_DAC2 0x3F7 /* Data Address Compare 2 */
110 #define SPRN_DAC1 0x13C /* Book E Data Address Compare 1 */
111 #define SPRN_DAC2 0x13D /* Book E Data Address Compare 2 */
112 #endif /* CONFIG_BOOKE */
113 #define SPRN_DAR 0x013 /* Data Address Register */
114 #define SPRN_DBAT0L 0x219 /* Data BAT 0 Lower Register */
115 #define SPRN_DBAT0U 0x218 /* Data BAT 0 Upper Register */
116 #define SPRN_DBAT1L 0x21B /* Data BAT 1 Lower Register */
117 #define SPRN_DBAT1U 0x21A /* Data BAT 1 Upper Register */
118 #define SPRN_DBAT2L 0x21D /* Data BAT 2 Lower Register */
119 #define SPRN_DBAT2U 0x21C /* Data BAT 2 Upper Register */
120 #define SPRN_DBAT3L 0x21F /* Data BAT 3 Lower Register */
121 #define SPRN_DBAT3U 0x21E /* Data BAT 3 Upper Register */
122 #define SPRN_DBAT4L 0x239 /* Data BAT 4 Lower Register */
123 #define SPRN_DBAT4U 0x238 /* Data BAT 4 Upper Register */
124 #define SPRN_DBAT5L 0x23B /* Data BAT 5 Lower Register */
125 #define SPRN_DBAT5U 0x23A /* Data BAT 5 Upper Register */
126 #define SPRN_DBAT6L 0x23D /* Data BAT 6 Lower Register */
127 #define SPRN_DBAT6U 0x23C /* Data BAT 6 Upper Register */
128 #define SPRN_DBAT7L 0x23F /* Data BAT 7 Lower Register */
129 #define SPRN_DBAT7U 0x23E /* Data BAT 7 Upper Register */
131 #define SPRN_DBCR 0x3F2 /* Debug Control Regsiter */
132 #define DBCR_EDM 0x80000000
133 #define DBCR_IDM 0x40000000
134 #define DBCR_RST(x) (((x) & 0x3) << 28)
135 #define DBCR_RST_NONE 0
136 #define DBCR_RST_CORE 1
137 #define DBCR_RST_CHIP 2
138 #define DBCR_RST_SYSTEM 3
139 #define DBCR_IC 0x08000000 /* Instruction Completion Debug Evnt */
140 #define DBCR_BT 0x04000000 /* Branch Taken Debug Event */
141 #define DBCR_EDE 0x02000000 /* Exception Debug Event */
142 #define DBCR_TDE 0x01000000 /* TRAP Debug Event */
143 #define DBCR_FER 0x00F80000 /* First Events Remaining Mask */
144 #define DBCR_FT 0x00040000 /* Freeze Timers on Debug Event */
145 #define DBCR_IA1 0x00020000 /* Instr. Addr. Compare 1 Enable */
146 #define DBCR_IA2 0x00010000 /* Instr. Addr. Compare 2 Enable */
147 #define DBCR_D1R 0x00008000 /* Data Addr. Compare 1 Read Enable */
148 #define DBCR_D1W 0x00004000 /* Data Addr. Compare 1 Write Enable */
149 #define DBCR_D1S(x) (((x) & 0x3) << 12) /* Data Adrr. Compare 1 Size */
154 #define DBCR_D2R 0x00000800 /* Data Addr. Compare 2 Read Enable */
155 #define DBCR_D2W 0x00000400 /* Data Addr. Compare 2 Write Enable */
156 #define DBCR_D2S(x) (((x) & 0x3) << 8) /* Data Addr. Compare 2 Size */
157 #define DBCR_SBT 0x00000040 /* Second Branch Taken Debug Event */
158 #define DBCR_SED 0x00000020 /* Second Exception Debug Event */
159 #define DBCR_STD 0x00000010 /* Second Trap Debug Event */
160 #define DBCR_SIA 0x00000008 /* Second IAC Enable */
161 #define DBCR_SDA 0x00000004 /* Second DAC Enable */
162 #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */
163 #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */
165 #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */
167 #define SPRN_DBCR0 0x134 /* Book E Debug Control Register 0 */
168 #endif /* CONFIG_BOOKE */
169 #define DBCR0_EDM 0x80000000 /* External Debug Mode */
170 #define DBCR0_IDM 0x40000000 /* Internal Debug Mode */
171 #define DBCR0_RST 0x30000000 /* all the bits in the RST field */
172 #define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */
173 #define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */
174 #define DBCR0_RST_CORE 0x10000000 /* Core Reset */
175 #define DBCR0_RST_NONE 0x00000000 /* No Reset */
176 #define DBCR0_IC 0x08000000 /* Instruction Completion */
177 #define DBCR0_BT 0x04000000 /* Branch Taken */
178 #define DBCR0_EDE 0x02000000 /* Exception Debug Event */
179 #define DBCR0_TDE 0x01000000 /* TRAP Debug Event */
180 #define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */
181 #define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */
182 #define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */
183 #define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */
184 #define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */
185 #define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */
186 #define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */
187 #define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */
188 #define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */
189 #define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */
190 #define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */
192 #define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */
193 #define SPRN_DBSR 0x3F0 /* Debug Status Register */
194 #define DBSR_IC 0x80000000 /* Instruction Completion */
195 #define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */
197 #define SPRN_DBCR1 0x135 /* Book E Debug Control Register 1 */
198 #define SPRN_DBSR 0x130 /* Book E Debug Status Register */
199 #define DBSR_IC 0x08000000 /* Book E Instruction Completion */
200 #define DBSR_TIE 0x01000000 /* Book E Trap Instruction Event */
201 #endif /* CONFIG_BOOKE */
202 #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */
203 #define DCCR_NOCACHE 0 /* Noncacheable */
204 #define DCCR_CACHE 1 /* Cacheable */
205 #define SPRN_DCMP 0x3D1 /* Data TLB Compare Register */
206 #define SPRN_DCWR 0x3BA /* Data Cache Write-thru Register */
207 #define DCWR_COPY 0 /* Copy-back */
208 #define DCWR_WRITE 1 /* Write-through */
210 #define SPRN_DEAR 0x3D5 /* Data Error Address Register */
212 #define SPRN_DEAR 0x03D /* Book E Data Error Address Register */
213 #endif /* CONFIG_BOOKE */
214 #define SPRN_DEC 0x016 /* Decrement Register */
215 #define SPRN_DER 0x095 /* Debug Enable Regsiter */
216 #define DER_RSTE 0x40000000 /* Reset Interrupt */
217 #define DER_CHSTPE 0x20000000 /* Check Stop */
218 #define DER_MCIE 0x10000000 /* Machine Check Interrupt */
219 #define DER_EXTIE 0x02000000 /* External Interrupt */
220 #define DER_ALIE 0x01000000 /* Alignment Interrupt */
221 #define DER_PRIE 0x00800000 /* Program Interrupt */
222 #define DER_FPUVIE 0x00400000 /* FP Unavailable Interrupt */
223 #define DER_DECIE 0x00200000 /* Decrementer Interrupt */
224 #define DER_SYSIE 0x00040000 /* System Call Interrupt */
225 #define DER_TRE 0x00020000 /* Trace Interrupt */
226 #define DER_SEIE 0x00004000 /* FP SW Emulation Interrupt */
227 #define DER_ITLBMSE 0x00002000 /* Imp. Spec. Instruction TLB Miss */
228 #define DER_ITLBERE 0x00001000 /* Imp. Spec. Instruction TLB Error */
229 #define DER_DTLBMSE 0x00000800 /* Imp. Spec. Data TLB Miss */
230 #define DER_DTLBERE 0x00000400 /* Imp. Spec. Data TLB Error */
231 #define DER_LBRKE 0x00000008 /* Load/Store Breakpoint Interrupt */
232 #define DER_IBRKE 0x00000004 /* Instruction Breakpoint Interrupt */
233 #define DER_EBRKE 0x00000002 /* External Breakpoint Interrupt */
234 #define DER_DPIE 0x00000001 /* Dev. Port Nonmaskable Request */
235 #define SPRN_DMISS 0x3D0 /* Data TLB Miss Register */
236 #define SPRN_DSISR 0x012 /* Data Storage Interrupt Status Register */
237 #define SPRN_EAR 0x11A /* External Address Register */
239 #define SPRN_ESR 0x3D4 /* Exception Syndrome Register */
241 #define SPRN_ESR 0x03E /* Book E Exception Syndrome Register */
242 #endif /* CONFIG_BOOKE */
243 #define ESR_IMCP 0x80000000 /* Instr. Machine Check - Protection */
244 #define ESR_IMCN 0x40000000 /* Instr. Machine Check - Non-config */
245 #define ESR_IMCB 0x20000000 /* Instr. Machine Check - Bus error */
246 #define ESR_IMCT 0x10000000 /* Instr. Machine Check - Timeout */
247 #define ESR_PIL 0x08000000 /* Program Exception - Illegal */
248 #define ESR_PPR 0x04000000 /* Program Exception - Priveleged */
249 #define ESR_PTR 0x02000000 /* Program Exception - Trap */
250 #define ESR_DST 0x00800000 /* Storage Exception - Data miss */
251 #define ESR_DIZ 0x00400000 /* Storage Exception - Zone fault */
252 #define SPRN_EVPR 0x3D6 /* Exception Vector Prefix Register */
253 #define SPRN_HASH1 0x3D2 /* Primary Hash Address Register */
254 #define SPRN_HASH2 0x3D3 /* Secondary Hash Address Resgister */
255 #define SPRN_HID0 0x3F0 /* Hardware Implementation Register 0 */
256 #define HID0_EMCP (1<<31) /* Enable Machine Check pin */
257 #define HID0_EBA (1<<29) /* Enable Bus Address Parity */
258 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */
259 #define HID0_SBCLK (1<<27)
260 #define HID0_EICE (1<<26)
261 #define HID0_TBEN (1<<26) /* Timebase enable - 74xx and 82xx */
262 #define HID0_ECLK (1<<25)
263 #define HID0_PAR (1<<24)
264 #define HID0_STEN (1<<24) /* Software table search enable - 745x */
265 #define HID0_HIGH_BAT (1<<23) /* Enable high BATs - 7455 */
266 #define HID0_DOZE (1<<23)
267 #define HID0_NAP (1<<22)
268 #define HID0_SLEEP (1<<21)
269 #define HID0_DPM (1<<20)
270 #define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */
271 #define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */
272 #define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/
273 #define HID0_ICE (1<<15) /* Instruction Cache Enable */
274 #define HID0_DCE (1<<14) /* Data Cache Enable */
275 #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */
276 #define HID0_DLOCK (1<<12) /* Data Cache Lock */
277 #define HID0_ICFI (1<<11) /* Instr. Cache Flash Invalidate */
278 #define HID0_DCI (1<<10) /* Data Cache Invalidate */
279 #define HID0_SPD (1<<9) /* Speculative disable */
280 #define HID0_SGE (1<<7) /* Store Gathering Enable */
281 #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */
282 #define HID0_DFCA (1<<6) /* Data Cache Flush Assist */
283 #define HID0_LRSTK (1<<4) /* Link register stack - 745x */
284 #define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */
285 #define HID0_ABE (1<<3) /* Address Broadcast Enable */
286 #define HID0_FOLD (1<<3) /* Branch Folding enable - 745x */
287 #define HID0_BHTE (1<<2) /* Branch History Table Enable */
288 #define HID0_BTCD (1<<1) /* Branch target cache disable */
289 #define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */
290 #define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */
292 #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */
293 #define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */
294 #define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */
295 #define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */
296 #define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */
297 #define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */
298 #define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */
299 #define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */
300 #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */
302 #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */
303 #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */
305 #define SPRN_IAC1 0x138 /* Book E Instruction Address Compare 1 */
306 #define SPRN_IAC2 0x139 /* Book E Instruction Address Compare 2 */
307 #endif /* CONFIG_BOOKE */
308 #define SPRN_IBAT0L 0x211 /* Instruction BAT 0 Lower Register */
309 #define SPRN_IBAT0U 0x210 /* Instruction BAT 0 Upper Register */
310 #define SPRN_IBAT1L 0x213 /* Instruction BAT 1 Lower Register */
311 #define SPRN_IBAT1U 0x212 /* Instruction BAT 1 Upper Register */
312 #define SPRN_IBAT2L 0x215 /* Instruction BAT 2 Lower Register */
313 #define SPRN_IBAT2U 0x214 /* Instruction BAT 2 Upper Register */
314 #define SPRN_IBAT3L 0x217 /* Instruction BAT 3 Lower Register */
315 #define SPRN_IBAT3U 0x216 /* Instruction BAT 3 Upper Register */
316 #define SPRN_IBAT4L 0x231 /* Instruction BAT 4 Lower Register */
317 #define SPRN_IBAT4U 0x230 /* Instruction BAT 4 Upper Register */
318 #define SPRN_IBAT5L 0x233 /* Instruction BAT 5 Lower Register */
319 #define SPRN_IBAT5U 0x232 /* Instruction BAT 5 Upper Register */
320 #define SPRN_IBAT6L 0x235 /* Instruction BAT 6 Lower Register */
321 #define SPRN_IBAT6U 0x234 /* Instruction BAT 6 Upper Register */
322 #define SPRN_IBAT7L 0x237 /* Instruction BAT 7 Lower Register */
323 #define SPRN_IBAT7U 0x236 /* Instruction BAT 7 Upper Register */
324 #define SPRN_ICCR 0x3FB /* Instruction Cache Cacheability Register */
325 #define ICCR_NOCACHE 0 /* Noncacheable */
326 #define ICCR_CACHE 1 /* Cacheable */
327 #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */
328 #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */
329 #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */
330 #define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */
331 #define ICTRL_EICE 0x08000000 /* enable icache parity errs */
332 #define ICTRL_EDCE 0x04000000 /* enable dcache parity errs */
333 #define ICTRL_EICP 0x00000100 /* enable icache par. check */
334 #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */
335 #define SPRN_IMMR 0x27E /* Internal Memory Map Register */
336 #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */
337 #define L2CR_L2E 0x80000000 /* L2 enable */
338 #define L2CR_L2PE 0x40000000 /* L2 parity enable */
339 #define L2CR_L2SIZ_MASK 0x30000000 /* L2 size mask */
340 #define L2CR_L2SIZ_256KB 0x10000000 /* L2 size 256KB */
341 #define L2CR_L2SIZ_512KB 0x20000000 /* L2 size 512KB */
342 #define L2CR_L2SIZ_1MB 0x30000000 /* L2 size 1MB */
343 #define L2CR_L2CLK_MASK 0x0e000000 /* L2 clock mask */
344 #define L2CR_L2CLK_DISABLED 0x00000000 /* L2 clock disabled */
345 #define L2CR_L2CLK_DIV1 0x02000000 /* L2 clock / 1 */
346 #define L2CR_L2CLK_DIV1_5 0x04000000 /* L2 clock / 1.5 */
347 #define L2CR_L2CLK_DIV2 0x08000000 /* L2 clock / 2 */
348 #define L2CR_L2CLK_DIV2_5 0x0a000000 /* L2 clock / 2.5 */
349 #define L2CR_L2CLK_DIV3 0x0c000000 /* L2 clock / 3 */
350 #define L2CR_L2RAM_MASK 0x01800000 /* L2 RAM type mask */
351 #define L2CR_L2RAM_FLOW 0x00000000 /* L2 RAM flow through */
352 #define L2CR_L2RAM_PIPE 0x01000000 /* L2 RAM pipelined */
353 #define L2CR_L2RAM_PIPE_LW 0x01800000 /* L2 RAM pipelined latewr */
354 #define L2CR_L2DO 0x00400000 /* L2 data only */
355 #define L2CR_L2I 0x00200000 /* L2 global invalidate */
356 #define L2CR_L2CTL 0x00100000 /* L2 RAM control */
357 #define L2CR_L2WT 0x00080000 /* L2 write-through */
358 #define L2CR_L2TS 0x00040000 /* L2 test support */
359 #define L2CR_L2OH_MASK 0x00030000 /* L2 output hold mask */
360 #define L2CR_L2OH_0_5 0x00000000 /* L2 output hold 0.5 ns */
361 #define L2CR_L2OH_1_0 0x00010000 /* L2 output hold 1.0 ns */
362 #define L2CR_L2SL 0x00008000 /* L2 DLL slow */
363 #define L2CR_L2DF 0x00004000 /* L2 differential clock */
364 #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */
365 #define L2CR_L2IP 0x00000001 /* L2 GI in progress */
366 #define SPRN_L2CR2 0x3f8
367 #define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter (7450) */
368 #define L3CR_L3E 0x80000000 /* L3 enable */
369 #define L3CR_L3PE 0x40000000 /* L3 data parity enable */
370 #define L3CR_L3APE 0x20000000 /* L3 addr parity enable */
371 #define L3CR_L3SIZ 0x10000000 /* L3 size */
372 #define L3CR_L3CLKEN 0x08000000 /* L3 clock enable */
373 #define L3CR_L3RES 0x04000000 /* L3 special reserved bit */
374 #define L3CR_L3CLKDIV 0x03800000 /* L3 clock divisor */
375 #define L3CR_L3IO 0x00400000 /* L3 instruction only */
376 #define L3CR_L3SPO 0x00040000 /* L3 sample point override */
377 #define L3CR_L3CKSP 0x00030000 /* L3 clock sample point */
378 #define L3CR_L3PSP 0x0000e000 /* L3 P-clock sample point */
379 #define L3CR_L3REP 0x00001000 /* L3 replacement algorithm */
380 #define L3CR_L3HWF 0x00000800 /* L3 hardware flush */
381 #define L3CR_L3I 0x00000400 /* L3 global invalidate */
382 #define L3CR_L3RT 0x00000300 /* L3 SRAM type */
383 #define L3CR_L3NIRCA 0x00000080 /* L3 non-integer ratio clock adj. */
384 #define L3CR_L3DO 0x00000040 /* L3 data only mode */
385 #define L3CR_PMEN 0x00000004 /* L3 private memory enable */
386 #define L3CR_PMSIZ 0x00000001 /* L3 private memory size */
387 #define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */
388 #define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */
389 #define SPRN_LDSTCR 0x3f8 /* Load/Store control register */
390 #define SPRN_LDSTDB 0x3f4 /* */
391 #define SPRN_LR 0x008 /* Link Register */
392 #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */
393 #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */
394 #define SPRN_PBL1 0x3FC /* Protection Bound Lower 1 */
395 #define SPRN_PBL2 0x3FE /* Protection Bound Lower 2 */
396 #define SPRN_PBU1 0x3FD /* Protection Bound Upper 1 */
397 #define SPRN_PBU2 0x3FF /* Protection Bound Upper 2 */
399 #define SPRN_PID 0x3B1 /* Process ID */
400 #define SPRN_PIR 0x3FF /* Processor Identification Register */
402 #define SPRN_PID 0x030 /* Book E Process ID */
403 #define SPRN_PIR 0x11E /* Book E Processor Identification Register */
404 #endif /* CONFIG_BOOKE */
405 #define SPRN_PIT 0x3DB /* Programmable Interval Timer */
406 #define SPRN_EDEC SPRN_PIT/* Book E Decrementer */
407 #define SPRN_PMC1 0x3B9 /* Performance Counter Register 1 */
408 #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */
409 #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */
410 #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */
411 #define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */
412 #define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */
413 #define SPRN_PVR 0x11F /* Processor Version Register */
414 #define SPRN_RPA 0x3D6 /* Required Physical Address Register */
415 #define SPRN_SDA 0x3BF /* Sampled Data Address Register */
416 #define SPRN_SDR1 0x019 /* MMU Hash Base Register */
417 #define SPRN_SGR 0x3B9 /* Storage Guarded Register */
419 #define SGR_GUARDED 1
420 #define SPRN_SIA 0x3BB /* Sampled Instruction Address Register */
421 #define SPRN_SLER 0x3BB /* Little-endian real mode */
422 #define SPRN_SPRG0 0x110 /* Special Purpose Register General 0 */
423 #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */
424 #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */
425 #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */
426 #define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 (4xx) */
427 #define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 (4xx) */
428 #define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 (4xx) */
429 #define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 (4xx) */
430 #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */
431 #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */
432 #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */
433 #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */
434 #define SPRN_SU0R 0x3BC /* "User 0" real mode */
435 #define SPRN_TBHI 0x3DC /* Time Base High (4xx) */
436 #define SPRN_TBHU 0x3CC /* Time Base High User-mode (4xx) */
437 #define SPRN_TBLO 0x3DD /* Time Base Low (4xx) */
438 #define SPRN_TBLU 0x3CD /* Time Base Low User-mode (4xx) */
439 #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */
440 #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */
441 #define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */
442 #define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */
444 #define SPRN_TCR 0x3DA /* Timer Control Register */
446 #define SPRN_TCR 0x154 /* Book E Timer Control Register */
448 #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */
449 #define TCR_WP_MASK TCR_WP(3)
450 #define WP_2_17 0 /* 2^17 clocks */
451 #define WP_2_21 1 /* 2^21 clocks */
452 #define WP_2_25 2 /* 2^25 clocks */
453 #define WP_2_29 3 /* 2^29 clocks */
454 #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */
455 #define TCR_WRC_MASK TCR_WRC(3)
456 #define WRC_NONE 0 /* No reset will occur */
457 #define WRC_CORE 1 /* Core reset will occur */
458 #define WRC_CHIP 2 /* Chip reset will occur */
459 #define WRC_SYSTEM 3 /* System reset will occur */
460 #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */
461 #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */
462 #define TCR_DIE TCR_PIE /* DEC Interrupt Enable */
463 #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */
464 #define TCR_FP_MASK TCR_FP(3)
465 #define FP_2_9 0 /* 2^9 clocks */
466 #define FP_2_13 1 /* 2^13 clocks */
467 #define FP_2_17 2 /* 2^17 clocks */
468 #define FP_2_21 3 /* 2^21 clocks */
469 #define TCR_FIE 0x00800000 /* FIT Interrupt Enable */
470 #define TCR_ARE 0x00400000 /* Auto Reload Enable */
471 #define SPRN_THRM1 0x3FC /* Thermal Management Register 1 */
472 /* these bits were defined in inverted endian sense originally, ugh, confusing */
473 #define THRM1_TIN (1 << 31)
474 #define THRM1_TIV (1 << 30)
475 #define THRM1_THRES(x) ((x&0x7f)<<23)
476 #define THRM3_SITV(x) ((x&0x3fff)<<1)
477 #define THRM1_TID (1<<2)
478 #define THRM1_TIE (1<<1)
479 #define THRM1_V (1<<0)
480 #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */
481 #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */
482 #define THRM3_E (1<<0)
483 #define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */
485 #define SPRN_TSR 0x3D8 /* Timer Status Register */
487 #define SPRN_TSR 0x150 /* Book E Timer Status Register */
488 #endif /* CONFIG_BOOKE */
489 #define TSR_ENW 0x80000000 /* Enable Next Watchdog */
490 #define TSR_WIS 0x40000000 /* WDT Interrupt Status */
491 #define TSR_WRS(x) (((x)&0x3)<<28) /* WDT Reset Status */
492 #define WRS_NONE 0 /* No WDT reset occurred */
493 #define WRS_CORE 1 /* WDT forced core reset */
494 #define WRS_CHIP 2 /* WDT forced chip reset */
495 #define WRS_SYSTEM 3 /* WDT forced system reset */
496 #define TSR_PIS 0x08000000 /* PIT Interrupt Status */
497 #define TSR_DIS TSR_PIS /* DEC Interrupt Status */
498 #define TSR_FIS 0x04000000 /* FIT Interrupt Status */
499 #define SPRN_UMMCR0 0x3A8 /* User Monitor Mode Control Register 0 */
500 #define SPRN_UMMCR1 0x3AC /* User Monitor Mode Control Register 0 */
501 #define SPRN_UPMC1 0x3A9 /* User Performance Counter Register 1 */
502 #define SPRN_UPMC2 0x3AA /* User Performance Counter Register 2 */
503 #define SPRN_UPMC3 0x3AD /* User Performance Counter Register 3 */
504 #define SPRN_UPMC4 0x3AE /* User Performance Counter Register 4 */
505 #define SPRN_USIA 0x3AB /* User Sampled Instruction Address Register */
506 #define SPRN_VRSAVE 0x100 /* Vector Register Save Register */
507 #define SPRN_XER 0x001 /* Fixed Point Exception Register */
508 #define SPRN_ZPR 0x3B0 /* Zone Protection Register */
510 /* Book E definitions */
511 #define SPRN_DECAR 0x036 /* Decrementer Auto Reload Register */
512 #define SPRN_CSRR0 0x03A /* Critical SRR0 */
513 #define SPRN_CSRR1 0x03B /* Critical SRR0 */
514 #define SPRN_IVPR 0x03F /* Interrupt Vector Prefix Register */
515 #define SPRN_USPRG0 0x100 /* User Special Purpose Register General 0 */
516 #define SPRN_SPRG4R 0x104 /* Special Purpose Register General 4 Read */
517 #define SPRN_SPRG5R 0x105 /* Special Purpose Register General 5 Read */
518 #define SPRN_SPRG6R 0x106 /* Special Purpose Register General 6 Read */
519 #define SPRN_SPRG7R 0x107 /* Special Purpose Register General 7 Read */
520 #define SPRN_SPRG4W 0x114 /* Special Purpose Register General 4 Write */
521 #define SPRN_SPRG5W 0x115 /* Special Purpose Register General 5 Write */
522 #define SPRN_SPRG6W 0x116 /* Special Purpose Register General 6 Write */
523 #define SPRN_SPRG7W 0x117 /* Special Purpose Register General 7 Write */
524 #define SPRN_DBCR2 0x136 /* Debug Control Register 2 */
525 #define SPRN_IAC3 0x13A /* Instruction Address Compare 3 */
526 #define SPRN_IAC4 0x13B /* Instruction Address Compare 4 */
527 #define SPRN_DVC1 0x13E /* */
528 #define SPRN_DVC2 0x13F /* */
529 #define SPRN_IVOR0 0x190 /* Interrupt Vector Offset Register 0 */
530 #define SPRN_IVOR1 0x191 /* Interrupt Vector Offset Register 1 */
531 #define SPRN_IVOR2 0x192 /* Interrupt Vector Offset Register 2 */
532 #define SPRN_IVOR3 0x193 /* Interrupt Vector Offset Register 3 */
533 #define SPRN_IVOR4 0x194 /* Interrupt Vector Offset Register 4 */
534 #define SPRN_IVOR5 0x195 /* Interrupt Vector Offset Register 5 */
535 #define SPRN_IVOR6 0x196 /* Interrupt Vector Offset Register 6 */
536 #define SPRN_IVOR7 0x197 /* Interrupt Vector Offset Register 7 */
537 #define SPRN_IVOR8 0x198 /* Interrupt Vector Offset Register 8 */
538 #define SPRN_IVOR9 0x199 /* Interrupt Vector Offset Register 9 */
539 #define SPRN_IVOR10 0x19a /* Interrupt Vector Offset Register 10 */
540 #define SPRN_IVOR11 0x19b /* Interrupt Vector Offset Register 11 */
541 #define SPRN_IVOR12 0x19c /* Interrupt Vector Offset Register 12 */
542 #define SPRN_IVOR13 0x19d /* Interrupt Vector Offset Register 13 */
543 #define SPRN_IVOR14 0x19e /* Interrupt Vector Offset Register 14 */
544 #define SPRN_IVOR15 0x19f /* Interrupt Vector Offset Register 15 */
545 #define SPRN_MMUCR 0x3b2 /* MMU Control Register */
547 #define ESR_ST 0x00800000 /* Store Operation */
549 /* Short-hand versions for a number of the above SPRNs */
551 #define CTR SPRN_CTR /* Counter Register */
552 #define DAR SPRN_DAR /* Data Address Register */
553 #define DABR SPRN_DABR /* Data Address Breakpoint Register */
554 #define DBAT0L SPRN_DBAT0L /* Data BAT 0 Lower Register */
555 #define DBAT0U SPRN_DBAT0U /* Data BAT 0 Upper Register */
556 #define DBAT1L SPRN_DBAT1L /* Data BAT 1 Lower Register */
557 #define DBAT1U SPRN_DBAT1U /* Data BAT 1 Upper Register */
558 #define DBAT2L SPRN_DBAT2L /* Data BAT 2 Lower Register */
559 #define DBAT2U SPRN_DBAT2U /* Data BAT 2 Upper Register */
560 #define DBAT3L SPRN_DBAT3L /* Data BAT 3 Lower Register */
561 #define DBAT3U SPRN_DBAT3U /* Data BAT 3 Upper Register */
562 #define DBAT4L SPRN_DBAT4L /* Data BAT 4 Lower Register */
563 #define DBAT4U SPRN_DBAT4U /* Data BAT 4 Upper Register */
564 #define DBAT5L SPRN_DBAT5L /* Data BAT 5 Lower Register */
565 #define DBAT5U SPRN_DBAT5U /* Data BAT 5 Upper Register */
566 #define DBAT6L SPRN_DBAT6L /* Data BAT 6 Lower Register */
567 #define DBAT6U SPRN_DBAT6U /* Data BAT 6 Upper Register */
568 #define DBAT7L SPRN_DBAT7L /* Data BAT 7 Lower Register */
569 #define DBAT7U SPRN_DBAT7U /* Data BAT 7 Upper Register */
570 #define DCMP SPRN_DCMP /* Data TLB Compare Register */
571 #define DEC SPRN_DEC /* Decrement Register */
572 #define DECAR SPRN_DECAR /* Decrementer Auto Reload Register */
573 #define DMISS SPRN_DMISS /* Data TLB Miss Register */
574 #define DSISR SPRN_DSISR /* Data Storage Interrupt Status Register */
575 #define EAR SPRN_EAR /* External Address Register */
576 #define HASH1 SPRN_HASH1 /* Primary Hash Address Register */
577 #define HASH2 SPRN_HASH2 /* Secondary Hash Address Register */
578 #define HID0 SPRN_HID0 /* Hardware Implementation Register 0 */
579 #define HID1 SPRN_HID1 /* Hardware Implementation Register 1 */
580 #define IABR SPRN_IABR /* Instruction Address Breakpoint Register */
581 #define IBAT0L SPRN_IBAT0L /* Instruction BAT 0 Lower Register */
582 #define IBAT0U SPRN_IBAT0U /* Instruction BAT 0 Upper Register */
583 #define IBAT1L SPRN_IBAT1L /* Instruction BAT 1 Lower Register */
584 #define IBAT1U SPRN_IBAT1U /* Instruction BAT 1 Upper Register */
585 #define IBAT2L SPRN_IBAT2L /* Instruction BAT 2 Lower Register */
586 #define IBAT2U SPRN_IBAT2U /* Instruction BAT 2 Upper Register */
587 #define IBAT3L SPRN_IBAT3L /* Instruction BAT 3 Lower Register */
588 #define IBAT3U SPRN_IBAT3U /* Instruction BAT 3 Upper Register */
589 #define IBAT4L SPRN_IBAT4L /* Instruction BAT 4 Lower Register */
590 #define IBAT4U SPRN_IBAT4U /* Instruction BAT 4 Upper Register */
591 #define IBAT5L SPRN_IBAT5L /* Instruction BAT 5 Lower Register */
592 #define IBAT5U SPRN_IBAT5U /* Instruction BAT 5 Upper Register */
593 #define IBAT6L SPRN_IBAT6L /* Instruction BAT 6 Lower Register */
594 #define IBAT6U SPRN_IBAT6U /* Instruction BAT 6 Upper Register */
595 #define IBAT7L SPRN_IBAT7L /* Instruction BAT 7 Lower Register */
596 #define IBAT7U SPRN_IBAT7U /* Instruction BAT 7 Upper Register */
597 #define ICMP SPRN_ICMP /* Instruction TLB Compare Register */
598 #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */
599 #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */
600 #define L2CR SPRN_L2CR /* PPC 750 L2 control register */
601 #define L3CR SPRN_L3CR /* PPC 7450 L3 Cache control register */
603 #define PVR SPRN_PVR /* Processor Version */
604 #define RPA SPRN_RPA /* Required Physical Address Register */
605 #define SDR1 SPRN_SDR1 /* MMU hash base register */
606 #define USPRG0 SPRN_USPRG0
607 #define SPR0 SPRN_SPRG0 /* Supervisor Private Registers */
608 #define SPR1 SPRN_SPRG1
609 #define SPR2 SPRN_SPRG2
610 #define SPR3 SPRN_SPRG3
611 #define SPR4 SPRN_SPRG4 /* Supervisor Private Registers (4xx) */
612 #define SPR5 SPRN_SPRG5
613 #define SPR6 SPRN_SPRG6
614 #define SPR7 SPRN_SPRG7
615 #define SPRG0 SPRN_SPRG0
616 #define SPRG1 SPRN_SPRG1
617 #define SPRG2 SPRN_SPRG2
618 #define SPRG3 SPRN_SPRG3
619 #define SPRG4 SPRN_SPRG4
620 #define SPRG5 SPRN_SPRG5
621 #define SPRG6 SPRN_SPRG6
622 #define SPRG7 SPRN_SPRG7
623 #define SPRG4R SPRN_SPRG4R /* Book E Supervisor Private Registers */
624 #define SPRG5R SPRN_SPRG5R
625 #define SPRG6R SPRN_SPRG6R
626 #define SPRG7R SPRN_SPRG7R
627 #define SPRG4W SPRN_SPRG4W
628 #define SPRG5W SPRN_SPRG5W
629 #define SPRG6W SPRN_SPRG6W
630 #define SPRG7W SPRN_SPRG7W
631 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */
632 #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */
633 #define TBRL SPRN_TBRL /* Time Base Read Lower Register */
634 #define TBRU SPRN_TBRU /* Time Base Read Upper Register */
635 #define TBWL SPRN_TBWL /* Time Base Write Lower Register */
636 #define TBWU SPRN_TBWU /* Time Base Write Upper Register */
638 #define THRM1 SPRN_THRM1 /* Thermal Management Register 1 */
639 #define THRM2 SPRN_THRM2 /* Thermal Management Register 2 */
640 #define THRM3 SPRN_THRM3 /* Thermal Management Register 3 */
643 /* Processor Version Register */
645 /* Processor Version Register (PVR) field extraction */
647 #define PVR_VER(pvr) (((pvr) >> 16) & 0xFFFF) /* Version field */
648 #define PVR_REV(pvr) (((pvr) >> 0) & 0xFFFF) /* Revison field */
651 * IBM has further subdivided the standard PowerPC 16-bit version and
652 * revision subfields of the PVR for the PowerPC 403s into the following:
655 #define PVR_FAM(pvr) (((pvr) >> 20) & 0xFFF) /* Family field */
656 #define PVR_MEM(pvr) (((pvr) >> 16) & 0xF) /* Member field */
657 #define PVR_CORE(pvr) (((pvr) >> 12) & 0xF) /* Core field */
658 #define PVR_CFG(pvr) (((pvr) >> 8) & 0xF) /* Configuration field */
659 #define PVR_MAJ(pvr) (((pvr) >> 4) & 0xF) /* Major revision field */
660 #define PVR_MIN(pvr) (((pvr) >> 0) & 0xF) /* Minor revision field */
662 /* Processor Version Numbers */
664 #define PVR_403GA 0x00200000
665 #define PVR_403GB 0x00200100
666 #define PVR_403GC 0x00200200
667 #define PVR_403GCX 0x00201400
668 #define PVR_405GP 0x40110000
669 #define PVR_STB03XXX 0x40310000
670 #define PVR_NP405H 0x41410000
671 #define PVR_NP405L 0x41610000
672 #define PVR_440GP_RB 0x40120440
673 #define PVR_440GP_RC1 0x40120481
674 #define PVR_440GP_RC2 0x40200481
675 #define PVR_601 0x00010000
676 #define PVR_602 0x00050000
677 #define PVR_603 0x00030000
678 #define PVR_603e 0x00060000
679 #define PVR_603ev 0x00070000
680 #define PVR_603r 0x00071000
681 #define PVR_604 0x00040000
682 #define PVR_604e 0x00090000
683 #define PVR_604r 0x000A0000
684 #define PVR_620 0x00140000
685 #define PVR_740 0x00080000
686 #define PVR_750 PVR_740
687 #define PVR_740P 0x10080000
688 #define PVR_750P PVR_740P
689 #define PVR_7400 0x000C0000
690 #define PVR_7410 0x800C0000
691 #define PVR_7450 0x80000000
693 * For the 8xx processors, all of them report the same PVR family for
694 * the PowerPC core. The various versions of these processors must be
695 * differentiated by the version number in the Communication Processor
698 #define PVR_821 0x00500000
699 #define PVR_823 PVR_821
700 #define PVR_850 PVR_821
701 #define PVR_860 PVR_821
702 #define PVR_8240 0x00810100
703 #define PVR_8245 0x80811014
704 #define PVR_8260 PVR_8240
706 /* We only need to define a new _MACH_xxx for machines which are part of
707 * a configuration which supports more than one type of different machine.
708 * This is currently limited to CONFIG_ALL_PPC and CHRP/PReP/PMac. -- Tom
710 #define _MACH_prep 0x00000001
711 #define _MACH_Pmac 0x00000002 /* pmac or pmac clone (non-chrp) */
712 #define _MACH_chrp 0x00000004 /* chrp machine */
714 /* see residual.h for these */
715 #define _PREP_Motorola 0x01 /* motorola prep */
716 #define _PREP_Firm 0x02 /* firmworks prep */
717 #define _PREP_IBM 0x00 /* ibm prep */
718 #define _PREP_Bull 0x03 /* bull prep */
720 /* these are arbitrary */
721 #define _CHRP_Motorola 0x04 /* motorola chrp, the cobra */
722 #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */
725 .stabs __stringify(n:F-1),N_FUN,0,0,n;\
729 /* Macros for setting and retrieving special purpose registers */
731 #define mfmsr() ({unsigned int rval; \
732 asm volatile("mfmsr %0" : "=r" (rval)); rval;})
733 #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v))
735 #define mfspr(rn) ({unsigned int rval; \
736 asm volatile("mfspr %0," __stringify(rn) \
737 : "=r" (rval)); rval;})
738 #define mtspr(rn, v) asm volatile("mtspr " __stringify(rn) ",%0" : : "r" (v))
740 #define mfsrin(v) ({unsigned int rval; \
741 asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \
744 #define proc_trap() asm volatile("trap")
746 #ifdef CONFIG_PPC_ISERIES
747 /* Macros for adjusting thread priority (hardware multi-threading) */
748 #define HMT_PRIO_LOW "or 1,1,1\n" /* low prio, used for spin loops */
749 #define HMT_PRIO_MED "or 2,2,2\n" /* medium prio, for normal code */
750 #define HMT_PRIO_HIGH "or 3,3,3\n" /* high priority */
752 #define HMT_low() asm volatile("or 1,1,1")
753 #define HMT_medium() asm volatile("or 2,2,2")
754 #define HMT_high() asm volatile("or 3,3,3")
756 /* iSeries CTRL register (for runlatch) */
760 #define RUNLATCH 0x0001
762 #else /* !CONFIG_PPC_ISERIES */
765 #define HMT_PRIO_HIGH
767 #endif /* CONFIG_PPC_ISERIES */
769 /* Segment Registers */
789 #if defined(CONFIG_ALL_PPC)
792 /* what kind of prep workstation we are */
793 extern int _prep_type;
796 * This is used to identify the board type from a given PReP board
797 * vendor. Board revision is also made available.
799 extern unsigned char ucSystemType;
800 extern unsigned char ucBoardRev;
801 extern unsigned char ucBoardRevMaj, ucBoardRevMin;
804 #endif /* CONFIG_ALL_PPC */
807 void start_thread(struct pt_regs *regs, unsigned long nip, unsigned long sp);
808 void release_thread(struct task_struct *);
811 * Create a new kernel thread.
813 extern long kernel_thread(int (*fn)(void *), void *arg, unsigned long flags);
819 #define EISA_bus__is_a_macro /* for versions in ksyms.c */
821 #define MCA_bus__is_a_macro /* for versions in ksyms.c */
823 /* Lazy FPU handling on uni-processor */
824 extern struct task_struct *last_task_used_math;
825 extern struct task_struct *last_task_used_altivec;
828 * this is the minimum allowable io space due to the location
829 * of the io areas on prep (first one at 0x80000000) but
830 * as soon as I get around to remapping the io areas with the BATs
831 * to match the mac we can raise this. -- Cort
833 #ifdef CONFIG_TASK_SIZE_BOOL
834 #define TASK_SIZE CONFIG_TASK_SIZE
836 #define TASK_SIZE (0x80000000UL)
839 /* This decides where the kernel will search for a free chunk of vm
840 * space during mmap's.
842 #define TASK_UNMAPPED_BASE (TASK_SIZE / 8 * 3)
848 struct thread_struct {
849 unsigned long ksp; /* Kernel stack pointer */
850 struct pt_regs *regs; /* Pointer to saved register state */
851 mm_segment_t fs; /* for get_fs() validation */
852 void *pgdir; /* root of page-table tree */
853 int fpexc_mode; /* floating-point exception mode */
854 signed long last_syscall;
855 double fpr[32]; /* Complete floating point set */
856 unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */
857 unsigned long fpscr; /* Floating point status */
858 #ifdef CONFIG_ALTIVEC
859 vector128 vr[32]; /* Complete AltiVec set */
860 vector128 vscr; /* AltiVec status */
861 unsigned long vrsave;
862 #endif /* CONFIG_ALTIVEC */
863 #if defined(CONFIG_4xx) || defined (CONFIG_BOOKE)
864 /* Saved 4xx debug registers */
869 #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack)
871 #define INIT_THREAD { \
874 .pgdir = swapper_pg_dir, \
875 .fpexc_mode = MSR_FE0 | MSR_FE1, \
879 * Return saved PC of a blocked thread. For now, this is the "user" PC
881 static inline unsigned long thread_saved_pc(struct thread_struct *t)
883 return (t->regs) ? t->regs->nip : 0;
886 #define copy_segments(tsk, mm) do { } while (0)
887 #define release_segments(mm) do { } while (0)
889 unsigned long get_wchan(struct task_struct *p);
891 #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0)
892 #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0)
894 /* Get/set floating-point exception mode */
895 #define GET_FPEXC_CTL(tsk, adr) get_fpexc_mode((tsk), (adr))
896 #define SET_FPEXC_CTL(tsk, val) set_fpexc_mode((tsk), (val))
898 extern int get_fpexc_mode(struct task_struct *tsk, unsigned long adr);
899 extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val);
902 * NOTE! The task struct and the stack go together
904 #define THREAD_SIZE (2*PAGE_SIZE)
906 #define alloc_task_struct() \
907 ((struct task_struct *) __get_free_pages(GFP_KERNEL,1))
909 #define alloc_task_struct() \
910 ((struct task_struct *) __get_free_pages(GFP_DMA,1))
911 #endif /* CONFIG_440 */
912 #define free_task_struct(p) free_pages((unsigned long)(p),1)
913 #define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count)
915 /* in process.c - for early bootup debug -- Cort */
916 int ll_printk(const char *, ...);
917 void ll_puts(const char *);
919 #define init_task (init_task_union.task)
920 #define init_stack (init_task_union.stack)
923 void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val);
925 #define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac)
927 #define cpu_relax() do { } while (0)
932 #define ARCH_HAS_PREFETCH
933 #define ARCH_HAS_PREFETCHW
934 #define ARCH_HAS_SPINLOCK_PREFETCH
936 extern inline void prefetch(const void *x)
938 __asm__ __volatile__ ("dcbt 0,%0" : : "r" (x));
941 extern inline void prefetchw(const void *x)
943 __asm__ __volatile__ ("dcbtst 0,%0" : : "r" (x));
946 #define spin_lock_prefetch(x) prefetchw(x)
948 #endif /* !__ASSEMBLY__ */
950 #endif /* __ASM_PPC_PROCESSOR_H */
951 #endif /* __KERNEL__ */