include/asm-s390/lowcore.h

   1 /*
   2  *  include/asm-s390/lowcore.h
   3  *
   4  *  S390 version
   5  *    Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
   6  *    Author(s): Hartmut Penner (hp@de.ibm.com),
   7  *               Martin Schwidefsky (schwidefsky@de.ibm.com),
   8  *               Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
   9  */
  10
  11 #ifndef _ASM_S390_LOWCORE_H
  12 #define _ASM_S390_LOWCORE_H
  13
  14 #define __LC_EXT_OLD_PSW                0x018
  15 #define __LC_SVC_OLD_PSW                0x020
  16 #define __LC_PGM_OLD_PSW                0x028
  17 #define __LC_MCK_OLD_PSW                0x030
  18 #define __LC_IO_OLD_PSW                 0x038
  19 #define __LC_EXT_NEW_PSW                0x058
  20 #define __LC_SVC_NEW_PSW                0x060
  21 #define __LC_PGM_NEW_PSW                0x068
  22 #define __LC_MCK_NEW_PSW                0x070
  23 #define __LC_IO_NEW_PSW                 0x078
  24 #define __LC_EXT_PARAMS                 0x080
  25 #define __LC_CPU_ADDRESS                0x084
  26 #define __LC_EXT_INT_CODE               0x086
  27 #define __LC_SVC_INT_CODE               0x08B
  28 #define __LC_PGM_ILC                    0x08C
  29 #define __LC_PGM_INT_CODE               0x08E
  30 #define __LC_TRANS_EXC_ADDR             0x090
  31 #define __LC_SUBCHANNEL_ID              0x0B8
  32 #define __LC_SUBCHANNEL_NR              0x0BA
  33 #define __LC_IO_INT_PARM                0x0BC
  34 #define __LC_IO_INT_WORD                0x0C0
  35 #define __LC_MCCK_CODE                  0x0E8
  36 #define __LC_AREGS_SAVE_AREA            0x120
  37 #define __LC_CREGS_SAVE_AREA            0x1C0
  38 #define __LC_RETURN_PSW                 0x200
  39
  40 #define __LC_SYNC_IO_WORD               0x400
  41
  42 #define __LC_SAVE_AREA                  0xC00
  43 #define __LC_KERNEL_STACK               0xC40
  44 #define __LC_ASYNC_STACK                0xC44
  45 #define __LC_CPUID                      0xC60
  46 #define __LC_CPUADDR                    0xC68
  47 #define __LC_IPLDEV                     0xC7C
  48
  49 #define __LC_JIFFY_TIMER                0xC80
  50 #define __LC_INT_CLOCK                  0xC88
  51
  52 #define __LC_PANIC_MAGIC                0xE00
  53
  54 #define __LC_PFAULT_INTPARM             0x080
  55
  56 /* interrupt handler start with all io, external and mcck interrupt disabled */
  57
  58 #define _RESTART_PSW_MASK    0x00080000
  59 #define _EXT_PSW_MASK        0x04080000
  60 #define _PGM_PSW_MASK        0x04080000
  61 #define _SVC_PSW_MASK        0x04080000
  62 #define _MCCK_PSW_MASK       0x04080000
  63 #define _IO_PSW_MASK         0x04080000
  64 #define _USER_PSW_MASK       0x070DC000/* DAT, IO, EXT, Home-space         */
  65 #define _WAIT_PSW_MASK       0x070E0000/* DAT, IO, EXT, Wait, Home-space   */
  66 #define _DW_PSW_MASK         0x000A0000/* disabled wait PSW mask           */
  67
  68 #define _PRIMARY_MASK        0x0000    /* MASK for SACF                    */
  69 #define _SECONDARY_MASK      0x0100    /* MASK for SACF                    */
  70 #define _ACCESS_MASK         0x0200    /* MASK for SACF                    */
  71 #define _HOME_MASK           0x0300    /* MASK for SACF                    */
  72
  73 #define _PSW_PRIM_SPACE_MODE 0x00000000
  74 #define _PSW_SEC_SPACE_MODE  0x00008000
  75 #define _PSW_ACC_REG_MODE    0x00004000
  76 #define _PSW_HOME_SPACE_MODE 0x0000C000
  77
  78 #define _PSW_WAIT_MASK_BIT   0x00020000 /* Wait bit */
  79 #define _PSW_IO_MASK_BIT     0x02000000 /* IO bit */
  80 #define _PSW_IO_WAIT         0x02020000 /* IO & Wait bit */
  81
  82 /* we run in 31 Bit mode */
  83 #define _ADDR_31             0x80000000
  84
  85 #ifndef __ASSEMBLY__
  86
  87 #include <linux/config.h>
  88 #include <asm/processor.h>
  89 #include <linux/types.h>
  90 #include <asm/atomic.h>
  91 #include <asm/sigp.h>
  92
  93 void restart_int_handler(void);
  94 void ext_int_handler(void);
  95 void system_call(void);
  96 void pgm_check_handler(void);
  97 void mcck_int_handler(void);
  98 void io_int_handler(void);
  99
 100 struct _lowcore
 101 {
 102         /* prefix area: defined by architecture */
 103         psw_t        restart_psw;              /* 0x000 */
 104         __u32        ccw2[4];                  /* 0x008 */
 105         psw_t        external_old_psw;         /* 0x018 */
 106         psw_t        svc_old_psw;              /* 0x020 */
 107         psw_t        program_old_psw;          /* 0x028 */
 108         psw_t        mcck_old_psw;             /* 0x030 */
 109         psw_t        io_old_psw;               /* 0x038 */
 110         __u8         pad1[0x58-0x40];          /* 0x040 */
 111         psw_t        external_new_psw;         /* 0x058 */
 112         psw_t        svc_new_psw;              /* 0x060 */
 113         psw_t        program_new_psw;          /* 0x068 */
 114         psw_t        mcck_new_psw;             /* 0x070 */
 115         psw_t        io_new_psw;               /* 0x078 */
 116         __u32        ext_params;               /* 0x080 */
 117         __u16        cpu_addr;                 /* 0x084 */
 118         __u16        ext_int_code;             /* 0x086 */
 119         __u16        svc_ilc;                  /* 0x088 */
 120         __u16        svc_code;                 /* 0x08a */
 121         __u16        pgm_ilc;                  /* 0x08c */
 122         __u16        pgm_code;                 /* 0x08e */
 123         __u32        trans_exc_code;           /* 0x090 */
 124         __u16        mon_class_num;            /* 0x094 */
 125         __u16        per_perc_atmid;           /* 0x096 */
 126         __u32        per_address;              /* 0x098 */
 127         __u32        monitor_code;             /* 0x09c */
 128         __u8         exc_access_id;            /* 0x0a0 */
 129         __u8         per_access_id;            /* 0x0a1 */
 130         __u8         pad2[0xB8-0xA2];          /* 0x0a2 */
 131         __u16        subchannel_id;            /* 0x0b8 */
 132         __u16        subchannel_nr;            /* 0x0ba */
 133         __u32        io_int_parm;              /* 0x0bc */
 134         __u32        io_int_word;              /* 0x0c0 */
 135         __u8         pad3[0xD8-0xC4];          /* 0x0c4 */
 136         __u32        cpu_timer_save_area[2];   /* 0x0d8 */
 137         __u32        clock_comp_save_area[2];  /* 0x0e0 */
 138         __u32        mcck_interruption_code[2]; /* 0x0e8 */
 139         __u8         pad4[0xf4-0xf0];          /* 0x0f0 */
 140         __u32        external_damage_code;     /* 0x0f4 */
 141         __u32        failing_storage_address;  /* 0x0f8 */
 142         __u8         pad5[0x100-0xfc];         /* 0x0fc */
 143         __u32        st_status_fixed_logout[4];/* 0x100 */
 144         __u8         pad6[0x120-0x110];        /* 0x110 */
 145         __u32        access_regs_save_area[16];/* 0x120 */
 146         __u32        floating_pt_save_area[8]; /* 0x160 */
 147         __u32        gpregs_save_area[16];     /* 0x180 */
 148         __u32        cregs_save_area[16];      /* 0x240 */
 149
 150         psw_t        return_psw;               /* 0x200 */
 151         __u8         pad8[0x400-0x208];        /* 0x208 */
 152
 153         __u32        sync_io_word;             /* 0x400 */
 154
 155         __u8         pad9[0xc00-0x404];        /* 0x404 */
 156
 157         /* System info area */
 158         __u32        save_area[16];            /* 0xc00 */
 159         __u32        kernel_stack;             /* 0xc40 */
 160         __u32        async_stack;              /* 0xc44 */
 161         /* entry.S sensitive area start */
 162         __u8         pad10[0xc60-0xc48];       /* 0xc5c */
 163         struct       cpuinfo_S390 cpu_data;    /* 0xc60 */
 164         __u32        ipl_device;               /* 0xc7c */
 165         /* entry.S sensitive area end */
 166
 167         /* SMP info area: defined by DJB */
 168         __u64        jiffy_timer;              /* 0xc80 */
 169         __u64        int_clock;                /* 0xc88 */
 170         atomic_t     ext_call_fast;            /* 0xc90 */
 171         __u8         pad11[0xe00-0xc94];       /* 0xc94 */
 172
 173         /* 0xe00 is used as indicator for dump tools */
 174         /* whether the kernel died with panic() or not */
 175         __u32        panic_magic;              /* 0xe00 */
 176
 177         /* Align to the top 1k of prefix area */
 178         __u8         pad12[0x1000-0xe04];      /* 0xe04 */
 179 } __attribute__((packed)); /* End structure*/
 180
 181 extern __inline__ void set_prefix(__u32 address)
 182 {
 183         __asm__ __volatile__ ("spx %0" : : "m" (address) : "memory" );
 184 }
 185
 186 #define S390_lowcore (*((struct _lowcore *) 0))
 187 extern struct _lowcore *lowcore_ptr[];
 188
 189 #ifndef CONFIG_SMP
 190 #define get_cpu_lowcore(cpu)      (&S390_lowcore)
 191 #define safe_get_cpu_lowcore(cpu) (&S390_lowcore)
 192 #else
 193 #define get_cpu_lowcore(cpu)      (lowcore_ptr[(cpu)])
 194 #define safe_get_cpu_lowcore(cpu) \
 195         ((cpu) == smp_processor_id() ? &S390_lowcore : lowcore_ptr[(cpu)])
 196 #endif
 197 #endif /* __ASSEMBLY__ */
 198
 199 #define __PANIC_MAGIC           0xDEADC0DE
 200
 201 #endif
 202