2 * include/asm-s390/pgtable.h
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Hartmut Penner (hp@de.ibm.com)
7 * Ulrich Weigand (weigand@de.ibm.com)
8 * Martin Schwidefsky (schwidefsky@de.ibm.com)
10 * Derived from "include/asm-i386/pgtable.h"
13 #ifndef _ASM_S390_PGTABLE_H
14 #define _ASM_S390_PGTABLE_H
17 * The Linux memory management assumes a three-level page table setup. On
18 * the S390, we use that, but "fold" the mid level into the top-level page
19 * table, so that we physically have the same two-level page table as the
22 * The "pgd_xxx()" functions are trivial for a folded two-level
23 * setup: the pgd is never bad, and a pmd always exists (as it's folded
26 * This file contains the functions and defines necessary to modify and use
27 * the S390 page table tree.
30 #include <asm/processor.h>
31 #include <linux/threads.h>
33 extern pgd_t swapper_pg_dir[] __attribute__ ((aligned (4096)));
34 extern void paging_init(void);
36 /* Caches aren't brain-dead on S390. */
37 #define flush_cache_all() do { } while (0)
38 #define flush_cache_mm(mm) do { } while (0)
39 #define flush_cache_range(mm, start, end) do { } while (0)
40 #define flush_cache_page(vma, vmaddr) do { } while (0)
41 #define flush_page_to_ram(page) do { } while (0)
42 #define flush_dcache_page(page) do { } while (0)
43 #define flush_icache_range(start, end) do { } while (0)
44 #define flush_icache_page(vma,pg) do { } while (0)
45 #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
48 * The S390 doesn't have any external MMU info: the kernel page
49 * tables contain all the necessary information.
51 #define update_mmu_cache(vma, address, pte) do { } while (0)
54 * ZERO_PAGE is a global shared page that is always zero: used
55 * for zero-mapped memory areas etc..
57 extern char empty_zero_page[PAGE_SIZE];
58 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
59 #endif /* !__ASSEMBLY__ */
62 * PMD_SHIFT determines the size of the area a second-level page
66 #define PMD_SIZE (1UL << PMD_SHIFT)
67 #define PMD_MASK (~(PMD_SIZE-1))
69 /* PGDIR_SHIFT determines what a third-level page table entry can map */
70 #define PGDIR_SHIFT 22
71 #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
72 #define PGDIR_MASK (~(PGDIR_SIZE-1))
75 * entries per page directory level: the S390 is two-level, so
76 * we don't really have any PMD directory physically.
77 * for S390 segment-table entries are combined to one PGD
78 * that leads to 1024 pte per pgd
80 #define PTRS_PER_PTE 1024
81 #define PTRS_PER_PMD 1
82 #define PTRS_PER_PGD 512
85 * pgd entries used up by user/kernel:
87 #define USER_PTRS_PER_PGD 512
88 #define USER_PGD_PTRS 512
89 #define KERNEL_PGD_PTRS 512
90 #define FIRST_USER_PGD_NR 0
92 #define pte_ERROR(e) \
93 printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
94 #define pmd_ERROR(e) \
95 printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
96 #define pgd_ERROR(e) \
97 printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
101 * Just any arbitrary offset to the start of the vmalloc VM area: the
102 * current 8MB value just means that there will be a 8MB "hole" after the
103 * physical memory until the kernel virtual memory starts. That means that
104 * any out-of-bounds memory accesses will hopefully be caught.
105 * The vmalloc() routines leaves a hole of 4kB between each vmalloced
106 * area for the same reason. ;)
108 #define VMALLOC_OFFSET (8*1024*1024)
109 #define VMALLOC_START (((unsigned long) high_memory + VMALLOC_OFFSET) \
110 & ~(VMALLOC_OFFSET-1))
111 #define VMALLOC_VMADDR(x) ((unsigned long)(x))
112 #define VMALLOC_END (0x7fffffffL)
116 * A pagetable entry of S390 has following format:
119 * 00000000001111111111222222222233
120 * 01234567890123456789012345678901
122 * I Page-Invalid Bit: Page is not available for address-translation
123 * P Page-Protection Bit: Store access not possible for page
125 * A segmenttable entry of S390 has following format:
126 * | P-table origin | |PTL
128 * 00000000001111111111222222222233
129 * 01234567890123456789012345678901
131 * I Segment-Invalid Bit: Segment is not available for address-translation
132 * C Common-Segment Bit: Segment is not private (PoP 3-30)
133 * PTL Page-Table-Length: Page-table length (PTL+1*16 entries -> up to 256)
135 * The segmenttable origin of S390 has following format:
137 * |S-table origin | | STL |
139 * 00000000001111111111222222222233
140 * 01234567890123456789012345678901
142 * X Space-Switch event:
143 * G Segment-Invalid Bit: *
144 * P Private-Space Bit: Segment is not private (PoP 3-30)
145 * S Storage-Alteration:
146 * STL Segment-Table-Length: Segment-table length (STL+1*16 entries -> up to 2048)
148 * A storage key has the following format:
152 * F : fetch protection bit
157 /* Bits in the page table entry */
158 #define _PAGE_PRESENT 0x001 /* Software */
159 #define _PAGE_MKCLEAN 0x002 /* Software */
160 #define _PAGE_ISCLEAN 0x004 /* Software */
161 #define _PAGE_RO 0x200 /* HW read-only */
162 #define _PAGE_INVALID 0x400 /* HW invalid */
164 /* Bits in the segment table entry */
165 #define _PAGE_TABLE_LEN 0xf /* only full page-tables */
166 #define _PAGE_TABLE_COM 0x10 /* common page-table */
167 #define _PAGE_TABLE_INV 0x20 /* invalid page-table */
168 #define _SEG_PRESENT 0x001 /* Software (overlap with PTL) */
170 /* Bits int the storage key */
171 #define _PAGE_CHANGED 0x02 /* HW changed bit */
172 #define _PAGE_REFERENCED 0x04 /* HW referenced bit */
174 #define _USER_SEG_TABLE_LEN 0x7f /* user-segment-table up to 2 GB */
175 #define _KERNEL_SEG_TABLE_LEN 0x7f /* kernel-segment-table up to 2 GB */
178 * User and Kernel pagetables are identical
180 #define _PAGE_TABLE (_PAGE_TABLE_LEN )
181 #define _KERNPG_TABLE (_PAGE_TABLE_LEN )
184 * The Kernel segment-tables includes the User segment-table
187 #define _SEGMENT_TABLE (_USER_SEG_TABLE_LEN|0x80000000|0x100)
188 #define _KERNSEG_TABLE (_KERNEL_SEG_TABLE_LEN)
191 * No mapping available
193 #define PAGE_INVALID __pgprot(_PAGE_INVALID)
194 #define PAGE_NONE_SHARED __pgprot(_PAGE_PRESENT|_PAGE_INVALID)
195 #define PAGE_NONE_PRIVATE __pgprot(_PAGE_PRESENT|_PAGE_INVALID|_PAGE_ISCLEAN)
196 #define PAGE_RO_SHARED __pgprot(_PAGE_PRESENT|_PAGE_RO)
197 #define PAGE_RO_PRIVATE __pgprot(_PAGE_PRESENT|_PAGE_RO|_PAGE_ISCLEAN)
198 #define PAGE_COPY __pgprot(_PAGE_PRESENT|_PAGE_RO|_PAGE_ISCLEAN)
199 #define PAGE_SHARED __pgprot(_PAGE_PRESENT)
200 #define PAGE_KERNEL __pgprot(_PAGE_PRESENT)
203 * The S390 can't do page protection for execute, and considers that the
204 * same are read. Also, write permissions imply read permissions. This is
205 * the closest we can get..
208 #define __P000 PAGE_NONE_PRIVATE
209 #define __P001 PAGE_RO_PRIVATE
210 #define __P010 PAGE_COPY
211 #define __P011 PAGE_COPY
212 #define __P100 PAGE_RO_PRIVATE
213 #define __P101 PAGE_RO_PRIVATE
214 #define __P110 PAGE_COPY
215 #define __P111 PAGE_COPY
217 #define __S000 PAGE_NONE_SHARED
218 #define __S001 PAGE_RO_SHARED
219 #define __S010 PAGE_SHARED
220 #define __S011 PAGE_SHARED
221 #define __S100 PAGE_RO_SHARED
222 #define __S101 PAGE_RO_SHARED
223 #define __S110 PAGE_SHARED
224 #define __S111 PAGE_SHARED
227 * Certain architectures need to do special things when PTEs
228 * within a page table are directly modified. Thus, the following
229 * hook is made available.
231 extern inline void set_pte(pte_t *pteptr, pte_t pteval)
233 if ((pte_val(pteval) & (_PAGE_MKCLEAN|_PAGE_INVALID))
236 pte_val(pteval) &= ~_PAGE_MKCLEAN;
238 asm volatile ("sske %0,%1"
239 : : "d" (0), "a" (pte_val(pteval)));
245 #define pages_to_mb(x) ((x) >> (20-PAGE_SHIFT))
248 * pgd/pmd/pte query functions
250 extern inline int pgd_present(pgd_t pgd) { return 1; }
251 extern inline int pgd_none(pgd_t pgd) { return 0; }
252 extern inline int pgd_bad(pgd_t pgd) { return 0; }
254 extern inline int pmd_present(pmd_t pmd) { return pmd_val(pmd) & _SEG_PRESENT; }
255 extern inline int pmd_none(pmd_t pmd) { return pmd_val(pmd) & _PAGE_TABLE_INV; }
256 extern inline int pmd_bad(pmd_t pmd)
258 return (pmd_val(pmd) & (~PAGE_MASK & ~_PAGE_TABLE_INV)) != _PAGE_TABLE;
261 extern inline int pte_present(pte_t pte) { return pte_val(pte) & _PAGE_PRESENT; }
262 extern inline int pte_none(pte_t pte)
264 return ((pte_val(pte) &
265 (_PAGE_INVALID | _PAGE_RO | _PAGE_PRESENT)) == _PAGE_INVALID);
268 #define pte_same(a,b) (pte_val(a) == pte_val(b))
271 * query functions pte_write/pte_dirty/pte_young only work if
272 * pte_present() is true. Undefined behaviour if not..
274 extern inline int pte_write(pte_t pte)
276 return (pte_val(pte) & _PAGE_RO) == 0;
279 extern inline int pte_dirty(pte_t pte)
283 if (pte_val(pte) & _PAGE_ISCLEAN)
285 asm volatile ("iske %0,%1" : "=d" (skey) : "a" (pte_val(pte)));
286 return skey & _PAGE_CHANGED;
289 extern inline int pte_young(pte_t pte)
293 asm volatile ("iske %0,%1" : "=d" (skey) : "a" (pte_val(pte)));
294 return skey & _PAGE_REFERENCED;
298 * pgd/pmd/pte modification functions
300 extern inline void pgd_clear(pgd_t * pgdp) { }
302 extern inline void pmd_clear(pmd_t * pmdp)
304 pmd_val(pmdp[0]) = _PAGE_TABLE_INV;
305 pmd_val(pmdp[1]) = _PAGE_TABLE_INV;
306 pmd_val(pmdp[2]) = _PAGE_TABLE_INV;
307 pmd_val(pmdp[3]) = _PAGE_TABLE_INV;
310 extern inline void pte_clear(pte_t *ptep)
312 pte_val(*ptep) = _PAGE_INVALID;
315 #define PTE_INIT(x) pte_clear(x)
318 * The following pte modification functions only work if
319 * pte_present() is true. Undefined behaviour if not..
321 extern inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
323 pte_val(pte) &= PAGE_MASK | _PAGE_ISCLEAN;
324 pte_val(pte) |= pgprot_val(newprot) & ~_PAGE_ISCLEAN;
328 extern inline pte_t pte_wrprotect(pte_t pte)
330 pte_val(pte) |= _PAGE_RO;
334 extern inline pte_t pte_mkwrite(pte_t pte)
336 pte_val(pte) &= ~_PAGE_RO;
340 extern inline pte_t pte_mkclean(pte_t pte)
342 /* The only user of pte_mkclean is the fork() code.
343 We must *not* clear the *physical* page dirty bit
344 just because fork() wants to clear the dirty bit in
345 *one* of the page's mappings. So we just do nothing. */
349 extern inline pte_t pte_mkdirty(pte_t pte)
351 /* We do not explicitly set the dirty bit because the
352 * sske instruction is slow. It is faster to let the
353 * next instruction set the dirty bit.
355 pte_val(pte) &= ~(_PAGE_MKCLEAN | _PAGE_ISCLEAN);
359 extern inline pte_t pte_mkold(pte_t pte)
361 asm volatile ("rrbe 0,%0" : : "a" (pte_val(pte)) : "cc" );
365 extern inline pte_t pte_mkyoung(pte_t pte)
367 /* To set the referenced bit we read the first word from the real
368 * page with a special instruction: load using real address (lura).
369 * Isn't S/390 a nice architecture ?! */
370 asm volatile ("lura 0,%0" : : "a" (pte_val(pte) & PAGE_MASK) : "0" );
374 static inline int ptep_test_and_clear_young(pte_t *ptep)
378 asm volatile ("rrbe 0,%1\n\t"
381 : "=d" (ccode) : "a" (pte_val(*ptep)) : "cc" );
385 static inline int ptep_test_and_clear_dirty(pte_t *ptep)
389 if (pte_val(*ptep) & _PAGE_ISCLEAN)
391 asm volatile ("iske %0,%1" : "=d" (skey) : "a" (*ptep));
392 if ((skey & _PAGE_CHANGED) == 0)
394 /* We can't clear the changed bit atomically. For now we
395 * clear (!) the page referenced bit. */
396 asm volatile ("sske %0,%1"
397 : : "d" (0), "a" (*ptep));
401 static inline pte_t ptep_get_and_clear(pte_t *ptep)
408 static inline void ptep_set_wrprotect(pte_t *ptep)
410 pte_t old_pte = *ptep;
411 set_pte(ptep, pte_wrprotect(old_pte));
414 static inline void ptep_mkdirty(pte_t *ptep)
420 * Conversion functions: convert a page and protection to a page entry,
421 * and a page entry and page directory to the page they refer to.
423 static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
426 pte_val(__pte) = physpage + pgprot_val(pgprot);
430 #define mk_pte(pg, pgprot) \
432 struct page *__page = (pg); \
433 pgprot_t __pgprot = (pgprot); \
434 unsigned long __physpage = __pa((__page-mem_map) << PAGE_SHIFT); \
435 pte_t __pte = mk_pte_phys(__physpage, __pgprot); \
437 if (!(pgprot_val(__pgprot) & _PAGE_ISCLEAN)) { \
438 int __users = !!__page->buffers + !!__page->mapping; \
439 if (__users + page_count(__page) == 1) \
440 pte_val(__pte) |= _PAGE_MKCLEAN; \
445 #define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT)))
447 #define pmd_page(pmd) \
448 ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
450 /* to find an entry in a page-table-directory */
451 #define pgd_index(address) ((address >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
452 #define pgd_offset(mm, address) ((mm)->pgd+pgd_index(address))
454 /* to find an entry in a kernel page-table-directory */
455 #define pgd_offset_k(address) pgd_offset(&init_mm, address)
457 /* Find an entry in the second-level page table.. */
458 extern inline pmd_t * pmd_offset(pgd_t * dir, unsigned long address)
460 return (pmd_t *) dir;
463 /* Find an entry in the third-level page table.. */
464 #define pte_offset(pmd, address) \
465 ((pte_t *) (pmd_page(*pmd) + ((address>>10) & ((PTRS_PER_PTE-1)<<2))))
468 * A page-table entry has some bits we have to treat in a special way.
469 * Bits 0, 20 and bit 23 have to be zero, otherwise an specification
470 * exception will occur instead of a page translation exception. The
471 * specifiation exception has the bad habit not to store necessary
472 * information in the lowcore.
473 * Bit 21 and bit 22 are the page invalid bit and the page protection
474 * bit. We set both to indicate a swapped page.
475 * Bit 31 is used as the software page present bit. If a page is
476 * swapped this obviously has to be zero.
477 * This leaves the bits 1-19 and bits 24-30 to store type and offset.
478 * We use the 7 bits from 24-30 for the type and the 19 bits from 1-19
480 * 0| offset |0110|type |0
481 * 00000000001111111111222222222233
482 * 01234567890123456789012345678901
484 extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
487 pte_val(pte) = (type << 1) | (offset << 12) | _PAGE_INVALID | _PAGE_RO;
488 pte_val(pte) &= 0x7ffff6fe; /* better to be paranoid */
492 #define SWP_TYPE(entry) (((entry).val >> 1) & 0x3f)
493 #define SWP_OFFSET(entry) (((entry).val >> 12) & 0x7FFFF )
494 #define SWP_ENTRY(type,offset) ((swp_entry_t) { pte_val(mk_swap_pte((type),(offset))) })
496 #define pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
497 #define swp_entry_to_pte(x) ((pte_t) { (x).val })
499 #endif /* !__ASSEMBLY__ */
501 /* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
502 #define PageSkip(page) (0)
503 #define kern_addr_valid(addr) (1)
506 * No page table caches to initialise
508 #define pgtable_cache_init() do { } while (0)
510 #endif /* _S390_PAGE_H */