2 * include/asm-s390/ptrace.h
5 * Copyright (C) 1999,2000 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Denis Joseph Barrow (djbarrow@de.ibm.com,barrow_dj@yahoo.com)
10 #define _S390_PTRACE_H
13 * Offsets in the user_regs_struct. They are used for the ptrace
14 * system call and in entry.S
16 #define PT_PSWMASK 0x00
17 #define PT_PSWADDR 0x04
50 #define PT_ORIGGPR2 0x88
53 * A nasty fact of life that the ptrace api
54 * only supports passing of longs.
56 #define PT_FPR0_HI 0x98
57 #define PT_FPR0_LO 0x9C
58 #define PT_FPR1_HI 0xA0
59 #define PT_FPR1_LO 0xA4
60 #define PT_FPR2_HI 0xA8
61 #define PT_FPR2_LO 0xAC
62 #define PT_FPR3_HI 0xB0
63 #define PT_FPR3_LO 0xB4
64 #define PT_FPR4_HI 0xB8
65 #define PT_FPR4_LO 0xBC
66 #define PT_FPR5_HI 0xC0
67 #define PT_FPR5_LO 0xC4
68 #define PT_FPR6_HI 0xC8
69 #define PT_FPR6_LO 0xCC
70 #define PT_FPR7_HI 0xD0
71 #define PT_FPR7_LO 0xD4
72 #define PT_FPR8_HI 0xD8
73 #define PT_FPR8_LO 0XDC
74 #define PT_FPR9_HI 0xE0
75 #define PT_FPR9_LO 0xE4
76 #define PT_FPR10_HI 0xE8
77 #define PT_FPR10_LO 0xEC
78 #define PT_FPR11_HI 0xF0
79 #define PT_FPR11_LO 0xF4
80 #define PT_FPR12_HI 0xF8
81 #define PT_FPR12_LO 0xFC
82 #define PT_FPR13_HI 0x100
83 #define PT_FPR13_LO 0x104
84 #define PT_FPR14_HI 0x108
85 #define PT_FPR14_LO 0x10C
86 #define PT_FPR15_HI 0x110
87 #define PT_FPR15_LO 0x114
89 #define PT_CR_10 0x11C
90 #define PT_CR_11 0x120
91 #define PT_IEEE_IP 0x13C
92 #define PT_LASTOFF PT_IEEE_IP
93 #define PT_ENDREGS 0x140-1
102 #define FPC_PAD_SIZE 4 /* gcc insists on aligning the fpregs */
106 #define STACK_FRAME_OVERHEAD 96 /* size of minimum stack frame */
109 #include <linux/config.h>
110 #include <linux/stddef.h>
111 #include <linux/types.h>
113 #include <asm/current.h>
114 #include <asm/setup.h>
116 /* this typedef defines how a Program Status Word looks like */
121 } __attribute__ ((aligned(8))) psw_t;
124 #define FIX_PSW(addr) ((unsigned long)(addr)|0x80000000UL)
125 #define ADDR_BITS_REMOVE(addr) ((addr)&0x7fffffff)
143 freg_t fprs[NUM_FPRS];
146 #define FPC_EXCEPTION_MASK 0xF8000000
147 #define FPC_FLAGS_MASK 0x00F80000
148 #define FPC_DXC_MASK 0x0000FF00
149 #define FPC_RM_MASK 0x00000003
150 #define FPC_VALID_MASK 0xF8F8FF03
153 * The first entries in pt_regs and user_regs_struct
154 * are common for the two structures. The s390_regs structure
155 * covers the common parts. It simplifies copying the common part
156 * between the three structures.
161 __u32 gprs[NUM_GPRS];
162 __u32 acrs[NUM_ACRS];
167 * The pt_regs struct defines the way the registers are stored on
168 * the stack during a system call.
173 __u32 gprs[NUM_GPRS];
174 __u32 acrs[NUM_ACRS];
180 * Now for the program event recording (trace) definitions.
187 #define PER_EM_MASK 0xE8000000
191 unsigned em_branching : 1;
192 unsigned em_instruction_fetch : 1;
194 * Switching on storage alteration automatically fixes
195 * the storage alteration event bit in the users std.
197 unsigned em_storage_alteration : 1;
198 unsigned em_gpr_alt_unused : 1;
199 unsigned em_store_real_address : 1;
201 unsigned branch_addr_ctl : 1;
203 unsigned storage_alt_space_ctl : 1;
205 addr_t starting_addr;
211 __u16 perc_atmid; /* 0x096 */
212 __u32 address; /* 0x098 */
213 __u8 access_id; /* 0x0a1 */
218 unsigned perc_branching : 1; /* 0x096 */
219 unsigned perc_instruction_fetch : 1;
220 unsigned perc_storage_alteration : 1;
221 unsigned perc_gpr_alt_unused : 1;
222 unsigned perc_store_real_address : 1;
224 unsigned atmid_validity_bit : 1;
225 unsigned atmid_psw_bit_32 : 1;
226 unsigned atmid_psw_bit_5 : 1;
227 unsigned atmid_psw_bit_16 : 1;
228 unsigned atmid_psw_bit_17 : 1;
230 addr_t address; /* 0x098 */
231 unsigned : 4; /* 0x0a1 */
232 unsigned access_id : 4;
242 * Use these flags instead of setting em_instruction_fetch
243 * directly they are used so that single stepping can be
244 * switched on & off while not affecting other tracing
246 unsigned single_step : 1;
247 unsigned instruction_fetch : 1;
250 * These addresses are copied into cr10 & cr11 if single
251 * stepping is switched off
256 per_lowcore_words words;
257 per_lowcore_bits bits;
269 * S/390 specific non posix ptrace requests. I chose unusual values so
270 * they are unlikely to clash with future ptrace definitions.
272 #define PTRACE_PEEKUSR_AREA 0x5000
273 #define PTRACE_POKEUSR_AREA 0x5001
274 #define PTRACE_PEEKTEXT_AREA 0x5002
275 #define PTRACE_PEEKDATA_AREA 0x5003
276 #define PTRACE_POKETEXT_AREA 0x5004
277 #define PTRACE_POKEDATA_AREA 0x5005
279 * PT_PROT definition is loosely based on hppa bsd definition in
282 #define PTRACE_PROT 21
286 ptprot_set_access_watchpoint,
287 ptprot_set_write_watchpoint,
288 ptprot_disable_watchpoint
298 /* Sequence of bytes for breakpoint illegal instruction. */
299 #define S390_BREAKPOINT {0x0,0x1}
300 #define S390_BREAKPOINT_U16 ((__u16)0x0001)
301 #define S390_SYSCALL_OPCODE ((__u16)0x0a00)
302 #define S390_SYSCALL_SIZE 2
305 * The user_regs_struct defines the way the user registers are
306 * store on the stack for signal handling.
308 struct user_regs_struct
311 __u32 gprs[NUM_GPRS];
312 __u32 acrs[NUM_ACRS];
314 s390_fp_regs fp_regs;
316 * These per registers are in here so that gdb can modify them
317 * itself as there is no "official" ptrace interface for hardware
318 * watchpoints. This is the way intel does it.
321 addr_t ieee_instruction_pointer;
322 /* Used to give failing instruction back to user for ieee exceptions */
326 #define user_mode(regs) (((regs)->psw.mask & PSW_PROBLEM_STATE) != 0)
327 #define instruction_pointer(regs) ((regs)->psw.addr)
328 extern void show_regs(struct pt_regs * regs);
329 extern char *task_show_regs(struct task_struct *task, char *buffer);
332 #endif /* __ASSEMBLY__ */
334 #endif /* _S390_PTRACE_H */