2 * include/asm-s390/system.h
5 * Copyright (C) 1999 IBM Deutschland Entwicklung GmbH, IBM Corporation
6 * Author(s): Martin Schwidefsky (schwidefsky@de.ibm.com),
8 * Derived from "include/asm-i386/system.h"
11 #ifndef __ASM_SYSTEM_H
12 #define __ASM_SYSTEM_H
14 #include <linux/config.h>
15 #include <asm/types.h>
17 #include <asm/lowcore.h>
19 #include <linux/kernel.h>
21 #define prepare_to_switch() do { } while(0)
22 #define switch_to(prev,next,last) do { \
25 save_fp_regs1(&prev->thread.fp_regs); \
26 restore_fp_regs1(&next->thread.fp_regs); \
27 last = resume(prev,next); \
32 #define nop() __asm__ __volatile__ ("nop")
34 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
36 extern void __misaligned_u16(void);
37 extern void __misaligned_u32(void);
39 static inline unsigned long __xchg(unsigned long x, void * ptr, int size)
45 " nr 1,%0\n" /* isolate last 2 bits */
46 " xr %0,1\n" /* align ptr */
48 " icm 1,8,3(%1)\n" /* for ptr&3 == 0 */
50 " icm 1,4,3(%1)\n" /* for ptr&3 == 1 */
52 " icm 1,2,3(%1)\n" /* for ptr&3 == 2 */
54 " icm 1,1,3(%1)\n" /* for ptr&3 == 3 */
57 " la 2,0(1,2)\n" /* r2 points to an icm */
58 " l 0,0(%0)\n" /* get fullword */
59 "1: lr 1,0\n" /* cs loop */
60 " ex 0,0(2)\n" /* insert x */
63 " ex 0,4(2)" /* store *ptr to x */
64 : "+a&" (ptr) : "a" (&x)
65 : "memory", "cc", "0", "1", "2");
72 " nr 1,%0\n" /* isolate bit 2^1 */
73 " xr %0,1\n" /* align ptr */
75 " icm 1,12,2(%1)\n" /* for ptr&2 == 0 */
77 " icm 1,3,2(%1)\n" /* for ptr&2 == 1 */
80 " la 2,0(1,2)\n" /* r2 points to an icm */
81 " l 0,0(%0)\n" /* get fullword */
82 "1: lr 1,0\n" /* cs loop */
83 " ex 0,0(2)\n" /* insert x */
86 " ex 0,4(2)" /* store *ptr to x */
87 : "+a&" (ptr) : "a" (&x)
88 : "memory", "cc", "0", "1", "2");
98 : "+d&" (x) : "a" (ptr)
99 : "memory", "cc", "0" );
106 * Force strict CPU ordering.
107 * And yes, this is required on UP too when we're talking
110 * This is very similar to the ppc eieio/sync instruction in that is
111 * does a checkpoint syncronisation & makes sure that
112 * all memory ops have completed wrt other CPU's ( see 7-15 POP DJB ).
115 #define eieio() __asm__ __volatile__ ("BCR 15,0")
116 # define SYNC_OTHER_CORES(x) eieio()
118 #define rmb() eieio()
119 #define wmb() eieio()
120 #define smp_mb() mb()
121 #define smp_rmb() rmb()
122 #define smp_wmb() wmb()
123 #define smp_mb__before_clear_bit() smp_mb()
124 #define smp_mb__after_clear_bit() smp_mb()
127 #define set_mb(var, value) do { var = value; mb(); } while (0)
128 #define set_wmb(var, value) do { var = value; wmb(); } while (0)
130 /* interrupt control.. */
133 __asm__ __volatile__ ( \
134 "stosm 0(%0),0x03" : : "a" (&dummy) : "memory"); \
139 __asm__ __volatile__ ( \
140 "stnsm 0(%0),0xFC" : : "a" (&flags) : "memory"); \
144 #define __save_flags(x) \
145 __asm__ __volatile__("stosm 0(%0),0" : : "a" (&x) : "memory")
147 #define __restore_flags(x) \
148 __asm__ __volatile__("ssm 0(%0)" : : "a" (&x) : "memory")
150 #define __load_psw(psw) \
151 __asm__ __volatile__("lpsw 0(%0)" : : "a" (&psw) : "cc" );
153 #define __ctl_load(array, low, high) ({ \
154 __asm__ __volatile__ ( \
159 : : "m" (array), "a" (((low)<<4)+(high)) : "1", "2" ); \
162 #define __ctl_store(array, low, high) ({ \
163 __asm__ __volatile__ ( \
166 " stctl 0,0,0(1)\n" \
168 : "=m" (array) : "a" (((low)<<4)+(high)): "1", "2" ); \
171 #define __ctl_set_bit(cr, bit) ({ \
173 __asm__ __volatile__ ( \
174 " la 1,%0\n" /* align to 8 byte */ \
178 " bras 2,0f\n" /* skip indirect insns */ \
179 " stctl 0,0,0(1)\n" \
181 "0: ex %1,0(2)\n" /* execute stctl */ \
183 " or 0,%2\n" /* set the bit */ \
185 "1: ex %1,4(2)" /* execute lctl */ \
186 : "=m" (dummy) : "a" (cr*17), "a" (1<<(bit)) \
187 : "cc", "0", "1", "2"); \
190 #define __ctl_clear_bit(cr, bit) ({ \
192 __asm__ __volatile__ ( \
193 " la 1,%0\n" /* align to 8 byte */ \
197 " bras 2,0f\n" /* skip indirect insns */ \
198 " stctl 0,0,0(1)\n" \
200 "0: ex %1,0(2)\n" /* execute stctl */ \
202 " nr 0,%2\n" /* set the bit */ \
204 "1: ex %1,4(2)" /* execute lctl */ \
205 : "=m" (dummy) : "a" (cr*17), "a" (~(1<<(bit))) \
206 : "cc", "0", "1", "2"); \
209 #define __save_and_cli(x) do { __save_flags(x); __cli(); } while(0);
210 #define __save_and_sti(x) do { __save_flags(x); __sti(); } while(0);
212 /* For spinlocks etc */
213 #define local_irq_save(x) ((x) = __cli())
214 #define local_irq_set(x) __save_and_sti(x)
215 #define local_irq_restore(x) __restore_flags(x)
216 #define local_irq_disable() __cli()
217 #define local_irq_enable() __sti()
221 extern void __global_cli(void);
222 extern void __global_sti(void);
224 extern unsigned long __global_save_flags(void);
225 extern void __global_restore_flags(unsigned long);
226 #define cli() __global_cli()
227 #define sti() __global_sti()
228 #define save_flags(x) ((x)=__global_save_flags())
229 #define restore_flags(x) __global_restore_flags(x)
230 #define save_and_cli(x) do { save_flags(x); cli(); } while(0);
231 #define save_and_sti(x) do { save_flags(x); sti(); } while(0);
233 extern void smp_ctl_set_bit(int cr, int bit);
234 extern void smp_ctl_clear_bit(int cr, int bit);
235 #define ctl_set_bit(cr, bit) smp_ctl_set_bit(cr, bit)
236 #define ctl_clear_bit(cr, bit) smp_ctl_clear_bit(cr, bit)
240 #define cli() __cli()
241 #define sti() __sti()
242 #define save_flags(x) __save_flags(x)
243 #define restore_flags(x) __restore_flags(x)
244 #define save_and_cli(x) __save_and_cli(x)
245 #define save_and_sti(x) __save_and_sti(x)
247 #define ctl_set_bit(cr, bit) __ctl_set_bit(cr, bit)
248 #define ctl_clear_bit(cr, bit) __ctl_clear_bit(cr, bit)
254 extern struct task_struct *resume(void *, void *);
256 extern int save_fp_regs1(s390_fp_regs *fpregs);
257 extern void save_fp_regs(s390_fp_regs *fpregs);
258 extern int restore_fp_regs1(s390_fp_regs *fpregs);
259 extern void restore_fp_regs(s390_fp_regs *fpregs);
261 extern void (*_machine_restart)(char *command);
262 extern void (*_machine_halt)(void);
263 extern void (*_machine_power_off)(void);