1 /* $Id: ide.h,v 1.1.1.1 2005/04/11 02:50:57 jack Exp $
2 * ide.h: Ultra/PCI specific IDE glue.
4 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
5 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
13 #include <linux/config.h>
14 #include <asm/pgalloc.h>
16 #include <asm/hdreg.h>
18 #include <asm/spitfire.h>
23 static __inline__ int ide_default_irq(ide_ioreg_t base)
28 static __inline__ ide_ioreg_t ide_default_io_base(int index)
33 static __inline__ void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, ide_ioreg_t ctrl_port, int *irq)
35 ide_ioreg_t reg = data_port;
38 for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) {
39 hw->io_ports[i] = reg;
43 hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port;
45 hw->io_ports[IDE_CONTROL_OFFSET] = 0;
49 hw->io_ports[IDE_IRQ_OFFSET] = 0;
53 * This registers the standard ports for this architecture with the IDE
56 static __inline__ void ide_init_default_hwifs(void)
58 #ifndef CONFIG_BLK_DEV_IDEPCI
62 for (index = 0; index < MAX_HWIFS; index++) {
63 ide_init_hwif_ports(&hw, ide_default_io_base(index), 0, NULL);
64 hw.irq = ide_default_irq(ide_default_io_base(index));
65 ide_register_hw(&hw, NULL);
67 #endif /* CONFIG_BLK_DEV_IDEPCI */
70 #undef SUPPORT_SLOW_DATA_PORTS
71 #define SUPPORT_SLOW_DATA_PORTS 0
73 #undef SUPPORT_VLB_SYNC
74 #define SUPPORT_VLB_SYNC 0
77 #define HD_DATA ((ide_ioreg_t)0)
79 #define __ide_insl(data_reg, buffer, wcount) \
80 __ide_insw(data_reg, buffer, (wcount)<<1)
81 #define __ide_outsl(data_reg, buffer, wcount) \
82 __ide_outsw(data_reg, buffer, (wcount)<<1)
84 /* On sparc64, I/O ports and MMIO registers are accessed identically. */
85 #define __ide_mm_insw __ide_insw
86 #define __ide_mm_insl __ide_insl
87 #define __ide_mm_outsw __ide_outsw
88 #define __ide_mm_outsl __ide_outsl
90 static __inline__ unsigned int inw_be(unsigned long addr)
94 __asm__ __volatile__("lduha [%1] %2, %0"
96 : "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
101 static __inline__ void __ide_insw(unsigned long port,
105 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
106 unsigned long end = (unsigned long)dst + (count << 1);
111 if(((u64)ps) & 0x2) {
112 *ps++ = inw_be(port);
119 w = inw_be(port) << 16;
126 *ps++ = inw_be(port);
128 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
129 __flush_dcache_range((unsigned long)dst, end);
133 static __inline__ void outw_be(unsigned short w, unsigned long addr)
135 __asm__ __volatile__("stha %0, [%1] %2"
137 : "r" (w), "r" (addr), "i" (ASI_PHYS_BYPASS_EC_E));
140 static __inline__ void __ide_outsw(unsigned long port,
144 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
145 unsigned long end = (unsigned long)src + (count << 1);
150 if(((u64)src) & 0x2) {
151 outw_be(*ps++, port);
154 pi = (const u32 *)ps;
159 outw_be((w >> 16), port);
163 ps = (const u16 *)pi;
167 #if (L1DCACHE_SIZE > PAGE_SIZE) /* is there D$ aliasing problem */
168 __flush_dcache_range((unsigned long)src, end);
172 #endif /* __KERNEL__ */
174 #endif /* _SPARC64_IDE_H */