2 * @file arch/alpha/oprofile/op_model_ev67.c
4 * @remark Copyright 2002 OProfile authors
5 * @remark Read the file COPYING
7 * @author Richard Henderson <rth@twiddle.net>
8 * @author Falk Hueffner <falk@debian.org>
11 #include <linux/oprofile.h>
12 #include <linux/init.h>
13 #include <linux/smp.h>
14 #include <asm/ptrace.h>
15 #include <asm/system.h>
20 /* Compute all of the registers in preparation for enabling profiling. */
23 ev67_reg_setup(struct op_register_config *reg,
24 struct op_counter_config *ctr,
25 struct op_system_config *sys)
27 unsigned long ctl, reset, need_reset, i;
29 /* Select desired events. */
30 ctl = 1UL << 4; /* Enable ProfileMe mode. */
32 /* The event numbers are chosen so we can use them directly if
35 ctl |= (ctr[1].event & 3) << 2;
37 if (ctr[0].event == 0) /* cycles */
40 reg->mux_select = ctl;
42 /* Select logging options. */
43 /* ??? Need to come up with some mechanism to trace only
44 selected processes. EV67 does not have a mechanism to
45 select kernel or user mode only. For now, enable always. */
48 /* EV67 cannot change the width of the counters as with the
49 other implementations. But fortunately, we can write to
50 the counters and set the value such that it will overflow
52 reset = need_reset = 0;
53 for (i = 0; i < 2; ++i) {
54 unsigned long count = ctr[i].count;
61 reset |= (0x100000 - count) << (i ? 6 : 28);
62 if (count != 0x100000)
65 reg->reset_values = reset;
66 reg->need_reset = need_reset;
69 /* Program all of the registers in preparation for enabling profiling. */
72 ev67_cpu_setup (void *x)
74 struct op_register_config *reg = x;
76 wrperfmon(2, reg->mux_select);
77 wrperfmon(3, reg->proc_mode);
78 wrperfmon(6, reg->reset_values | 3);
81 /* CTR is a counter for which the user has requested an interrupt count
82 in between one of the widths selectable in hardware. Reset the count
83 for CTR to the value stored in REG->RESET_VALUES. */
86 ev67_reset_ctr(struct op_register_config *reg, unsigned long ctr)
88 wrperfmon(6, reg->reset_values | (1 << ctr));
91 /* ProfileMe conditions which will show up as counters. We can also
92 detect the following, but it seems unlikely that anybody is
93 interested in counting them:
95 * MT_FPCR (write to floating point control register)
98 * Machine Check (ECC fault, etc.)
99 * OPCDEC (illegal opcode)
100 * Floating point disabled
101 * Differentiate between DTB single/double misses and 3 or 4 level
103 * Istream access violation
105 * Icache Parity Error.
106 * Instruction killed (nop, trapb)
108 Unfortunately, there seems to be no way to detect Dcache and Bcache
109 misses; the latter could be approximated by making the counter
110 count Bcache misses, but that is not precise.
112 We model this as 20 counters:
115 * 9 ProfileMe events, induced by PCTR0
116 * 9 ProfileMe events, induced by PCTR1
119 enum profileme_counters {
120 PM_STALLED, /* Stalled for at least one cycle
121 between the fetch and map stages */
122 PM_TAKEN, /* Conditional branch taken */
123 PM_MISPREDICT, /* Branch caused mispredict trap */
124 PM_ITB_MISS, /* ITB miss */
125 PM_DTB_MISS, /* DTB miss */
126 PM_REPLAY, /* Replay trap */
127 PM_LOAD_STORE, /* Load-store order trap */
128 PM_ICACHE_MISS, /* Icache miss */
129 PM_UNALIGNED, /* Unaligned Load/Store */
134 op_add_pm(unsigned long pc, int kern, unsigned long counter,
135 struct op_counter_config *ctr, unsigned long event)
137 unsigned long fake_counter = 2 + event;
139 fake_counter += PM_NUM_COUNTERS;
140 if (ctr[fake_counter].enabled)
141 oprofile_add_sample(pc, kern, fake_counter,
146 ev67_handle_interrupt(unsigned long which, struct pt_regs *regs,
147 struct op_counter_config *ctr)
149 unsigned long pmpc, pctr_ctl;
150 int kern = !user_mode(regs);
155 unsigned reserved: 30; /* 0-29 */
156 unsigned overcount: 3; /* 30-32 */
157 unsigned icache_miss: 1; /* 33 */
158 unsigned trap_type: 4; /* 34-37 */
159 unsigned load_store: 1; /* 38 */
160 unsigned trap: 1; /* 39 */
161 unsigned mispredict: 1; /* 40 */
168 TRAP_DTB_DOUBLE_MISS_3,
169 TRAP_DTB_DOUBLE_MISS_4,
172 TRAP_DTB_SINGLE_MISS,
184 pmpc = wrperfmon(9, 0);
185 /* ??? Don't know how to handle physical-mode PALcode address. */
188 pmpc &= ~2; /* clear reserved bit */
190 i_stat.v = wrperfmon(8, 0);
191 if (i_stat.fields.trap) {
192 switch (i_stat.fields.trap_type) {
196 /* Pipeline redirection ocurred. PMPC points
197 to PALcode. Recognize ITB miss by PALcode
198 offset address, and get actual PC from
200 oprofile_add_sample(regs->pc, kern, which,
202 if ((pmpc & ((1 << 15) - 1)) == 581)
203 op_add_pm(regs->pc, kern, which,
205 /* Most other bit and counter values will be
206 those for the first instruction in the
207 fault handler, so we're done. */
210 op_add_pm(pmpc, kern, which, ctr,
211 (i_stat.fields.load_store
212 ? PM_LOAD_STORE : PM_REPLAY));
214 case TRAP_DTB_DOUBLE_MISS_3:
215 case TRAP_DTB_DOUBLE_MISS_4:
216 case TRAP_DTB_SINGLE_MISS:
217 op_add_pm(pmpc, kern, which, ctr, PM_DTB_MISS);
220 op_add_pm(pmpc, kern, which, ctr, PM_UNALIGNED);
223 case TRAP_FP_DISABLED:
224 case TRAP_DSTREAM_FAULT:
226 case TRAP_MACHINE_CHECK:
227 case TRAP_ARITHMETIC:
233 /* ??? JSR/JMP/RET/COR or HW_JSR/HW_JMP/HW_RET/HW_COR
234 mispredicts do not set this bit but can be
235 recognized by the presence of one of these
236 instructions at the PMPC location with bit 39
238 if (i_stat.fields.mispredict) {
240 op_add_pm(pmpc, kern, which, ctr, PM_MISPREDICT);
244 oprofile_add_sample(pmpc, kern, which, smp_processor_id());
246 pctr_ctl = wrperfmon(5, 0);
247 if (pctr_ctl & (1UL << 27))
248 op_add_pm(pmpc, kern, which, ctr, PM_STALLED);
250 /* Unfortunately, TAK is undefined on mispredicted branches.
251 ??? It is also undefined for non-cbranch insns, should
253 if (!mispredict && pctr_ctl & (1UL << 0))
254 op_add_pm(pmpc, kern, which, ctr, PM_TAKEN);
257 struct op_axp_model op_model_ev67 = {
258 .reg_setup = ev67_reg_setup,
259 .cpu_setup = ev67_cpu_setup,
260 .reset_ctr = ev67_reset_ctr,
261 .handle_interrupt = ev67_handle_interrupt,
262 .cpu_type = "alpha/ev67",
264 .can_set_proc_mode = 0,