1 /*****************************************************************************/
4 * crt0_ram.S -- startup code for MCF5206e ColdFire based CADRE3 boards.
6 * (C) Copyright 1999-2002, Greg Ungerer (gerg@snapgear.com)
8 * 1999/02/24 Modified for the 5307 processor David W. Miller
11 /*****************************************************************************/
13 #include "linux/autoconf.h"
14 #include "asm/coldfire.h"
15 #include "asm/mcfsim.h"
17 /*****************************************************************************/
20 * Cadre-III M5206e ColdFire eval board, chip select and memory setup.
23 #define MEM_BASE 0x00000000 /* Memory base at address 0 */
24 #define MEM_SIZE 0x00400000 /* Memory size 4Mb */
25 #define VBR_BASE MEM_BASE /* Vector address */
27 /*****************************************************************************/
35 /*****************************************************************************/
40 * Set up the usable of RAM stuff. Size of RAM is determined then
41 * an initial stack set up at the end.
52 /*****************************************************************************/
57 * This is the codes first entry point. This is where it all
63 move.w #0x2700, %sr /* No interrupts */
66 * Setup VBR here, otherwise buserror remap will not work.
67 * if dBug was active before (on my SBC with dBug 1.1 of Dec 16 1996)
71 * Note: this is because dBUG points VBR to ROM, making vectors read
72 * only, so the bus trap can't be changed. (RS)
74 move.l #VBR_BASE, %a7 /* Note VBR can't be read */
76 move.l %a7, _ramvec /* Set up vector addr */
77 move.l %a7, _rambase /* Set up base RAM addr */
81 * Set to 4 meg for the Cadre III board (m5206e).
85 move.l %a0, %d0 /* Mem end addr is in a0 */
86 move.l %d0, %sp /* Set up initial stack ptr */
87 move.l %d0, _ramend /* Set end ram addr */
91 * Enable CPU internal cache.
93 move.l #0x01000000, %d0 /* Invalidate cache cmd */
94 movec %d0, %CACR /* Invalidate cache */
95 move.l #0x80000100, %d0 /* Setup cache mask */
96 movec %d0, %CACR /* Enable cache */
99 #ifdef CONFIG_ROMFS_FS
101 * Move ROM filesystem above bss :-)
103 lea.l _sbss, %a0 /* Get start of bss */
104 lea.l _ebss, %a1 /* Set up destination */
105 move.l %a0, %a2 /* Copy of bss start */
107 move.l 8(%a0), %d0 /* Get size of ROMFS */
108 addq.l #8, %d0 /* Allow for rounding */
109 and.l #0xfffffffc, %d0 /* Whole words */
111 add.l %d0, %a0 /* Copy from end */
112 add.l %d0, %a1 /* Copy from end */
113 move.l %a1, _ramstart /* Set start of ram */
116 move.l -(%a0), %d0 /* Copy dword */
118 cmp.l %a0, %a2 /* Check if at end */
121 #else /* CONFIG_ROMFS_FS */
123 move.l %a1, _ramstart
124 #endif /* CONFIG_ROMFS_FS */
128 * Zero out the bss region.
130 lea.l _sbss, %a0 /* Get start of bss */
131 lea.l _ebss, %a1 /* Get end of bss */
132 clr.l %d0 /* Set value */
134 move.l %d0, (%a0)+ /* Clear each word */
135 cmp.l %a0, %a1 /* Check if at end */
139 * Load the current task pointer and stack.
141 lea init_thread_union, %a0
145 * Assember start up done, start code proper.
147 jsr start_kernel /* Start Linux kernel */
150 jmp _exit /* Should never get here */
152 /*****************************************************************************/