1 /* $Revision: 1.1.1.1 $$Date: 2006/04/12 06:25:58 $
2 * linux/include/linux/cyclades.h
4 * This file was initially written by
5 * Randolph Bentson <bentson@grieg.seaslug.org> and is maintained by
6 * Ivan Passos <ivan@cyclades.com>.
8 * This file contains the general definitions for the cyclades.c driver
10 *Revision 1.1.1.1 2006/04/12 06:25:58 michaelc
11 *Original Broadcom V3.06.02V release
13 *Revision 3.1 2002/01/29 11:36:16 henrique
14 *added throttle field on struct cyclades_port to indicate whether the
15 *port is throttled or not
17 *Revision 3.1 2000/04/19 18:52:52 ivan
18 *converted address fields to unsigned long and added fields for physical
19 *addresses on cyclades_card structure;
21 *Revision 3.0 1998/11/02 14:20:59 ivan
22 *added nports field on cyclades_card structure;
24 *Revision 2.5 1998/08/03 16:57:01 ivan
25 *added cyclades_idle_stats structure;
27 *Revision 2.4 1998/06/01 12:09:53 ivan
28 *removed closing_wait2 from cyclades_port structure;
30 *Revision 2.3 1998/03/16 18:01:12 ivan
31 *changes in the cyclades_port structure to get it closer to the
32 *standard serial port structure;
33 *added constants for new ioctls;
35 *Revision 2.2 1998/02/17 16:50:00 ivan
36 *changes in the cyclades_port structure (addition of shutdown_wait and
38 *added constants for new ioctls and for CD1400 rev. numbers.
40 *Revision 2.1 1997/10/24 16:03:00 ivan
41 *added rflow (which allows enabling the CD1400 special flow control
42 *feature) and rtsdtr_inv (which allows DTR/RTS pin inversion) to
43 *cyclades_port structure;
46 *Revision 2.0 1997/06/30 10:30:00 ivan
47 *added some new doorbell command constants related to IOCTLW and
50 *Revision 1.8 1997/06/03 15:30:00 ivan
51 *added constant ZFIRM_HLT
52 *added constant CyPCI_Ze_win ( = 2 * Cy_PCI_Zwin)
54 *Revision 1.7 1997/03/26 10:30:00 daniel
55 *new entries at the end of cyclades_port struct to reallocate
56 *variables illegally allocated within card memory.
58 *Revision 1.6 1996/09/09 18:35:30 bentson
59 *fold in changes for Cyclom-Z -- including structures for
60 *communicating with board as well modest changes to original
61 *structures to support new features.
63 *Revision 1.5 1995/11/13 21:13:31 bentson
64 *changes suggested by Michael Chastain <mec@duracef.shout.net>
65 *to support use of this file in non-kernel applications
70 #ifndef _LINUX_CYCLADES_H
71 #define _LINUX_CYCLADES_H
73 struct cyclades_monitor {
74 unsigned long int_count;
75 unsigned long char_count;
76 unsigned long char_max;
77 unsigned long char_last;
81 * These stats all reflect activity since the device was last initialized.
82 * (i.e., since the port was opened with no other processes already having it
85 struct cyclades_idle_stats {
86 time_t in_use; /* Time device has been in use (secs) */
87 time_t recv_idle; /* Time since last char received (secs) */
88 time_t xmit_idle; /* Time since last char transmitted (secs) */
89 unsigned long recv_bytes; /* Bytes received */
90 unsigned long xmit_bytes; /* Bytes transmitted */
91 unsigned long overruns; /* Input overruns */
92 unsigned long frame_errs; /* Input framing errors */
93 unsigned long parity_errs; /* Input parity errors */
96 #define CYCLADES_MAGIC 0x4359
98 #define CYGETMON 0x435901
99 #define CYGETTHRESH 0x435902
100 #define CYSETTHRESH 0x435903
101 #define CYGETDEFTHRESH 0x435904
102 #define CYSETDEFTHRESH 0x435905
103 #define CYGETTIMEOUT 0x435906
104 #define CYSETTIMEOUT 0x435907
105 #define CYGETDEFTIMEOUT 0x435908
106 #define CYSETDEFTIMEOUT 0x435909
107 #define CYSETRFLOW 0x43590a
108 #define CYGETRFLOW 0x43590b
109 #define CYSETRTSDTR_INV 0x43590c
110 #define CYGETRTSDTR_INV 0x43590d
111 #define CYZSETPOLLCYCLE 0x43590e
112 #define CYZGETPOLLCYCLE 0x43590f
113 #define CYGETCD1400VER 0x435910
114 #define CYGETCARDINFO 0x435911
115 #define CYSETWAIT 0x435912
116 #define CYGETWAIT 0x435913
118 /*************** CYCLOM-Z ADDITIONS ***************/
120 #define CZIOC ('M' << 8)
121 #define CZ_NBOARDS (CZIOC|0xfa)
122 #define CZ_BOOT_START (CZIOC|0xfb)
123 #define CZ_BOOT_DATA (CZIOC|0xfc)
124 #define CZ_BOOT_END (CZIOC|0xfd)
125 #define CZ_TEST (CZIOC|0xfe)
127 #define CZ_DEF_POLL (HZ/25)
129 #define MAX_BOARD 4 /* Max number of boards */
130 #define MAX_DEV 256 /* Max number of ports total */
131 #define CYZ_MAX_SPEED 921600
133 #define CYZ_FIFO_SIZE 16
135 #define CYZ_BOOT_NWORDS 0x100
136 struct CYZ_BOOT_CTRL {
137 unsigned short nboard;
138 int status[MAX_BOARD];
139 int nchannel[MAX_BOARD];
140 int fw_rev[MAX_BOARD];
141 unsigned long offset;
142 unsigned long data[CYZ_BOOT_NWORDS];
146 #ifndef DP_WINDOW_SIZE
147 /* #include "cyclomz.h" */
148 /****************** ****************** *******************/
150 * The data types defined below are used in all ZFIRM interface
151 * data structures. They accomodate differences between HW
152 * architectures and compilers.
155 #if defined(__alpha__)
156 typedef unsigned long ucdouble; /* 64 bits, unsigned */
157 typedef unsigned int uclong; /* 32 bits, unsigned */
159 typedef unsigned long uclong; /* 32 bits, unsigned */
161 typedef unsigned short ucshort; /* 16 bits, unsigned */
162 typedef unsigned char ucchar; /* 8 bits, unsigned */
165 * Memory Window Sizes
168 #define DP_WINDOW_SIZE (0x00080000) /* window size 512 Kb */
169 #define ZE_DP_WINDOW_SIZE (0x00100000) /* window size 1 Mb (Ze and
171 #define CTRL_WINDOW_SIZE (0x00000080) /* runtime regs 128 bytes */
174 * CUSTOM_REG - Cyclom-Z/PCI Custom Registers Set. The driver
175 * normally will access only interested on the fpga_id, fpga_version,
176 * start_cpu and stop_cpu.
180 uclong fpga_id; /* FPGA Identification Register */
181 uclong fpga_version; /* FPGA Version Number Register */
182 uclong cpu_start; /* CPU start Register (write) */
183 uclong cpu_stop; /* CPU stop Register (write) */
184 uclong misc_reg; /* Miscelaneous Register */
185 uclong idt_mode; /* IDT mode Register */
186 uclong uart_irq_status; /* UART IRQ status Register */
187 uclong clear_timer0_irq; /* Clear timer interrupt Register */
188 uclong clear_timer1_irq; /* Clear timer interrupt Register */
189 uclong clear_timer2_irq; /* Clear timer interrupt Register */
190 uclong test_register; /* Test Register */
191 uclong test_count; /* Test Count Register */
192 uclong timer_select; /* Timer select register */
193 uclong pr_uart_irq_status; /* Prioritized UART IRQ stat Reg */
194 uclong ram_wait_state; /* RAM wait-state Register */
195 uclong uart_wait_state; /* UART wait-state Register */
196 uclong timer_wait_state; /* timer wait-state Register */
197 uclong ack_wait_state; /* ACK wait State Register */
201 * RUNTIME_9060 - PLX PCI9060ES local configuration and shared runtime
202 * registers. This structure can be used to access the 9060 registers
206 struct RUNTIME_9060 {
207 uclong loc_addr_range; /* 00h - Local Address Range */
208 uclong loc_addr_base; /* 04h - Local Address Base */
209 uclong loc_arbitr; /* 08h - Local Arbitration */
210 uclong endian_descr; /* 0Ch - Big/Little Endian Descriptor */
211 uclong loc_rom_range; /* 10h - Local ROM Range */
212 uclong loc_rom_base; /* 14h - Local ROM Base */
213 uclong loc_bus_descr; /* 18h - Local Bus descriptor */
214 uclong loc_range_mst; /* 1Ch - Local Range for Master to PCI */
215 uclong loc_base_mst; /* 20h - Local Base for Master PCI */
216 uclong loc_range_io; /* 24h - Local Range for Master IO */
217 uclong pci_base_mst; /* 28h - PCI Base for Master PCI */
218 uclong pci_conf_io; /* 2Ch - PCI configuration for Master IO */
219 uclong filler1; /* 30h */
220 uclong filler2; /* 34h */
221 uclong filler3; /* 38h */
222 uclong filler4; /* 3Ch */
223 uclong mail_box_0; /* 40h - Mail Box 0 */
224 uclong mail_box_1; /* 44h - Mail Box 1 */
225 uclong mail_box_2; /* 48h - Mail Box 2 */
226 uclong mail_box_3; /* 4Ch - Mail Box 3 */
227 uclong filler5; /* 50h */
228 uclong filler6; /* 54h */
229 uclong filler7; /* 58h */
230 uclong filler8; /* 5Ch */
231 uclong pci_doorbell; /* 60h - PCI to Local Doorbell */
232 uclong loc_doorbell; /* 64h - Local to PCI Doorbell */
233 uclong intr_ctrl_stat; /* 68h - Interrupt Control/Status */
234 uclong init_ctrl; /* 6Ch - EEPROM control, Init Control, etc */
237 /* Values for the Local Base Address re-map register */
239 #define WIN_RAM 0x00000001L /* set the sliding window to RAM */
240 #define WIN_CREG 0x14000001L /* set the window to custom Registers */
242 /* Values timer select registers */
244 #define TIMER_BY_1M 0x00 /* clock divided by 1M */
245 #define TIMER_BY_256K 0x01 /* clock divided by 256k */
246 #define TIMER_BY_128K 0x02 /* clock divided by 128k */
247 #define TIMER_BY_32K 0x03 /* clock divided by 32k */
249 /****************** ****************** *******************/
253 /* #include "zfwint.h" */
254 /****************** ****************** *******************/
256 * This file contains the definitions for interfacing with the
257 * Cyclom-Z ZFIRM Firmware.
260 /* General Constant definitions */
262 #define MAX_CHAN 64 /* max number of channels per board */
264 /* firmware id structure (set after boot) */
266 #define ID_ADDRESS 0x00000180L /* signature/pointer address */
267 #define ZFIRM_ID 0x5557465AL /* ZFIRM/U signature */
268 #define ZFIRM_HLT 0x59505B5CL /* ZFIRM needs external power supply */
269 #define ZFIRM_RST 0x56040674L /* RST signal (due to FW reset) */
271 #define ZF_TINACT_DEF 1000 /* default inactivity timeout
273 #define ZF_TINACT ZF_TINACT_DEF
276 uclong signature; /* ZFIRM/U signature */
277 uclong zfwctrl_addr; /* pointer to ZFW_CTRL structure */
282 #define C_OS_LINUX 0x00000030 /* generic Linux system */
284 /* channel op_mode */
286 #define C_CH_DISABLE 0x00000000 /* channel is disabled */
287 #define C_CH_TXENABLE 0x00000001 /* channel Tx enabled */
288 #define C_CH_RXENABLE 0x00000002 /* channel Rx enabled */
289 #define C_CH_ENABLE 0x00000003 /* channel Tx/Rx enabled */
290 #define C_CH_LOOPBACK 0x00000004 /* Loopback mode */
292 /* comm_parity - parity */
294 #define C_PR_NONE 0x00000000 /* None */
295 #define C_PR_ODD 0x00000001 /* Odd */
296 #define C_PR_EVEN 0x00000002 /* Even */
297 #define C_PR_MARK 0x00000004 /* Mark */
298 #define C_PR_SPACE 0x00000008 /* Space */
299 #define C_PR_PARITY 0x000000ff
301 #define C_PR_DISCARD 0x00000100 /* discard char with frame/par error */
302 #define C_PR_IGNORE 0x00000200 /* ignore frame/par error */
304 /* comm_data_l - data length and stop bits */
306 #define C_DL_CS5 0x00000001
307 #define C_DL_CS6 0x00000002
308 #define C_DL_CS7 0x00000004
309 #define C_DL_CS8 0x00000008
310 #define C_DL_CS 0x0000000f
311 #define C_DL_1STOP 0x00000010
312 #define C_DL_15STOP 0x00000020
313 #define C_DL_2STOP 0x00000040
314 #define C_DL_STOP 0x000000f0
316 /* interrupt enabling/status */
318 #define C_IN_DISABLE 0x00000000 /* zero, disable interrupts */
319 #define C_IN_TXBEMPTY 0x00000001 /* tx buffer empty */
320 #define C_IN_TXLOWWM 0x00000002 /* tx buffer below LWM */
321 #define C_IN_RXHIWM 0x00000010 /* rx buffer above HWM */
322 #define C_IN_RXNNDT 0x00000020 /* rx no new data timeout */
323 #define C_IN_MDCD 0x00000100 /* modem DCD change */
324 #define C_IN_MDSR 0x00000200 /* modem DSR change */
325 #define C_IN_MRI 0x00000400 /* modem RI change */
326 #define C_IN_MCTS 0x00000800 /* modem CTS change */
327 #define C_IN_RXBRK 0x00001000 /* Break received */
328 #define C_IN_PR_ERROR 0x00002000 /* parity error */
329 #define C_IN_FR_ERROR 0x00004000 /* frame error */
330 #define C_IN_OVR_ERROR 0x00008000 /* overrun error */
331 #define C_IN_RXOFL 0x00010000 /* RX buffer overflow */
332 #define C_IN_IOCTLW 0x00020000 /* I/O control w/ wait */
333 #define C_IN_MRTS 0x00040000 /* modem RTS drop */
334 #define C_IN_ICHAR 0x00080000
338 #define C_FL_OXX 0x00000001 /* output Xon/Xoff flow control */
339 #define C_FL_IXX 0x00000002 /* output Xon/Xoff flow control */
340 #define C_FL_OIXANY 0x00000004 /* output Xon/Xoff (any xon) */
341 #define C_FL_SWFLOW 0x0000000f
345 #define C_FS_TXIDLE 0x00000000 /* no Tx data in the buffer or UART */
346 #define C_FS_SENDING 0x00000001 /* UART is sending data */
347 #define C_FS_SWFLOW 0x00000002 /* Tx is stopped by received Xoff */
349 /* rs_control/rs_status RS-232 signals */
351 #define C_RS_PARAM 0x80000000 /* Indicates presence of parameter in
353 #define C_RS_RTS 0x00000001 /* RTS */
354 #define C_RS_DTR 0x00000004 /* DTR */
355 #define C_RS_DCD 0x00000100 /* CD */
356 #define C_RS_DSR 0x00000200 /* DSR */
357 #define C_RS_RI 0x00000400 /* RI */
358 #define C_RS_CTS 0x00000800 /* CTS */
360 /* commands Host <-> Board */
362 #define C_CM_RESET 0x01 /* reset/flush buffers */
363 #define C_CM_IOCTL 0x02 /* re-read CH_CTRL */
364 #define C_CM_IOCTLW 0x03 /* re-read CH_CTRL, intr when done */
365 #define C_CM_IOCTLM 0x04 /* RS-232 outputs change */
366 #define C_CM_SENDXOFF 0x10 /* send Xoff */
367 #define C_CM_SENDXON 0x11 /* send Xon */
368 #define C_CM_CLFLOW 0x12 /* Clear flow control (resume) */
369 #define C_CM_SENDBRK 0x41 /* send break */
370 #define C_CM_INTBACK 0x42 /* Interrupt back */
371 #define C_CM_SET_BREAK 0x43 /* Tx break on */
372 #define C_CM_CLR_BREAK 0x44 /* Tx break off */
373 #define C_CM_CMD_DONE 0x45 /* Previous command done */
374 #define C_CM_INTBACK2 0x46 /* Alternate Interrupt back */
375 #define C_CM_TINACT 0x51 /* set inactivity detection */
376 #define C_CM_IRQ_ENBL 0x52 /* enable generation of interrupts */
377 #define C_CM_IRQ_DSBL 0x53 /* disable generation of interrupts */
378 #define C_CM_ACK_ENBL 0x54 /* enable acknowledged interrupt mode */
379 #define C_CM_ACK_DSBL 0x55 /* disable acknowledged intr mode */
380 #define C_CM_FLUSH_RX 0x56 /* flushes Rx buffer */
381 #define C_CM_FLUSH_TX 0x57 /* flushes Tx buffer */
382 #define C_CM_Q_ENABLE 0x58 /* enables queue access from the
384 #define C_CM_Q_DISABLE 0x59 /* disables queue access from the
387 #define C_CM_TXBEMPTY 0x60 /* Tx buffer is empty */
388 #define C_CM_TXLOWWM 0x61 /* Tx buffer low water mark */
389 #define C_CM_RXHIWM 0x62 /* Rx buffer high water mark */
390 #define C_CM_RXNNDT 0x63 /* rx no new data timeout */
391 #define C_CM_TXFEMPTY 0x64
392 #define C_CM_ICHAR 0x65
393 #define C_CM_MDCD 0x70 /* modem DCD change */
394 #define C_CM_MDSR 0x71 /* modem DSR change */
395 #define C_CM_MRI 0x72 /* modem RI change */
396 #define C_CM_MCTS 0x73 /* modem CTS change */
397 #define C_CM_MRTS 0x74 /* modem RTS drop */
398 #define C_CM_RXBRK 0x84 /* Break received */
399 #define C_CM_PR_ERROR 0x85 /* Parity error */
400 #define C_CM_FR_ERROR 0x86 /* Frame error */
401 #define C_CM_OVR_ERROR 0x87 /* Overrun error */
402 #define C_CM_RXOFL 0x88 /* RX buffer overflow */
403 #define C_CM_CMDERROR 0x90 /* command error */
404 #define C_CM_FATAL 0x91 /* fatal error */
405 #define C_CM_HW_RESET 0x92 /* reset board */
408 * CH_CTRL - This per port structure contains all parameters
409 * that control an specific port. It can be seen as the
410 * configuration registers of a "super-serial-controller".
414 uclong op_mode; /* operation mode */
415 uclong intr_enable; /* interrupt masking */
416 uclong sw_flow; /* SW flow control */
417 uclong flow_status; /* output flow status */
418 uclong comm_baud; /* baud rate - numerically specified */
419 uclong comm_parity; /* parity */
420 uclong comm_data_l; /* data length/stop */
421 uclong comm_flags; /* other flags */
422 uclong hw_flow; /* HW flow control */
423 uclong rs_control; /* RS-232 outputs */
424 uclong rs_status; /* RS-232 inputs */
425 uclong flow_xon; /* xon char */
426 uclong flow_xoff; /* xoff char */
427 uclong hw_overflow; /* hw overflow counter */
428 uclong sw_overflow; /* sw overflow counter */
429 uclong comm_error; /* frame/parity error counter */
436 * BUF_CTRL - This per channel structure contains
437 * all Tx and Rx buffer control for a given channel.
441 uclong flag_dma; /* buffers are in Host memory */
442 uclong tx_bufaddr; /* address of the tx buffer */
443 uclong tx_bufsize; /* tx buffer size */
444 uclong tx_threshold; /* tx low water mark */
445 uclong tx_get; /* tail index tx buf */
446 uclong tx_put; /* head index tx buf */
447 uclong rx_bufaddr; /* address of the rx buffer */
448 uclong rx_bufsize; /* rx buffer size */
449 uclong rx_threshold; /* rx high water mark */
450 uclong rx_get; /* tail index rx buf */
451 uclong rx_put; /* head index rx buf */
452 uclong filler[5]; /* filler to align structures */
456 * BOARD_CTRL - This per board structure contains all global
457 * control fields related to the board.
462 /* static info provided by the on-board CPU */
463 uclong n_channel; /* number of channels */
464 uclong fw_version; /* firmware version */
466 /* static info provided by the driver */
467 uclong op_system; /* op_system id */
468 uclong dr_version; /* driver version */
470 /* board control area */
471 uclong inactivity; /* inactivity control */
473 /* host to FW commands */
474 uclong hcmd_channel; /* channel number */
475 uclong hcmd_param; /* pointer to parameters */
477 /* FW to Host commands */
478 uclong fwcmd_channel; /* channel number */
479 uclong fwcmd_param; /* pointer to parameters */
480 uclong zf_int_queue_addr; /* offset for INT_QUEUE structure */
482 /* filler so the structures are aligned */
486 /* Host Interrupt Queue */
488 #define QUEUE_SIZE (10*MAX_CHAN)
491 unsigned char intr_code[QUEUE_SIZE];
492 unsigned long channel[QUEUE_SIZE];
493 unsigned long param[QUEUE_SIZE];
499 * ZFW_CTRL - This is the data structure that includes all other
500 * data structures used by the Firmware.
504 struct BOARD_CTRL board_ctrl;
505 struct CH_CTRL ch_ctrl[MAX_CHAN];
506 struct BUF_CTRL buf_ctrl[MAX_CHAN];
509 /****************** ****************** *******************/
512 /* Per card data structure */
514 struct cyclades_card {
515 unsigned long base_phys;
516 unsigned long ctl_phys;
517 unsigned long base_addr;
518 unsigned long ctl_addr;
520 int num_chips; /* 0 if card absent, -1 if Z/PCI, else Y */
521 int first_line; /* minor number of first channel on card */
522 int nports; /* Number of ports in the card */
523 int bus_index; /* address shift - 0 for ISA, 1 for PCI */
524 int intr_enabled; /* FW Interrupt flag - 0 disabled, 1 enabled */
525 struct pci_dev *pdev;
527 spinlock_t card_lock;
529 unsigned long filler;
533 struct cyclades_chip {
540 /***************************************
541 * Memory access functions/macros *
542 * (required to support Alpha systems) *
543 ***************************************/
545 #define cy_writeb(port,val) {writeb((ucchar)(val),(ulong)(port)); mb();}
546 #define cy_writew(port,val) {writew((ushort)(val),(ulong)(port)); mb();}
547 #define cy_writel(port,val) {writel((uclong)(val),(ulong)(port)); mb();}
549 #define cy_readb(port) readb(port)
550 #define cy_readw(port) readw(port)
551 #define cy_readl(port) readl(port)
554 * Statistics counters
556 struct cyclades_icount {
557 __u32 cts, dsr, rng, dcd, tx, rx;
558 __u32 frame, parity, overrun, brk;
563 * This is our internal structure for each serial port's state.
565 * Many fields are paralleled by the structure used by the serial_struct
568 * For definitions of the flags field, see tty.h
571 struct cyclades_port {
575 int flags; /* defined in tty.h */
576 int type; /* UART type */
577 struct tty_struct *tty;
578 int read_status_mask;
579 int ignore_status_mask;
582 int cor1,cor2,cor3,cor4,cor5;
583 int tbpr,tco,rbpr,rco;
589 int x_char; /* to be pushed out ASAP */
591 unsigned short closing_wait;
593 unsigned long last_active;
594 int count; /* # of fd on device */
597 int blocked_open; /* # of blocked opens */
598 unsigned char *xmit_buf;
602 int default_threshold;
604 unsigned long jiffies[3];
605 unsigned long rflush_count;
606 struct cyclades_monitor mon;
607 struct cyclades_idle_stats idle_stats;
608 struct cyclades_icount icount;
609 struct work_struct tqueue;
610 wait_queue_head_t open_wait;
611 wait_queue_head_t close_wait;
612 wait_queue_head_t shutdown_wait;
613 wait_queue_head_t delta_msr_wait;
618 * Events are used to schedule things to happen at timer-interrupt
619 * time, instead of at cy interrupt time.
621 #define Cy_EVENT_READ_PROCESS 0
622 #define Cy_EVENT_WRITE_WAKEUP 1
623 #define Cy_EVENT_HANGUP 2
624 #define Cy_EVENT_BREAK 3
625 #define Cy_EVENT_OPEN_WAKEUP 4
626 #define Cy_EVENT_SHUTDOWN_WAKEUP 5
627 #define Cy_EVENT_DELTA_WAKEUP 6
628 #define Cy_EVENT_Z_RX_FULL 7
630 #define CLOSING_WAIT_DELAY 30*HZ
631 #define CY_CLOSING_WAIT_NONE 65535
632 #define CY_CLOSING_WAIT_INF 0
635 #define CyMAX_CHIPS_PER_CARD 8
636 #define CyMAX_CHAR_FIFO 12
637 #define CyPORTS_PER_CHIP 4
638 #define CD1400_MAX_SPEED 115200
640 #define CyISA_Ywin 0x2000
642 #define CyPCI_Ywin 0x4000
643 #define CyPCI_Yctl 0x80
644 #define CyPCI_Zctl CTRL_WINDOW_SIZE
645 #define CyPCI_Zwin 0x80000
646 #define CyPCI_Ze_win (2 * CyPCI_Zwin)
648 #define PCI_DEVICE_ID_MASK 0x06
650 /**** CD1400 registers ****/
652 #define CD1400_REV_G 0x46
653 #define CD1400_REV_J 0x48
655 #define CyRegSize 0x0400
656 #define Cy_HwReset 0x1400
657 #define Cy_ClrIntr 0x1800
658 #define Cy_EpldRev 0x1e00
660 /* Global Registers */
662 #define CyGFRCR (0x40*2)
664 #define CyCAR (0x68*2)
665 #define CyCHAN_0 (0x00)
666 #define CyCHAN_1 (0x01)
667 #define CyCHAN_2 (0x02)
668 #define CyCHAN_3 (0x03)
669 #define CyGCR (0x4B*2)
670 #define CyCH0_SERIAL (0x00)
671 #define CyCH0_PARALLEL (0x80)
672 #define CySVRR (0x67*2)
673 #define CySRModem (0x04)
674 #define CySRTransmit (0x02)
675 #define CySRReceive (0x01)
676 #define CyRICR (0x44*2)
677 #define CyTICR (0x45*2)
678 #define CyMICR (0x46*2)
679 #define CyICR0 (0x00)
680 #define CyICR1 (0x01)
681 #define CyICR2 (0x02)
682 #define CyICR3 (0x03)
683 #define CyRIR (0x6B*2)
684 #define CyTIR (0x6A*2)
685 #define CyMIR (0x69*2)
686 #define CyIRDirEq (0x80)
687 #define CyIRBusy (0x40)
688 #define CyIRUnfair (0x20)
689 #define CyIRContext (0x1C)
690 #define CyIRChannel (0x03)
691 #define CyPPR (0x7E*2)
692 #define CyCLOCK_20_1MS (0x27)
693 #define CyCLOCK_25_1MS (0x31)
694 #define CyCLOCK_25_5MS (0xf4)
695 #define CyCLOCK_60_1MS (0x75)
696 #define CyCLOCK_60_2MS (0xea)
698 /* Virtual Registers */
700 #define CyRIVR (0x43*2)
701 #define CyTIVR (0x42*2)
702 #define CyMIVR (0x41*2)
703 #define CyIVRMask (0x07)
704 #define CyIVRRxEx (0x07)
705 #define CyIVRRxOK (0x03)
706 #define CyIVRTxOK (0x02)
707 #define CyIVRMdmOK (0x01)
708 #define CyTDR (0x63*2)
709 #define CyRDSR (0x62*2)
710 #define CyTIMEOUT (0x80)
711 #define CySPECHAR (0x70)
712 #define CyBREAK (0x08)
713 #define CyPARITY (0x04)
714 #define CyFRAME (0x02)
715 #define CyOVERRUN (0x01)
716 #define CyMISR (0x4C*2)
717 /* see CyMCOR_ and CyMSVR_ for bits*/
718 #define CyEOSRR (0x60*2)
720 /* Channel Registers */
722 #define CyLIVR (0x18*2)
723 #define CyMscsr (0x01)
724 #define CyTdsr (0x02)
725 #define CyRgdsr (0x03)
726 #define CyRedsr (0x07)
727 #define CyCCR (0x05*2)
729 #define CyCHAN_RESET (0x80)
730 #define CyCHIP_RESET (0x81)
731 #define CyFlushTransFIFO (0x82)
733 #define CyCOR_CHANGE (0x40)
734 #define CyCOR1ch (0x02)
735 #define CyCOR2ch (0x04)
736 #define CyCOR3ch (0x08)
738 #define CySEND_SPEC_1 (0x21)
739 #define CySEND_SPEC_2 (0x22)
740 #define CySEND_SPEC_3 (0x23)
741 #define CySEND_SPEC_4 (0x24)
743 #define CyCHAN_CTL (0x10)
744 #define CyDIS_RCVR (0x01)
745 #define CyENB_RCVR (0x02)
746 #define CyDIS_XMTR (0x04)
747 #define CyENB_XMTR (0x08)
748 #define CySRER (0x06*2)
749 #define CyMdmCh (0x80)
750 #define CyRxData (0x10)
751 #define CyTxRdy (0x04)
752 #define CyTxMpty (0x02)
753 #define CyNNDT (0x01)
754 #define CyCOR1 (0x08*2)
755 #define CyPARITY_NONE (0x00)
756 #define CyPARITY_0 (0x20)
757 #define CyPARITY_1 (0xA0)
758 #define CyPARITY_E (0x40)
759 #define CyPARITY_O (0xC0)
760 #define Cy_1_STOP (0x00)
761 #define Cy_1_5_STOP (0x04)
762 #define Cy_2_STOP (0x08)
763 #define Cy_5_BITS (0x00)
764 #define Cy_6_BITS (0x01)
765 #define Cy_7_BITS (0x02)
766 #define Cy_8_BITS (0x03)
767 #define CyCOR2 (0x09*2)
769 #define CyTxIBE (0x40)
771 #define CyAUTO_TXFL (0x60)
774 #define CyRtsAO (0x04)
775 #define CyCtsAE (0x02)
776 #define CyDsrAE (0x01)
777 #define CyCOR3 (0x0A*2)
778 #define CySPL_CH_DRANGE (0x80) /* special character detect range */
779 #define CySPL_CH_DET1 (0x40) /* enable special character detection
781 #define CyFL_CTRL_TRNSP (0x20) /* Flow Control Transparency */
782 #define CySPL_CH_DET2 (0x10) /* Enable special character detection
784 #define CyREC_FIFO (0x0F) /* Receive FIFO threshold */
785 #define CyCOR4 (0x1E*2)
786 #define CyCOR5 (0x1F*2)
787 #define CyCCSR (0x0B*2)
788 #define CyRxEN (0x80)
789 #define CyRxFloff (0x40)
790 #define CyRxFlon (0x20)
791 #define CyTxEN (0x08)
792 #define CyTxFloff (0x04)
793 #define CyTxFlon (0x02)
794 #define CyRDCR (0x0E*2)
795 #define CySCHR1 (0x1A*2)
796 #define CySCHR2 (0x1B*2)
797 #define CySCHR3 (0x1C*2)
798 #define CySCHR4 (0x1D*2)
799 #define CySCRL (0x22*2)
800 #define CySCRH (0x23*2)
801 #define CyLNC (0x24*2)
802 #define CyMCOR1 (0x15*2)
803 #define CyMCOR2 (0x16*2)
804 #define CyRTPR (0x21*2)
805 #define CyMSVR1 (0x6C*2)
806 #define CyMSVR2 (0x6D*2)
807 #define CyANY_DELTA (0xF0)
814 #define CyPVSR (0x6F*2)
815 #define CyRBPR (0x78*2)
816 #define CyRCOR (0x7C*2)
817 #define CyTBPR (0x72*2)
818 #define CyTCOR (0x76*2)
820 /* Custom Registers */
822 #define CyPLX_VER (0x3400)
823 #define PLX_9050 0x0b
824 #define PLX_9060 0x0c
825 #define PLX_9080 0x0d
827 /***************************************************************************/
829 #endif /* __KERNEL__ */
830 #endif /* _LINUX_CYCLADES_H */