--- /dev/null
+/*===========================================================================
+
+ NV_INFO_TAB.C
+
+DESCRIPTION
+ This file is generated by NVC and contains NV Items table.
+
+ $Header: //source/qcom/qct/core/pkg/2H09/halcyon_modem/rel/LA2.0/AMSS/products/7x30/core/services/nv/src/nv_info_tab.c#1 $
+ Copyright (c) 2006 by QUALCOMM Incorporated. All Rights Reserved.
+===========================================================================*/
+
+/* NVC Version: 2.0.0 */
+
+/* Include Files */
+#include "comdef.h"
+#include "nvi.h"
+#include "nvim.h"
+#include "nvim_items.h"
+
+const nvim_item_info_type nvim_item_info_table[] = {
+ { sizeof(dword), 0, 1},
+ { sizeof(dword), 0, 1},
+ { sizeof(byte), 0, 1},
+ { sizeof(byte), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_config_chksum_type), 0, 1},
+ { sizeof(nvi_pref_mode_type), 2, 1},
+ { sizeof(nvi_pref_serv_type), 2, 1},
+ { sizeof(nvi_pref_serv_type), 2, 1},
+ { sizeof(nvi_sid_lock_type), 2, 1},
+ { sizeof(nvi_sid_acq_type), 2, 1},
+ { sizeof(nvi_sid_lock_type), 2, 1},
+ { sizeof(nvi_sid_acq_type), 2, 1},
+ { sizeof(nvi_firstchp_type), 2, 1},
+ { sizeof(nvi_sid_type), 2, 1},
+ { sizeof(nvi_analog_reg_type), 2, 1},
+ { sizeof(nvi_cdmach_type), 2, 1},
+ { sizeof(nvi_cdmach_type), 2, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_word_type), 2, 1},
+ { sizeof(nvi_a_key_type), 2, 1},
+ { sizeof(nvi_a_key_chksum_type), 2, 1},
+ { sizeof(nvi_ssd_type), 2, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_ssd_type), 2, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_count_type), 2, 1},
+ { sizeof(nvi_min1_type), 2, 1},
+ { sizeof(nvi_min2_type), 2, 1},
+ { sizeof(nvi_mob_term_type), 2, 1},
+ { sizeof(nvi_mob_term_type), 2, 1},
+ { sizeof(nvi_mob_term_type), 2, 1},
+ { sizeof(nvi_accolc_type), 2, 1},
+ { sizeof(nvi_sid_nid_type), 2, 1},
+ { sizeof(nvi_min_chksum_type), 2, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_name_type), 2, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_zone_list_type), 0, 1},
+ { sizeof(nvi_sid_nid_list_type), 0, 1},
+ { sizeof(nvi_dist_reg_type), 0, 1},
+ { sizeof(nvi_cdmach_type), 2, 1},
+ { sizeof(nvi_call_time_type), 2, 1},
+ { sizeof(nvi_call_time_type), 2, 1},
+ { sizeof(nvi_call_time_type), 2, 1},
+ { sizeof(nvi_call_time_type), 2, 1},
+ { sizeof(nvi_run_time_type), 0, 1},
+ { sizeof(nvi_dial_type), 110, 1},
+ { sizeof(nvi_stdial_type), 20, 1},
+ { sizeof(nvi_stack_idx_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_name_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_auto_answer_type), 0, 1},
+ { sizeof(nvi_auto_redial_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_maintrsn_type), 0, 1},
+ { sizeof(nvi_lckrsn_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_lock_code_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_sec_code_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_err_log_type), 20, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_fm_tx_pwr_type), 0, 1},
+ { sizeof(nvi_fr_temp_offset_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_fact_info_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pwr_table_type), 0, 1},
+ { sizeof(nvi_freq_table_type), 0, 1},
+ { sizeof(nvi_temp_table_type), 0, 1},
+ { sizeof(nvi_pwr_table_type), 0, 1},
+ { sizeof(nvi_pwr_table_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_cdma_rx_lin_slp_type), 0, 1},
+ { sizeof(nvi_freq_int1_table_type), 0, 1},
+ { sizeof(nvi_freq_int1_table_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_cdma_tx_lin_master_slp_type), 0, 1},
+ { sizeof(nvi_temp_table_type), 0, 1},
+ { sizeof(nvi_volt_table_type), 0, 1},
+ { sizeof(nvi_temp_table_type), 0, 1},
+ { sizeof(nvi_volt_table_type), 0, 1},
+ { sizeof(nvi_freq_table_type), 0, 1},
+ { sizeof(nvi_cdma_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_cdma_err_slp_vs_hdet_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_fm_agc_adj_vs_freq_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_call_cnt_type), 2, 1},
+ { sizeof(nvi_call_cnt_type), 2, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_imsi_mcc_type), 2, 1},
+ { sizeof(nvi_imsi_11_12_type), 2, 1},
+ { sizeof(nvi_dir_number_type), 2, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_fsc_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_run_time_type), 0, 1},
+ { sizeof(nvi_run_time_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_fsc2_type), 0, 1},
+ { sizeof(nvi_fsc2_chksum_type), 0, 1},
+ { sizeof(nvi_wdc_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_temp_int1_table_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_temp_int1_table_type), 0, 1},
+ { sizeof(nvi_temp_int1_table_type), 0, 1},
+ { sizeof(nvi_temp_int1_table_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_temp_table_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_imsi_addr_num_type), 2, 1},
+ { sizeof(nvi_tmsi_zone_length_type), 2, 1},
+ { sizeof(nvi_tmsi_zone_type), 2, 1},
+ { sizeof(nvi_tmsi_code_type), 2, 1},
+ { sizeof(nvi_tmsi_exp_time_type), 2, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_mob_dir_data_type), 2, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_dial_type), 1, 1},
+ { sizeof(nvi_sec_code_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_mru2_table_type), 2, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_up_link_info_type), 2, 1},
+ { sizeof(nvi_up_parms_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_dtaco_control_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_sid_nid_lock_type), 2, 1},
+ { sizeof(nvi_enabled_type), 2, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_sys_pref_type), 2, 1},
+ { sizeof(nvi_home_sid_nid_type), 2, 1},
+ { sizeof(nvi_enabled_type), 2, 1},
+ { sizeof(nvi_enabled_type), 2, 1},
+ { sizeof(nvi_min1_type), 2, 1},
+ { sizeof(nvi_min2_type), 2, 1},
+ { sizeof(nvi_imsi_mcc_type), 2, 1},
+ { sizeof(nvi_imsi_11_12_type), 2, 1},
+ { sizeof(nvi_imsi_addr_num_type), 2, 1},
+ { sizeof(nvi_up_alert_record_type), 9, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_pref_voice_so_type), 2, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_data_pkt_orig_str_type), 0, 1},
+ { sizeof(nvi_up_key_type), 2, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_roam_msg_type), 6, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_ubrowser_type), 32, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_fm_hdet_adc_range_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pn_id_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_user_zone_type), 35, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pap_user_id_type), 0, 1},
+ { sizeof(nvi_pap_password_type), 0, 1},
+ { sizeof(nvi_sta_values_type), 0, 1},
+ { sizeof(nvi_sta_values_type), 0, 1},
+ { sizeof(nvi_sta_values_type), 0, 1},
+ { sizeof(nvi_sta_values_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pcs_rx_lin_slp_type), 0, 1},
+ { sizeof(nvi_pcs_rx_comp_vs_freq_type), 0, 1},
+ { sizeof(nvi_pcs_tx_comp_vs_freq_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_pcs_tx_lin_master_slp_type), 0, 1},
+ { sizeof(nvi_pcs_tx_lin_vs_temp_type), 0, 1},
+ { sizeof(nvi_pcs_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_pcs_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_pcs_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pcs_pdm1_vs_freq_type), 0, 1},
+ { sizeof(nvi_pcs_pdm2_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_pcs_rx_lin_vs_temp_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pcs_pa_range_vs_temp_type), 0, 1},
+ { sizeof(nvi_pcs_pdm1_vs_temp_type), 0, 1},
+ { sizeof(nvi_pcs_pdm2_vs_temp_type), 0, 1},
+ { sizeof(nvi_pcs_rx_slp_vs_temp_type), 0, 1},
+ { sizeof(nvi_pcs_tx_slp_vs_temp_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_pa_offset_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_sms_bc_service_table_type), 128, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_cdma_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_cdma_lna_12_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pcs_cdma_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_pcs_cdma_lna_12_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_minmax_type), 0, 1},
+ { sizeof(nvi_ruim_chv_type), 0, 1},
+ { sizeof(nvi_ruim_chv_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_pa_range_offsets_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_mm_ringer_file_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_ruim_sms_status_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_pcs_pa_range_offsets_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_diag_restart_config_type), 0, 1},
+ { sizeof(nvi_band_pref_type), 2, 1},
+ { sizeof(nvi_roam_pref_type), 2, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_bd_addr_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enabled_type), 2, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
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+ { sizeof(nvi_gsm_locigprs_type), 0, 1},
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+ { sizeof(nvi_ppp_password_type), 0, 1},
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+ { sizeof(nvi_ppp_user_id_type), 0, 1},
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+ { sizeof(nvi_sms_default_template_type), 0, 1},
+ { sizeof(nvi_non_compliance_comment_type), 0, 1},
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+ { sizeof(nvi_c1_cdma_p1_rise_fall_offset_type), 0, 1},
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+ { sizeof(nvi_c1_cdma_vga_gain_offset_vs_freq_type), 0, 1},
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+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_range_map_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_comp_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_comp_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_lin_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_lin_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_slp_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_slp_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_range_map_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gsm_prui_00_type), 0, 1},
+ { sizeof(nvi_gsm_prui_01_type), 0, 1},
+ { sizeof(nvi_gsm_prui_02_type), 0, 1},
+ { sizeof(nvi_gsm_prui_03_type), 0, 1},
+ { sizeof(nvi_gsm_prui_04_type), 0, 1},
+ { sizeof(nvi_gsm_prui_05_type), 0, 1},
+ { sizeof(nvi_gsm_prui_06_type), 0, 1},
+ { sizeof(nvi_gsm_prui_07_type), 0, 1},
+ { sizeof(nvi_gsm_prui_08_type), 0, 1},
+ { sizeof(nvi_gsm_prui_09_type), 0, 1},
+ { sizeof(nvi_gsm_prui_10_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_00_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_01_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_02_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_03_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_04_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_05_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_06_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_07_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_08_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_09_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_10_type), 0, 1},
+ { sizeof(nvi_gsm_prdi_11_type), 0, 1},
+ { sizeof(nvi_dcs_prui_00_type), 0, 1},
+ { sizeof(nvi_dcs_prui_01_type), 0, 1},
+ { sizeof(nvi_dcs_prui_02_type), 0, 1},
+ { sizeof(nvi_dcs_prui_03_type), 0, 1},
+ { sizeof(nvi_dcs_prui_04_type), 0, 1},
+ { sizeof(nvi_dcs_prui_05_type), 0, 1},
+ { sizeof(nvi_dcs_prui_06_type), 0, 1},
+ { sizeof(nvi_dcs_prui_07_type), 0, 1},
+ { sizeof(nvi_dcs_prui_08_type), 0, 1},
+ { sizeof(nvi_dcs_prui_09_type), 0, 1},
+ { sizeof(nvi_dcs_prui_10_type), 0, 1},
+ { sizeof(nvi_dcs_prui_11_type), 0, 1},
+ { sizeof(nvi_dcs_prui_12_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_00_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_01_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_02_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_03_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_04_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_05_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_06_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_07_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_08_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_09_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_10_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_11_type), 0, 1},
+ { sizeof(nvi_dcs_prdi_12_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_00_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_01_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_02_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_03_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_04_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_05_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_06_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_07_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_08_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_09_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_10_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_11_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_02_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_03_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_04_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_05_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_06_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_07_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_09_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_10_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_12_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_brui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_brdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_brui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_brui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_brui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_brdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_brui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_brui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_brui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_brdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_brdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_brdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_c0_tx_freq_comp_type), 0, 1},
+ { sizeof(nvi_dcs_c0_tx_freq_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_c0_tx_freq_comp_type), 0, 1},
+ { sizeof(nvi_gsm_c1_tx_freq_comp_type), 0, 1},
+ { sizeof(nvi_dcs_c1_tx_freq_comp_type), 0, 1},
+ { sizeof(nvi_gsm1900_c1_tx_freq_comp_type), 0, 1},
+ { sizeof(nvi_gsm_enable_tx_freq_comp_vs_pcl_type), 0, 1},
+ { sizeof(nvi_dcs_enable_tx_freq_comp_vs_pcl_type), 0, 1},
+ { sizeof(nvi_gsm_1900_enable_tx_freq_comp_vs_pcl_type), 0, 1},
+ { sizeof(nvi_therm_comp_thresholds_type), 0, 1},
+ { sizeof(nvi_vbatt_comp_thresholds_type), 0, 1},
+ { sizeof(nvi_wcdma_c0_tx_comp_vs_freq_0_type), 0, 1},
+ { sizeof(nvi_wcdma_c0_tx_comp_vs_freq_1_type), 0, 1},
+ { sizeof(nvi_wcdma_c1_tx_comp_vs_freq_0_type), 0, 1},
+ { sizeof(nvi_wcdma_c1_tx_comp_vs_freq_1_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_lim_vs_volt_offset_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tl_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tl_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tl_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tl_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_tm_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_tm_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_tm_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_tm_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vl_th_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vl_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vl_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vm_th_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vm_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vm_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_prui_12_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_vh_th_prdi_12_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_prui_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_prui_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_prui_13_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_prdi_15_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_dcs_vh_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_prui_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_prui_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_prui_13_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_prdi_15_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_prdi_14_type), 0, 1},
+ { sizeof(nvi_gsm_1900_vh_th_prdi_13_type), 0, 1},
+ { sizeof(nvi_factory_data_1_type), 0, 1},
+ { sizeof(nvi_factory_data_2_type), 0, 1},
+ { sizeof(nvi_factory_data_3_type), 0, 1},
+ { sizeof(nvi_factory_data_4_type), 0, 1},
+ { sizeof(nvi_gsm_prui_11_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_00_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_01_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_11_type), 0, 1},
+ { sizeof(nvi_gsm_1900_prdi_08_type), 0, 1},
+ { sizeof(nvi_appx5_pref_type), 0, 1},
+ { sizeof(nvi_wlan_net_sel_mode_pref_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg4_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg5_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg6_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg7_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg8_f1_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg4_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg5_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg6_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg7_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg8_f2_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_gsm_amam_arfcn_type), 0, 1},
+ { sizeof(nvi_dcs_amam_arfcn_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_arfcn_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_arfcn_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_sys_struct_fct_file_name_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_sys_custom_ini_file_name_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_compensate_up_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_compensate_dn_with_dvs_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_compensate_up_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_compensate_dn_with_dvs_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_compensate_up_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_compensate_dn_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_max_pwr_backoff_voltages_type), 0, 1},
+ { sizeof(nvi_wcdma_max_pwr_backoff_volt1_type), 0, 1},
+ { sizeof(nvi_wcdma_max_pwr_backoff_volt2_type), 0, 1},
+ { sizeof(nvi_wcdma_max_pwr_backoff_volt3_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_max_pwr_backoff_voltages_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_max_pwr_backoff_volt1_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_max_pwr_backoff_volt2_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_max_pwr_backoff_volt3_type), 0, 1},
+ { sizeof(nvi_wcdma_800_max_pwr_backoff_voltages_type), 0, 1},
+ { sizeof(nvi_wcdma_800_max_pwr_backoff_volt1_type), 0, 1},
+ { sizeof(nvi_wcdma_800_max_pwr_backoff_volt2_type), 0, 1},
+ { sizeof(nvi_wcdma_800_max_pwr_backoff_volt3_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_amam_dynamic_range), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_amam_dynamic_range), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_amam_dynamic_range), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_amam_dynamic_range), 0, 1},
+ { sizeof(nvi_calpath_rsb_type), 0, 1},
+ { sizeof(nvi_calpath_rsb_type), 0, 1},
+ { sizeof(nvi_calpath_rsb_type), 0, 1},
+ { sizeof(nvi_calpath_rsb_type), 0, 1},
+ { sizeof(nvi_amam_sys_gain_dc_corr), 0, 1},
+ { sizeof(nvi_amam_sys_gain_dc_corr), 0, 1},
+ { sizeof(nvi_amam_sys_gain_dc_corr), 0, 1},
+ { sizeof(nvi_amam_sys_gain_dc_corr), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_c0_bc0_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc0_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c0_bc1_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc1_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c0_bc3_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc3_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c0_bc4_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc4_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c0_bc5_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc5_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c0_bc6_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc6_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_sw_version_info_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_bc0_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc1_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc3_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc4_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc5_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc6_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_device_serial_no_type), 0, 1},
+ { sizeof(nvi_ds_mip_rm_nai_type), 6, 1},
+ { sizeof(nvi_sms_bmc_reading_pref_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uploadmedia_album_addr_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uploadmedia_postcard_addr_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_vs_temp_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_vs_temp_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_slp_vs_temp_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_slp_vs_temp_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_slp_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_slp_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_rfr_vco_coarse_tuning_1800_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_range_map_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_compensate_up_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_compensate_dn_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_max_pwr_backoff_voltages_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_max_pwr_backoff_volt1_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_max_pwr_backoff_volt2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_max_pwr_backoff_volt3_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_ds_sip_rm_nai_type), 0, 1},
+ { sizeof(nvi_band_pref_32_63_type), 3, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_wcdma_utran_tx_lim_vs_temp_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_utran_tx_lim_vs_temp_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_800_utran_tx_lim_vs_temp_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_utran_tx_lim_vs_temp_offset_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_user_greeting_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_ms_sms_opco_types_supported_type), 0, 1},
+ { sizeof(nvi_ms_sms_smsc_address1_type), 0, 1},
+ { sizeof(nvi_ms_sms_smsc_address2_type), 0, 1},
+ { sizeof(nvi_ms_sms_smsc_address3_type), 0, 1},
+ { sizeof(nvi_ms_sms_smsc_address4_type), 0, 1},
+ { sizeof(nvi_ms_sms_smsc_address5_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_poc_server_ip1_type), 0, 1},
+ { sizeof(nvi_poc_server_ip2_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_poc_nai_type), 0, 1},
+ { sizeof(nvi_poc_billing_service_type), 0, 1},
+ { sizeof(nvi_poc_glm_password_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_rf_antsel_umts_1800_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_im_primary_ip_addr_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_im_server_name_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_ext_op_list_entry_name_type), 0, 1},
+ { sizeof(nvi_ext_op_list_entry_plmn_type), 0, 1},
+ { sizeof(nvi_bm_bat_stats_type), 0, 1},
+ { sizeof(nvi_display_language_options_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_input_language_options_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { 0, 0, 0},
+ { sizeof(nvi_gsm_power_levels_type), 0, 1},
+ { sizeof(nvi_dcs_power_levels_type), 0, 1},
+ { sizeof(nvi_gsm_850_power_levels_type), 0, 1},
+ { sizeof(nvi_gsm_1900_power_levels_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_gsm_amam_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_dcs_amam_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_amam_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_amam_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_gsm_ampm_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_dcs_ampm_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_ampm_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg4_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg5_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg6_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg7_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_ampm_master_tbl_seg8_f3_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_autocal_pwr_dac_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_rtr6250_rsb_type), 0, 1},
+ { sizeof(nvi_rtr6250_rsb_type), 0, 1},
+ { sizeof(nvi_rtr6250_rsb_type), 0, 1},
+ { sizeof(nvi_rtr6250_rsb_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_irda_device_name_type), 0, 1},
+ { sizeof(nvi_irda_pnp_device_id_type), 0, 1},
+ { sizeof(nvi_irda_pnp_manufacturer_type), 0, 1},
+ { sizeof(nvi_irda_pnp_name_type), 0, 1},
+ { sizeof(nvi_irda_pnp_device_category_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_im_supported_bearers_type), 0, 1},
+ { sizeof(nvi_im_supported_cir_methods_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_im_password_type), 0, 1},
+ { sizeof(nvi_im_cir_port_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_im_smsc_address_type), 0, 1},
+ { sizeof(nvi_im_optional_header_type), 0, 1},
+ { sizeof(nvi_im_digest_schemas_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_im_userid_type), 0, 1},
+ { sizeof(nvi_bc0_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc1_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc3_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc4_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc5_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc6_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_im_start_string_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_c0_bc0_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_c0_bc1_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_c0_bc3_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_c0_bc4_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_c0_bc5_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_c0_bc6_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rfr_vco_coarse_tuning_800_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_presupl_wap_gateway_address_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_poc_wtuser_password_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_browser_jump_portal_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk1_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk2_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk3_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk4_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk5_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk6_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk7_name_type), 0, 1},
+ { sizeof(nvi_browser_jump_embdlnk8_name_type), 0, 1},
+ { sizeof(nvi_voice_mail_line1_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_voice_mail_line2_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_wcdma_c0_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_sos_number_type), 0, 1},
+ { sizeof(nvi_wap_trusted_domain_type), 0, 1},
+ { sizeof(nvi_wap_push_autoload_type), 0, 1},
+ { sizeof(nvi_im_server_address_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_gsm_polar_ramp_profile_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_mf_700_agc_vs_freq_type), 0, 1},
+ { sizeof(nvi_mf_700_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_mf_afc_loop_params_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_sectime_offsets_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
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+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_2100_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_2100_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_2100_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_2100_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_rf_antsel_umts_2100_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_rf_antsel_umts_1900_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_rf_antsel_umts_800_type), 0, 1},
+ { sizeof(nvi_rfr_vco_coarse_tune_2_1900_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { sizeof(nvi_bc11_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_bc11_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_bc11_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_bc11_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_bc11_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_c0_bc11_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bc11_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bc11_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc11_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc11_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc11_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_c0_bc11_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_c1_bc11_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bc11_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bc11_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc11_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc11_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc11_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_c1_bc11_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_bc11_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc11_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_c0_bc11_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc11_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_bc11_ant_quality_type), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_c0_bc11_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_c0_bc11_intelliceiver_det_thresh_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_c1_bc11_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_comp_up_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_comp_down_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_comp_up_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_comp_down_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_comp_up_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_pa_comp_down_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_comp_up_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_comp_down_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_comp_up_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_comp_down_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_comp_up_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_800_pa_comp_down_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_comp_up_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_comp_down_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_comp_up_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_comp_down_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_comp_up_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_pa_comp_down_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_900_pa_comp_up_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_900_pa_comp_down_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_900_pa_comp_up_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_900_pa_comp_down_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_900_pa_comp_up_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_900_pa_comp_down_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_comp_up_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_comp_down_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_comp_up_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_comp_down_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_comp_up_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_pa_comp_down_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_0_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_1_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_vs_temp_0_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_vs_temp_1_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_slp_vs_temp_0_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_slp_vs_temp_1_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_slp_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_slp_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_pa_range_map_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_utran_tx_lim_vs_temp_offset_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_pa_compensate_up_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_pa_compensate_dn_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_max_pwr_backoff_voltages_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_max_pwr_backoff_volt1_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_max_pwr_backoff_volt2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_max_pwr_backoff_volt3_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_rfr_vco_coarse_tuning_bc4_type), 0, 1},
+ { sizeof(nvi_rf_antsel_umts_900_type), 0, 1},
+ { sizeof(nvi_rf_antsel_umts_bc4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_roam_ind_custom_home_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_mf_chan_support_type), 0, 1},
+ { sizeof(nvi_mf_rf_path_config_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_freq_0_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_freq_1_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_lock_code_ext_type), 0, 1},
+ { sizeof(nvi_wcdma_iaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_qaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_iaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_qaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_iaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_qaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_iaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_qaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_800_iaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_800_qaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_900_iaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_900_qaccum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_gsm_im2_type), 0, 1},
+ { sizeof(nvi_gsm_im2_type), 0, 1},
+ { sizeof(nvi_gsm_im2_type), 0, 1},
+ { sizeof(nvi_gsm_im2_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_tx_rsb_corr_type), 0, 1},
+ { sizeof(nvi_tx_rsb_corr_type), 0, 1},
+ { sizeof(nvi_tx_rsb_corr_type), 0, 1},
+ { sizeof(nvi_tx_rsb_corr_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_sec_csprng_init_seed_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_lock_code_ext_digits_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_hdridle_desired_slotted_mode_config), 0, 1},
+ { sizeof(nvi_wcdma_1800_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_wcdma_800_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_wcdma_900_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_gps_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uim_config_params_type), 0, 1},
+ { sizeof(nvi_hdrscmdb_secure_config_type), 0, 1},
+ { sizeof(nvi_hdramp_location_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_xo_trim_vals_type), 0, 1},
+ { sizeof(nvi_gsm_path_delay_comp_freq_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_850_path_delay_comp_freq_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_path_delay_cold_temp_vs_freq_type), 0, 1},
+ { sizeof(nvi_gsm_path_delay_room_temp_vs_freq_type), 0, 1},
+ { sizeof(nvi_gsm_path_delay_hot_temp_vs_freq_type), 0, 1},
+ { sizeof(nvi_gsm_850_path_delay_cold_temp_vs_freq_type), 0, 1},
+ { sizeof(nvi_gsm_850_path_delay_room_temp_vs_freq_type), 0, 1},
+ { sizeof(nvi_gsm_850_path_delay_hot_temp_vs_freq_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_hdrl1_dbg_msk_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_bus_prof_ebi1_mode_type), 0, 1},
+ { sizeof(nvi_bus_prof_smi_mode_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_wlan_bss_type_pref), 2, 1},
+ { sizeof(nvi_hdridle_pref_slotted_mode_config_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint64_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_bc15_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_bc15_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_bc15_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_bc15_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_bc15_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc15_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc15_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_c0_bc15_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bc15_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bc15_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c0_bc15_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc15_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc15_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc15_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c0_bc15_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_c1_bc15_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bc15_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bc15_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc15_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc15_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc15_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_bc15_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_c1_bc15_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_bc15_ant_quality_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_c0_bc15_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_c0_bc15_intelliceiver_det_thresh_type), 0, 1},
+ { sizeof(nvi_c1_bc15_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_gpsone_password_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gsm_850_pa_temp_comp_max_pwr_type), 0, 1},
+ { sizeof(nvi_gsm_pa_temp_comp_max_pwr_type), 0, 1},
+ { sizeof(nvi_dcs_pa_temp_comp_max_pwr_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pa_temp_comp_max_pwr_type), 0, 1},
+ { sizeof(nvi_gsm_rssi_temp_values_type), 0, 1},
+ { sizeof(nvi_gsm_850_rx_gain_range_1_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_rx_gain_range_1_temp_comp_type), 0, 1},
+ { sizeof(nvi_dcs_rx_gain_range_1_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rx_gain_range_1_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_rx_gain_range_2_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_rx_gain_range_2_temp_comp_type), 0, 1},
+ { sizeof(nvi_dcs_rx_gain_range_2_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rx_gain_range_2_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_rx_gain_range_3_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_rx_gain_range_3_temp_comp_type), 0, 1},
+ { sizeof(nvi_dcs_rx_gain_range_3_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rx_gain_range_3_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_rx_gain_range_4_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_rx_gain_range_4_temp_comp_type), 0, 1},
+ { sizeof(nvi_dcs_rx_gain_range_4_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rx_gain_range_4_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_rx_gain_range_5_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_rx_gain_range_5_temp_comp_type), 0, 1},
+ { sizeof(nvi_dcs_rx_gain_range_5_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rx_gain_range_5_temp_comp_type), 0, 1},
+ { sizeof(nvi_dcvsapps_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_800_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_900_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_ipv6_priv_addr_config), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_mf_pref_rf_chan_list_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_sms_bearer_prefs_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_aagps_xtra_primary_server_url_type), 0, 1},
+ { sizeof(nvi_aagps_xtra_secondary_server_url_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_aagps_xtra_tertiary_server_url_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_aagps_xtra_primary_sntp_server_url_type), 0, 1},
+ { sizeof(nvi_aagps_xtra_secondary_sntp_server_url_type), 0, 1},
+ { sizeof(nvi_aagps_xtra_tertiary_sntp_server_url_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_aagps_ipc_dm_thread_mask_type), 0, 1},
+ { sizeof(nvi_mf_rf_override_desc), 0, 1},
+ { sizeof(nvi_mf_dmtt_params), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint64_type), 0, 1},
+ { sizeof(nvi_word_type), 0, 1},
+ { 0, 0, 0},
+ { sizeof(nvi_bcx_block_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_bcx_block_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_dword_type), 0, 1},
+ { sizeof(nvi_bcx_block_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_bcx_block_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int2_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_int1_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_byte_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_gps1_xtra_primary_server_url_type), 0, 1},
+ { sizeof(nvi_gps1_xtra_secondary_server_url_type), 0, 1},
+ { sizeof(nvi_gps1_xtra_tertiary_server_url_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_vci_parameters_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_wlan_mac_address_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_dvbh_uhf_freq_band_range_type), 0, 1},
+ { sizeof(nvi_dvbh_vhf_freq_band_range_type), 0, 1},
+ { sizeof(nvi_dvbh_l_freq_band_range_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_dvbh_platform_nw_id_list_type), 0, 1},
+ { sizeof(nvi_http_proxy_server_addr_type), 0, 1},
+ { sizeof(nvi_http_proxy_server_addr_alt_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_cgps_1x_pde_server_addr_ipv6_type), 0, 1},
+ { sizeof(nvi_cgps_1x_pde_server_addr_url_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_cgps_1x_mpc_server_addr_ipv6_type), 0, 1},
+ { sizeof(nvi_cgps_1x_mpc_server_addr_url_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_cgps_umts_pde_server_addr_ipv6_type), 0, 1},
+ { sizeof(nvi_cgps_umts_pde_server_addr_url_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_freq_5_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc0_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc1_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc3_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc4_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc5_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc6_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc11_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc14_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc15_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc0_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc0_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc0_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc0_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc1_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc1_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc1_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc1_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc3_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc3_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc3_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc3_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc4_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc4_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc4_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc4_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc5_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc5_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc5_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc5_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc6_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc6_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc6_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc6_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc11_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc11_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc11_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc11_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc14_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc14_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc14_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc14_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_bc15_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc15_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc15_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc15_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_gsm_carrier_suppression_type), 0, 1},
+ { sizeof(nvi_gsm_850_carrier_suppression_type), 0, 1},
+ { sizeof(nvi_gsm_dcs_carrier_suppression_type), 0, 1},
+ { sizeof(nvi_gsm_1900_carrier_suppression_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_hdrsrch_dbg_msk_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_cal_freq_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_gs0_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_gs1_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_gs2_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_gs3_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_gs4_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_gs5_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_mflo_cal_freq_type), 0, 1},
+ { sizeof(nvi_mbp_rf_mflo_gs0_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_mflo_gs1_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_mflo_gs2_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_mflo_gs3_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_mflo_gs4_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_mflo_gs5_cal_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_nd_config_items), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_dvbh_uhf_band_freq_range_and_offset_1_type), 0, 1},
+ { sizeof(nvi_dvbh_uhf_band_freq_range_and_offset_2_type), 0, 1},
+ { sizeof(nvi_dvbh_cell_id_range_type), 0, 1},
+ { sizeof(nvi_jcdma_ruimid), 0, 1},
+ { sizeof(nvi_jcdma_uim_lock_data), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_gps1_xtra_primary_sntp_server_url_type), 0, 1},
+ { sizeof(nvi_gps1_xtra_secondary_sntp_server_url_type), 0, 1},
+ { sizeof(nvi_gps1_xtra_tertiary_sntp_server_url_type), 0, 1},
+ { sizeof(nvi_mf_proxy_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_rel6_tx_beta_scaling_comp_type), 0, 1},
+ { sizeof(nvi_wcdma_rel6_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_rel6_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_rel6_tx_beta_scaling_comp_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_rel6_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_rel6_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_wcdma_800_rel6_tx_beta_scaling_comp_type), 0, 1},
+ { sizeof(nvi_wcdma_800_rel6_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_800_rel6_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_rel6_tx_beta_scaling_comp_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_rel6_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_rel6_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_xo_cal_field_data_type), 0, 1},
+ { sizeof(nvi_xo_cal_fac_data_type), 0, 1},
+ { sizeof(nvi_xo_cal_ft_conv_type), 0, 1},
+ { sizeof(nvi_wcdma_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_usr_sid_to_mcc_assoc_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_ds_at_v250_registers_type), 0, 1},
+ { sizeof(nvi_ds_at_s_registers_type), 0, 1},
+ { sizeof(nvi_process_restart_switch_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_comp_vs_freq_0_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_comp_vs_freq_1_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_comp_vs_freq_2_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_comp_vs_freq_3_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_tx_comp_vs_freq_sec_pdm_list_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_comp_vs_freq_0_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_comp_vs_freq_1_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_comp_vs_freq_2_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_comp_vs_freq_3_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_comp_vs_freq_sec_pdm_list_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_comp_vs_freq_0_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_comp_vs_freq_1_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_comp_vs_freq_2_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_comp_vs_freq_3_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_comp_vs_freq_sec_pdm_list_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_0_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_1_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_2_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_3_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_comp_vs_freq_sec_pdm_list_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_0_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_1_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_2_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_3_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_comp_vs_freq_sec_pdm_list_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_comp_vs_freq_0_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_comp_vs_freq_1_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_comp_vs_freq_2_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_comp_vs_freq_3_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_comp_vs_freq_sec_pdm_list_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_therm_bins_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_web_info_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_phone_boot_naiurl_type), 0, 1},
+ { sizeof(nvi_phone_boot_url_type), 0, 1},
+ { sizeof(nvi_ds_phone_rdf_url_type), 0, 1},
+ { sizeof(nvi_browser_domain_trusted_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint64_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_nmea_config_info_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_lin_master_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_lin_master_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_master_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_master_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_lin_master_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_tx_lin_master_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_pdm_lin_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_pdm_lin_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_pdm_lin_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_pdm_lin_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_pdm_lin_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_tx_pdm_lin_0_enh_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_undp_hsu_vid_pid_type), 0, 1},
+ { sizeof(nvi_undp_hsu_mfgstr_type), 0, 1},
+ { sizeof(nvi_undp_hsu_prodstr_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_00_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_01_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_02_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_03_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_04_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_05_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_06_type), 0, 1},
+ { sizeof(nvi_rr_acq_db_chunk_07_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_gsm_850_smps_pdm_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_900_smps_pdm_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_1800_smps_pdm_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_1900_smps_pdm_tbl_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1900_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_wcdma_800_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_bc4_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_wcdma_900_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_900_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1800_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_bc0_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc1_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc3_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc4_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc5_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc6_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc11_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc14_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc15_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bcx_block_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc0_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc1_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc3_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc4_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc5_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc6_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc11_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc14_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc15_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bcx_block_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc0_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc1_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc3_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc4_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc5_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc6_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc11_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc14_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc15_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bcx_block_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc0_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc1_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc3_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc4_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc5_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc6_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc11_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc14_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc15_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bcx_block_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_ds_at_csas_csca_register), 0, 1},
+ { sizeof(nvi_ds_at_csas_csmp_settings), 0, 1},
+ { sizeof(nvi_ds_at_csas_cscb_settings), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_undp_hsu_vid_pid2_type), 0, 1},
+ { sizeof(nvi_undp_notebook_info_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_bc10_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_bc10_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_bc10_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_bc10_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_bc10_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_bc10_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc10_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc10_ant_quality_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bc10_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bc10_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bc10_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bc10_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bc10_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_c0_bc10_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bc10_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bc10_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c0_bc10_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc10_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc10_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bc10_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c0_bc10_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_c0_bc10_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_c0_bc10_intelliceiver_det_thresh_type), 0, 1},
+ { sizeof(nvi_c1_bc10_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bc10_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bc10_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bc10_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc10_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc10_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bc10_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_bc10_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_c1_bc10_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_kv_cal_chan_type), 0, 1},
+ { sizeof(nvi_kv_cal_chan_type), 0, 1},
+ { sizeof(nvi_kv_cal_chan_type), 0, 1},
+ { sizeof(nvi_kv_cal_chan_type), 0, 1},
+ { sizeof(nvi_wcdma_900_rel6_tx_beta_scaling_comp_type), 0, 1},
+ { sizeof(nvi_wcdma_900_rel6_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_900_rel6_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_rel6_tx_beta_scaling_comp_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_rel6_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_rel6_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_uint64_type), 0, 1},
+ { sizeof(nvi_multi_sec_code_type), 9, 1},
+ { sizeof(nvi_multi_sec_code_type), 9, 1},
+ { sizeof(nvi_multi_otksl_flag_type), 9, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gsm_850_padac_dc_offset_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_900_padac_dc_offset_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_1800_padac_dc_offset_tbl_type), 0, 1},
+ { sizeof(nvi_gsm_1900_padac_dc_offset_tbl_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_hsupa_irq_flow_ctrl_2ms_pdu_size_336_type), 0, 1},
+ { sizeof(nvi_hsupa_irq_flow_ctrl_2ms_pdu_size_656_type), 0, 1},
+ { sizeof(nvi_bc10_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc10_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc10_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bc10_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_gsm_850_kv_vs_temp_type), 0, 1},
+ { sizeof(nvi_gsm_900_kv_vs_temp_type), 0, 1},
+ { sizeof(nvi_gsm_1800_kv_vs_temp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_kv_vs_temp_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_undp_noem_test_type), 0, 1},
+ { sizeof(nvi_gsm_850_linear_pa_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_900_linear_pa_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1800_linear_pa_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_linear_pa_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_850_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_900_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1800_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_gsm_1900_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_process_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_dc_cal_type), 0, 1},
+ { sizeof(nvi_mf_band_class_sp_info_type), 0, 1},
+ { sizeof(nvi_ds_sip_profile_type), 17, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_ds_sip_profile_nai_info_type), 17, 1},
+ { sizeof(nvi_ds_sip_ppp_ss_info_type), 17, 1},
+ { sizeof(nvi_uint64_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_wcdma_800_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_wcdma_900_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_therm_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_850_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_rgi_g3_f3_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_850_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_900_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_1800_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g0_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g1_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g2_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g3_f1_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g0_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g1_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g2_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g3_f2_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g0_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g1_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g2_f3_type), 0, 1},
+ { sizeof(nvi_edge_1900_pmeas_g3_f3_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_esn_me_type), 0, 1},
+ { sizeof(nvi_uint64_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_amam_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_ampm_linear_seg_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_mipv6_gen_user_profile_type), 0, 1},
+ { sizeof(nvi_mipv6_nai_type), 0, 1},
+ { sizeof(nvi_mipv6_nai_type), 0, 1},
+ { sizeof(nvi_mipv6_nai_type), 0, 1},
+ { sizeof(nvi_mipv6_nai_type), 0, 1},
+ { sizeof(nvi_mipv6_nai_type), 0, 1},
+ { sizeof(nvi_mipv6_eap_aka_credential_type), 0, 1},
+ { sizeof(nvi_mipv6_ha_type), 0, 1},
+ { sizeof(nvi_mipv6_hoa_type), 0, 1},
+ { sizeof(nvi_mipv6_primary_dns_type), 0, 1},
+ { sizeof(nvi_mipv6_secondary_dns_type), 0, 1},
+ { sizeof(nvi_mipv6_ipsec_config_type), 0, 1},
+ { sizeof(nvi_mipv6_registration_config_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_mipv6_mn_aaa_shared_secret_type), 0, 1},
+ { sizeof(nvi_mipv6_mn_ha_shared_secret_type), 0, 1},
+ { sizeof(nvi_mipv6_auth_proto_config_type), 0, 1},
+ { sizeof(nvi_bc0_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc1_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc2_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc3_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc4_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc5_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc6_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc7_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc8_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc9_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc10_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc11_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc12_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc13_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc14_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_bc15_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_data_agg_timer_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_iwlan_operator_id_type), 0, 1},
+ { sizeof(nvi_iwlan_realm_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_iwlan_pdif_fqdn_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_sbas_area_node_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_bc0_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc1_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc3_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc4_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc6_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc5_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc10_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc11_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc14_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bc15_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_bcx_hdr_reva_tx_predistort_type), 0, 1},
+ { sizeof(nvi_hdrmrlparda_param_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_hs_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_hs_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_hs_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_wcdma_900_hs_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_wcdma_800_hs_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_hs_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_linearizer_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_tx_comp_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_lna_1_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_lna_2_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_lna_3_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_lna_4_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_hdr_p2_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_hdr_p3_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_bcx_block_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_bcx_block_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_c0_bcx_block_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_bcx_block_ant_quality_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_intelliceiver_det_thresh_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bcx_block_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_bcx_block_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_vco_coarse_tune_table_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_c1_bcx_block_1_rx_cal_chan_lru_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_hdr_p1_rise_fall_off_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_vco_tune_2_type), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_rf_rx_im2_cal), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_intelliceiver_cal_type), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_rf_rx_agc_lpm_switchpoints), 0, 1},
+ { sizeof(nvi_bcx_block_1_ant_quality_type), 0, 1},
+ { sizeof(nvi_c0_bcx_block_1_intelliceiver_det_thresh_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_0_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_1_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_2_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_pdm_3_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_lin_0_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_lin_1_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_lin_2_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_tx_lin_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_tx_pwr_temp_freq_based_comp_type), 0, 1},
+ { sizeof(nvi_lo_cal_type), 0, 1},
+ { sizeof(nvi_im2_cal_type), 0, 1},
+ { sizeof(nvi_bcx_block_1_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_thermal_monitor_thresholds_type), 0, 1},
+ { sizeof(nvi_thermal_monitor_timers_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_thermal_current_monitor_config_type), 0, 1},
+ { sizeof(nvi_thermal_monitor_max_temp_type), 0, 1},
+ { sizeof(nvi_eap_shared_secret_type), 0, 1},
+ { sizeof(nvi_ppp_eap_user_id_type), 0, 1},
+ { sizeof(nvi_ppp_vsncp_config_data_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_wlan_atheros_specific_cfg), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wwwan_config_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_adsp_dyn_clock_voltage_type), 0, 1},
+ { sizeof(nvi_mtpdp_app_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_current_monitor_thresholds_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_cgps_qwip_server_params_type), 0, 1},
+ { sizeof(nvi_cgps_qwip_tile_params_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
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+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_intelliceiver_rc_tune_cal_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_freq_6_type), 0, 1},
+ { sizeof(nvi_mf_chan_support_l_band_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_l_band_freq_0_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_l_band_freq_1_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_l_band_freq_2_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_l_band_freq_3_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_l_band_freq_4_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_l_band_freq_5_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_l_band_freq_6_type), 0, 1},
+ { sizeof(nvi_mf_chan_support_vhf_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_vhf_freq_0_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_vhf_freq_1_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_vhf_freq_2_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_vhf_freq_3_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_vhf_freq_4_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_vhf_freq_5_type), 0, 1},
+ { sizeof(nvi_mf_rssi_cal_vs_vhf_freq_6_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_cal_freq_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_gs0_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_gs1_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_gs2_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_gs3_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_gs4_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_gs5_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_isdbt_gs6_cal_type), 0, 1},
+ { sizeof(nvi_mbp_rf_dvbh_gs6_cal_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uim_iccid_tpl_type), 0, 1},
+ { sizeof(nvi_ehrpd_milenage_op_type), 0, 1},
+ { sizeof(nvi_ehrpd_imsi_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_gsm_850_linear_pa_r0_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_linear_pa_r1_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_linear_pa_r2_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_850_linear_pa_r3_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_900_linear_pa_r0_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_900_linear_pa_r1_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_900_linear_pa_r2_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_900_linear_pa_r3_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1800_linear_pa_r0_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1800_linear_pa_r1_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1800_linear_pa_r2_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1800_linear_pa_r3_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_linear_pa_r0_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_linear_pa_r1_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_linear_pa_r2_temp_comp_type), 0, 1},
+ { sizeof(nvi_gsm_1900_linear_pa_r3_temp_comp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wlan_uuid_type), 0, 1},
+ { sizeof(nvi_hdr_is683a_scan_list_type), 2, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_cgps_qwip_hepe_params_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
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+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_mipv6_sec_ha_type), 0, 1},
+ { sizeof(nvi_mipv6_hoa_prefix_len_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
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+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_undp_feat_configs_type), 0, 1},
+ { sizeof(nvi_lte_b13_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b13_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_lte_b13_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b13_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b13_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b13_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b13_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_rxf_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_agc_pa_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_agc_tx_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_pa_gain_up_down_time_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_rot_angle_pa_state_type), 0, 1},
+ { sizeof(nvi_lte_b13_pa_compensate_up_down_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_lin_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b13_pa_range_map_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b13_pa_rise_fall_threshold_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_limit_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b13_mpr_based_pa_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_digital_gain_comp_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_gain_index_0_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_gain_index_1_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_gain_index_2_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_gain_index_3_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_comp_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b13_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_limit_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_hdet_off_span_type), 0, 1},
+ { sizeof(nvi_lte_b13_antsel_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_antsel_type), 0, 1},
+ { sizeof(nvi_lte_c1_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_c1_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_b13_c1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b7_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b7_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b7_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b7_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b7_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b7_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b7_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_rxf_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_agc_pa_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_agc_tx_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_pa_gain_up_down_time_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_rot_angle_pa_state_type), 0, 1},
+ { sizeof(nvi_lte_b7_pa_compensate_up_down_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_lin_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b7_pa_range_map_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b7_pa_rise_fall_threshold_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_limit_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b7_mpr_based_pa_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_digital_gain_comp_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_gain_index_0_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_gain_index_1_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_gain_index_2_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_gain_index_3_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_comp_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b7_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_lte_b7_tx_limit_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_hdet_off_span_type), 0, 1},
+ { sizeof(nvi_lte_b7_antsel_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_antsel_type), 0, 1},
+ { sizeof(nvi_lte_c1_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_b7_c1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b17_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b17_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b17_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b17_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b17_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b17_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b17_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_rxf_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_agc_pa_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_agc_tx_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_pa_gain_up_down_time_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_rot_angle_pa_state_type), 0, 1},
+ { sizeof(nvi_lte_b17_pa_compensate_up_down_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_lin_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b17_pa_range_map_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b17_pa_rise_fall_threshold_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_limit_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_lte_b17_mpr_based_pa_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_digital_gain_comp_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_gain_index_0_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_gain_index_1_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_gain_index_2_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_gain_index_3_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_comp_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b17_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_lte_b17_tx_limit_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_hdet_off_span_type), 0, 1},
+ { sizeof(nvi_lte_b17_antsel_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_antsel_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_c1_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_c1_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_lte_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b40_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b40_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b40_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b40_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b40_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b40_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b40_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_rxf_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_agc_pa_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_agc_tx_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_pa_gain_up_down_time_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_rot_angle_pa_state_type), 0, 1},
+ { sizeof(nvi_lte_b40_pa_compensate_up_down_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_lin_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b40_pa_range_map_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b40_pa_rise_fall_threshold_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_limit_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b40_mpr_based_pa_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_digital_gain_comp_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_gain_index_0_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_gain_index_1_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_gain_index_2_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_gain_index_3_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_comp_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b40_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_lte_b40_tx_limit_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_hdet_off_span_type), 0, 1},
+ { sizeof(nvi_lte_b40_antsel_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_antsel_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_c1_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_c1_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_b40_c1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b1_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b1_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b1_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b1_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b1_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b1_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_rxf_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_int32_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_agc_pa_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_agc_tx_on_rise_fall_delay_type), 0, 1},
+ { sizeof(nvi_lte_pa_gain_up_down_time_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_rot_angle_pa_state_type), 0, 1},
+ { sizeof(nvi_lte_b1_pa_compensate_up_down_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_lin_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b1_pa_range_map_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b1_pa_rise_fall_threshold_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_limit_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b1_mpr_based_pa_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_digital_gain_comp_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_gain_index_0_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_gain_index_1_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_gain_index_2_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_gain_index_3_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_comp_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_b1_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_limit_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_hdet_off_span_type), 0, 1},
+ { sizeof(nvi_lte_b1_antsel_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_antsel_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_lte_c1_nonbypass_bypass_timer_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_lna_range_rise_fall_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_im_level_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_rx_gain_vs_temp_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_lna_phase_ctrl_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_rx_gain_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_rx_gain_vs_freq_type), 0, 1},
+ { sizeof(nvi_lte_c1_im2_values_type), 0, 1},
+ { sizeof(nvi_lte_b1_c1_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_lte_b13_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_lte_b7_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_lte_b17_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_lte_b40_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_lte_b1_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_rel7_pa_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gnss_pp_reserved_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_cgps_default_region_size_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_clkrgm_debug_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_csim_static_1x_app), 0, 1},
+ { sizeof(nvi_csim_static_gw_app), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_bus_prof_imem_mode_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_simple_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_bus_prof_advanced_settings_t), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_lte_tx_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_mismatch_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_carrier_feedthrough_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_carrier_feedthrough_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_carrier_feedthrough_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_carrier_feedthrough_comp_type), 0, 1},
+ { sizeof(nvi_lte_tx_carrier_feedthrough_comp_type), 0, 1},
+ { sizeof(nvi_lte_bc_config_type), 0, 1},
+ { sizeof(nvi_lte_bc_config_div_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_enhanced_hplmn_srch_tbl_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gnss_medium_preference_list_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_oem_item_1_type), 0, 1},
+ { sizeof(nvi_oem_item_2_type), 0, 1},
+ { sizeof(nvi_oem_item_3_type), 0, 1},
+ { sizeof(nvi_oem_item_4_type), 0, 1},
+ { sizeof(nvi_oem_item_5_type), 0, 1},
+ { sizeof(nvi_oem_item_6_type), 0, 1},
+ { sizeof(nvi_oem_item_7_type), 0, 1},
+ { sizeof(nvi_oem_item_8_type), 0, 1},
+ { sizeof(nvi_rc_process_errors_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_bc0_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc1_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc3_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc4_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc5_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc6_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc10_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc14_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_bc15_pa_smps_pdm_level_type), 0, 1},
+ { sizeof(nvi_hs_usb_phy_config_type), 0, 1},
+ { sizeof(nvi_qmi_port_list_type), 0, 1},
+ { sizeof(nvi_active_subs_info_s_type), 0, 1},
+ { sizeof(nvi_active_subs_info_s_type), 0, 1},
+ { sizeof(nvi_dual_standby_cfg_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_enum_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_master_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_master_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_vs_temp_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_vs_temp_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_slp_vs_temp_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_slp_vs_temp_1_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lim_vs_temp_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lim_vs_freq_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_exp_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_master_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_master_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_slp_vs_temp_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_slp_vs_temp_3_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_range_map_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_cal_chan_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_compensate_up_with_dvs_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_compensate_dn_with_dvs_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_utran_tx_lim_vs_temp_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_max_pwr_backoff_voltages_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_max_pwr_backoff_volt1_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_max_pwr_backoff_volt2_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_max_pwr_backoff_volt3_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_pdm_lin_0_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_pdm_lin_1_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_pdm_lin_2_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_pdm_lin_3_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_iaccum_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_qaccum_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int8_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_rel6_tx_beta_scaling_comp_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_rel6_tx_agc_offset_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_rel6_tx_mpr_backoff_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_0_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_1_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_2_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_3_secondary_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_comp_vs_freq_sec_pdm_list_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_master_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_pdm_lin_0_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_hs_switchpoints_shift_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_drx_mode_sel_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_vga_gain_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_vga_gain_offset_vs_temp_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_lna_offset_vs_freq_2_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_lna_offset_vs_freq_3_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_lna_offset_vs_freq_4_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_lna_offset_vs_freq_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_rx_cal_chan_type), 0, 1},
+ { sizeof(nvi_c1_rf_antsel_umts_1500_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_1500_lna_phase_ctl_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_comp_up_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_comp_down_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_comp_up_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_comp_down_r2_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_comp_up_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_pa_comp_down_r3_vs_freq_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_exp_hdet_vs_agc_v2_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_tx_lin_master_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_lin_master_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_lin_master_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_lin_master_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_lin_master_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_lin_master_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_lin_master_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_tx_pdm_lin_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_800_tx_pdm_lin_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_900_tx_pdm_lin_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_bc4_tx_pdm_lin_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1800_tx_pdm_lin_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1900_tx_pdm_lin_3_enh_type), 0, 1},
+ { sizeof(nvi_wcdma_1500_tx_pdm_lin_3_enh_type), 0, 1},
+ { sizeof(nvi_undp_uim_dvrstr_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gnss_internal_confidence_stationary_type), 0, 1},
+ { sizeof(nvi_gnss_internal_confidence_non_stationary_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_extended_equivalent_plmn_list_type), 0, 1},
+ { sizeof(nvi_data_call_over_ehrpd_only_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_wcdma_2100_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_2100_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_2100_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_gobi_boot_uqcn_filename_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_gobi_image_table_type), 17, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_wcdma_800_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_wcdma_800_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_800_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_ddtm_allow_so_list_s_type), 0, 1},
+ { sizeof(nvi_cgps_sm_supl_network_params_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_uint32_type), 0, 1},
+ { sizeof(nvi_boolean_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_uint8_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_wcdma_dc1_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_wcdma_dc2_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_wcdma_dc1_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_wcdma_dc2_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_dc1_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_dc2_rxf_ici_cal_data_car0_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_dc1_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_c1_wcdma_dc2_rxf_ici_cal_data_car1_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_int16_type), 0, 1},
+ { sizeof(nvi_lte_b17_c1_rx_gain_vs_freq_i_type), 0, 1},
+ { sizeof(nvi_lte_b13_exp_lpm_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_lte_b13_tx_limit_vs_freq_lpm_type), 0, 1},
+ { sizeof(nvi_uint16_type), 0, 1},
+ { sizeof(nvi_lte_b1_exp_lpm_hdet_vs_agc_type), 0, 1},
+ { sizeof(nvi_lte_b1_tx_limit_vs_freq_lpm_type), 0, 1},
+ { sizeof(nvi_therm_bins_2_type), 0, 1}
+#ifdef FEATURE_BAK_IMEI
+ ,{ sizeof(nvi_bak_imei_type), 0, 1}
+#endif
+};
projects / huawei.git / blobdiff