* Sandpoint X3 User's manual.
*/
static u_char sandpoint_openpic_initsenses[] __initdata = {
-// REX
-#if 0
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 0: SIOINT */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 2: PCI Slot 1 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 3: PCI Slot 2 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 4: PCI Slot 3 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 5: PCI Slot 4 */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 8: IDE (INT C) */
- (IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE) /* 9: IDE (INT D) */
-#else
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 17, EPIC IRQ 1 - PCI1 - flash*/
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 18, EPIC IRQ 2 - LAN*/
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 19, EPIC IRQ 3 - Not used*/
(IRQ_SENSE_LEVEL | IRQ_POLARITY_NEGATIVE), /* 20, EPIC IRQ 4 - Not used*/
1
-#endif
};
/*
* Motorola SPS Sandpoint interrupt routing.
*/
-#if 0 //REX: by MUSENKI
-static inline int
-sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { SANDPOINT_SIO_IRQ,
- 0, 0, 0 }, /* IDSEL 11 - i8259 on Winbond */
- { 0, 0, 0, 0 }, /* IDSEL 12 - unused */
-#ifdef CONFIG_SANDPOINT_X3
- { 17, 18, 19, 20 }, /* IDSEL 13 - PCI slot 1 */
- { 18, 19, 20, 17 }, /* IDSEL 14 - PCI slot 2 */
- { 19, 20, 17, 18 }, /* IDSEL 15 - PCI slot 3 */
- { 20, 17, 18, 19 }, /* IDSEL 16 - PCI slot 4 */
-#else
- { 16, 19, 18, 17 }, /* IDSEL 13 - PCI slot 1 */
- { 17, 16, 19, 18 }, /* IDSEL 14 - PCI slot 2 */
- { 18, 17, 16, 19 }, /* IDSEL 15 - PCI slot 3 */
- { 19, 18, 17, 16 }, /* IDSEL 16 - PCI slot 4 */
-#endif
- };
-
- const long min_idsel = 11, max_idsel = 16, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-}
-#endif
-#if 0 //+Bing modified 11252004
-static inline int
-sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
-{
- static char pci_irq_table[][4] =
- /*
- * PCI IDSEL/INTPIN->INTLINE
- * A B C D
- */
- {
- { 3, 0, 0, 0 }, /* IDSEL 17 - disable */
- { 0, 0, 0, 0 }, /* IDSEL 18 - PCI slot1*/
- { 2, 0, 0, 0 }, /* IDSEL 19 - LAN 83815 */
- { 1, 0, 4, 0 } /* IDSEL 20 - PCI slot2 */
- };
-
- const long min_idsel = 17, max_idsel = 20, irqs_per_slot = 4;
- return PCI_IRQ_TABLE_LOOKUP;
-}
-#else
+//REX: by MUSENKI
static inline int
sandpoint_map_irq(struct pci_dev *dev, unsigned char idsel, unsigned char pin)
{
const long min_idsel = 13, max_idsel = 16, irqs_per_slot = 4;
return PCI_IRQ_TABLE_LOOKUP;
}
-#endif //+Bing modified 11252004
+//REX: by MUSENKI
#if 0 //REX