www.usr.com/support/gpl/USR9107_release.1.4.tar.gz

[bcm963xx.git] / bcmdrivers / opensource / include / bcm963xx / 6338_map_part.h

diff --git a/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h b/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h
index cc3b98d..85e8b9f 100755 (executable)
--- a/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h
+++ b/bcmdrivers/opensource/include/bcm963xx/6338_map_part.h
@@ -27,14 +27,20 @@ extern "C" {
 #include "bcmtypes.h"
 
 #define PERF_BASE           0xfffe0000
+#define TIMR_BASE           0xfffe0200 
 #define UART_BASE           0xfffe0300
 #define GPIO_BASE           0xfffe0400
+#define SPI_BASE            0xfffe0c00
 
 typedef struct PerfControl {
   uint32        RevID;
   uint16        testControl;
   uint16        blkEnables;
-#define USBH_CLK_EN     0x0100
+#define EMAC_CLK_EN     0x0010
+#define USBS_CLK_EN     0x0010
+#define SAR_CLK_EN      0x0020
+
+#define SPI_CLK_EN      0x0200
 
   uint32        pll_control;
 #define SOFT_RESET 0x00000001
@@ -68,6 +74,39 @@ typedef struct PerfControl {
 
 #define PERF ((volatile PerfControl * const) PERF_BASE)
 
+
+typedef struct Timer {
+  uint16        unused0;
+  byte          TimerMask;
+#define TIMER0EN        0x01
+#define TIMER1EN        0x02
+#define TIMER2EN        0x04
+  byte          TimerInts;
+#define TIMER0          0x01
+#define TIMER1          0x02
+#define TIMER2          0x04
+#define WATCHDOG        0x08
+  uint32        TimerCtl0;
+  uint32        TimerCtl1;
+  uint32        TimerCtl2;
+#define TIMERENABLE     0x80000000
+#define RSTCNTCLR       0x40000000      
+  uint32        TimerCnt0;
+  uint32        TimerCnt1;
+  uint32        TimerCnt2;
+  uint32        WatchDogDefCount;
+
+  /* Write 0xff00 0x00ff to Start timer
+   * Write 0xee00 0x00ee to Stop and re-load default count
+   * Read from this register returns current watch dog count
+   */
+  uint32        WatchDogCtl;
+
+  /* Number of 40-MHz ticks for WD Reset pulse to last */
+  uint32        WDResetCount;
+} Timer;
+
+#define TIMER ((volatile Timer * const) TIMR_BASE)
 typedef struct UartChannel {
   byte          unused0;
   byte          control;
@@ -209,6 +248,50 @@ typedef struct GpioControl {
 #define GPIO_NUM_MAX_BITS_MASK          0x0f
 #define GPIO_NUM_TO_MASK(X)             (1 << ((X) & GPIO_NUM_MAX_BITS_MASK))
 
+/*
+** Spi Controller
+*/
+
+typedef struct SpiControl {
+  uint16        spiCmd;                 /* (0x0): SPI command */
+#define SPI_CMD_START_IMMEDIATE         3
+
+#define SPI_CMD_COMMAND_SHIFT           0
+#define SPI_CMD_DEVICE_ID_SHIFT         4
+#define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
+
+  byte          spiIntStatus;           /* (0x2): SPI interrupt status */
+  byte          spiMaskIntStatus;       /* (0x3): SPI masked interrupt status */
+
+  byte          spiIntMask;             /* (0x4): SPI interrupt mask */
+#define SPI_INTR_CMD_DONE               0x01
+#define SPI_INTR_CLEAR_ALL              0x1f
+
+  byte          spiStatus;              /* (0x5): SPI status */
+
+  byte          spiClkCfg;              /* (0x6): SPI clock configuration */
+
+  byte          spiFillByte;            /* (0x7): SPI fill byte */
+
+  byte          unused0; 
+  byte          spiMsgTail;             /* (0x9): msgtail */
+  byte          unused1; 
+  byte          spiRxTail;              /* (0xB): rxtail */
+
+  uint32        unused2[13];            /* (0x0c - 0x3c) reserved */
+
+  byte          spiMsgCtl;              /* (0x40) control byte */
+#define HALF_DUPLEX_W                   1
+#define HALF_DUPLEX_R                   2
+#define SPI_MSG_TYPE_SHIFT              6
+#define SPI_BYTE_CNT_SHIFT              0
+  byte          spiMsgData[63];         /* (0x41 - 0x7f) msg data */
+  byte          spiRxDataFifo[64];      /* (0x80 - 0xbf) rx data */
+  byte          unused3[64];            /* (0xc0 - 0xff) reserved */
+} SpiControl;
+
+#define SPI ((volatile SpiControl * const) SPI_BASE)
+
 /*
 ** External Bus Interface
 */