#-----------------------------------------------------------------------------\r
-\r
# Makefile for usb_jtag FX2 firmware\r
-\r
#-----------------------------------------------------------------------------\r
-\r
# Copyright 2007 Kolja Waschk, ixo.de\r
-\r
#-----------------------------------------------------------------------------\r
-\r
# This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
# it and/or modify it under the terms of the GNU General Public License as\r
-\r
# published by the Free Software Foundation; either version 2 of the License,\r
-\r
# or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
# that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
# GNU General Public License for more details. You should have received a\r
-\r
# copy of the GNU General Public License along with this program in the file\r
-\r
# COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
# St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
#-----------------------------------------------------------------------------\r
\r
-\r
-\r
LIBDIR=fx2\r
-\r
LIB=libfx2.lib\r
\r
-\r
-\r
ifeq (${HARDWARE},)\r
-\r
HARDWARE=hw_basic\r
-\r
+ #HARDWARE=hw_saxo_l\r
#HARDWARE=hw_xpcu_i\r
-\r
#HARDWARE=hw_xpcu_x\r
-\r
endif\r
\r
-\r
-\r
CC=sdcc\r
-\r
CFLAGS+=-mmcs51 --no-xinit-opt -I${LIBDIR} -D${HARDWARE}\r
\r
CFLAGS+=--opt-code-size\r
\r
-\r
-\r
AS=asx8051\r
-\r
ASFLAGS+=-plosgff\r
\r
-\r
-\r
LDFLAGS=--code-loc 0x0000 --code-size 0x1800\r
-\r
LDFLAGS+=--xram-loc 0x1800 --xram-size 0x0800\r
-\r
LDFLAGS+=-Wl '-b USBDESCSEG = 0xE100'\r
-\r
LDFLAGS+=-L ${LIBDIR}\r
\r
-\r
-\r
%.rel : %.a51\r
-\r
$(AS) $(ASFLAGS) $<\r
\r
-\r
-\r
%.rel : %.c\r
-\r
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@\r
\r
-\r
+default: usbjtag.iic\r
\r
%.iic : %.hex\r
-\r
./hex2bix -ir -f 0xC2 -m 0xF000 -c 0x1 -o $@ $<\r
\r
-\r
-\r
-default: usbjtag.iic\r
-\r
-\r
-\r
usbjtag.hex: vectors.rel usbjtag.rel dscr.rel eeprom.rel ${HARDWARE}.rel startup.rel ${LIBDIR}/${LIB}\r
-\r
$(CC) $(CFLAGS) $(LDFLAGS) -o $@ $+\r
-\r
packihx $@ > .tmp.hex\r
-\r
rm $@\r
-\r
mv .tmp.hex $@\r
\r
-\r
-\r
${LIBDIR}/${LIB}:\r
-\r
make -C ${LIBDIR}\r
\r
-\r
-\r
.PHONY: boot\r
-\r
boot: usbjtag.hex\r
-\r
-test -e /dev/usb_jtag && /sbin/fxload -D /dev/usb_jtag -I usbjtag.hex -t fx2\r
-\r
-test -e /dev/tracii_xl2 && /sbin/fxload -D /dev/tracii_xl2 -I usbjtag.hex -t fx2\r
-\r
-test -e /dev/xilinx_xpcu && /sbin/fxload -D /dev/xilinx_xpcu -I usbjtag.hex -t fx2\r
\r
-\r
-\r
REF=/home/kawk/work/xilinx/xtern/xusbdfwu/xusbdfwu-1025.hex\r
\r
-\r
-\r
.PHONY: ref\r
-\r
ref: \r
-\r
-test -e /dev/usb_jtag && /sbin/fxload -D /dev/usb_jtag -I ${REF} -t fx2\r
-\r
-test -e /dev/tracii_xl2 && /sbin/fxload -D /dev/tracii_xl2 -I ${REF} -t fx2\r
-\r
-test -e /dev/xilinx_xpcu && /sbin/fxload -D /dev/xilinx_xpcu -I ${REF} -t fx2\r
\r
-\r
-\r
dscr.rel: dscr.a51\r
-\r
eeprom.rel: eeprom.c eeprom.h\r
-\r
usbjtag.rel: usbjtag.c hardware.h eeprom.h\r
-\r
${HARDWARE}.rel: ${HARDWARE}.c hardware.h\r
\r
-\r
-\r
.PHONY: clean distclean\r
\r
-\r
-\r
clean:\r
-\r
make -C ${LIBDIR} clean\r
-\r
rm -f *.lst *.asm *.lib *.sym *.rel *.mem *.map *.rst *.lnk *.hex *.ihx *.iic\r
\r
-\r
-\r
distclean: clean\r
\r
\r
\r
-\r
-\r
-\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* FTDI EEPROM emulation\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Copyright (C) 2007 Kolja Waschk, ixo.de\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "eeprom.h"\r
-\r
#include "usb_descriptors.h"\r
\r
-\r
-\r
xdata unsigned char eeprom[128];\r
\r
-\r
-\r
extern xdata char dscr_vidpidver[6];\r
-\r
extern xdata char dscr_attrpow[2];\r
-\r
extern xdata char dscr_usbver[2];\r
-\r
extern xdata char dscr_strorder[4];\r
-\r
extern xdata char str1[];\r
-\r
extern xdata char str2[];\r
-\r
extern xdata char str3[];\r
\r
-\r
-\r
static unsigned char ee_ptr;\r
-\r
static unsigned short ee_cksum;\r
\r
-\r
-\r
void eeprom_append(unsigned char nb)\r
-\r
{\r
-\r
unsigned char pree_ptr = ee_ptr & ~1;\r
-\r
if(pree_ptr != ee_ptr)\r
-\r
{\r
-\r
ee_cksum = ee_cksum ^((unsigned short)nb << 8);\r
-\r
ee_cksum = ee_cksum ^ eeprom[pree_ptr];\r
-\r
ee_cksum = (ee_cksum << 1) | (ee_cksum >> 15);\r
-\r
};\r
-\r
eeprom[ee_ptr++] = nb;\r
-\r
}\r
\r
-\r
-\r
void eeprom_init(void)\r
-\r
{\r
-\r
char j,sofs;\r
-\r
ee_ptr = 0;\r
-\r
ee_cksum = 0xAAAA;\r
\r
-\r
-\r
eeprom_append(0x00);\r
-\r
eeprom_append(0x00);\r
-\r
for(j=0;j<6;j++) eeprom_append(dscr_vidpidver[j]);\r
-\r
for(j=0;j<2;j++) eeprom_append(dscr_attrpow[j]);\r
-\r
eeprom_append(0x1C);\r
-\r
eeprom_append(0x00);\r
-\r
for(j=0;j<2;j++) eeprom_append(dscr_usbver[j]);\r
-\r
sofs = 0x80 + ee_ptr + 6;\r
-\r
eeprom_append(sofs);\r
-\r
eeprom_append(str1[0]);\r
-\r
sofs += str1[0];\r
-\r
eeprom_append(sofs);\r
-\r
eeprom_append(str2[0]);\r
-\r
sofs += str2[0];\r
-\r
eeprom_append(sofs);\r
-\r
eeprom_append(str3[0]);\r
-\r
for(j=0;j<str1[0];j++) eeprom_append(str1[j]);\r
-\r
for(j=0;j<str2[0];j++) eeprom_append(str2[j]);\r
-\r
for(j=0;j<str3[0];j++) eeprom_append(str3[j]);\r
-\r
for(j=0;j<4;j++) eeprom_append(dscr_strorder[j]);\r
-\r
while(ee_ptr < 126) eeprom_append(0);\r
-\r
eeprom[126] = ee_cksum&0xFF;\r
-\r
eeprom[127] = (ee_cksum>>8)&0xFF;\r
-\r
}\r
\r
-\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* FTDI EEPROM emulation\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Copyright (C) 2007 Kolja Waschk, ixo.de\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _EEPROM_H\r
-\r
#define _EEPROM_H 1\r
\r
-\r
-\r
extern xdata unsigned char eeprom[128];\r
-\r
extern void eeprom_init(void);\r
\r
-\r
-\r
#endif /* _EEPROM_H */\r
\r
-\r
-\r
#-----------------------------------------------------------------------------\r
-\r
# Makefile for FX2 library code\r
-\r
#-----------------------------------------------------------------------------\r
-\r
# Copyright (C) 2007 Kolja Waschk, ixo.de\r
-\r
#-----------------------------------------------------------------------------\r
-\r
# This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
# it and/or modify it under the terms of the GNU General Public License as\r
-\r
# published by the Free Software Foundation; either version 2 of the License,\r
-\r
# or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
# that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
# warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
# GNU General Public License for more details. You should have received a\r
-\r
# copy of the GNU General Public License along with this program in the file\r
-\r
# COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
# St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
#-----------------------------------------------------------------------------\r
\r
-\r
-\r
CC=sdcc\r
-\r
CFLAGS+=-mmcs51 --no-xinit-opt -I.\r
-\r
CPPFLAGS+=\r
\r
-\r
-\r
%.rel : %.c\r
-\r
$(CC) -c $(CFLAGS) $(CPPFLAGS) $< -o $@\r
\r
-\r
-\r
libfx2.lib: delay.rel fx2utils.rel i2c.rel isr.rel timer.rel usb_common.rel\r
-\r
rm -f $@\r
-\r
touch $@\r
-\r
for obj in $^ ; do basename $$obj .rel >> $@ ; done\r
\r
-\r
-\r
clean:\r
-\r
rm -f *.lst *.asm *.lib *.sym *.rel *.lib\r
\r
\r
\r
\r
-\r
-\r
-\r
-\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Delay routines\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
/*\r
-\r
* Delay approximately 1 microsecond (including overhead in udelay).\r
-\r
*/\r
-\r
static void\r
-\r
udelay1 (void) _naked\r
-\r
{\r
-\r
_asm ; lcall that got us here took 4 bus cycles\r
-\r
ret ; 4 bus cycles\r
-\r
_endasm;\r
-\r
}\r
\r
-\r
-\r
/*\r
-\r
* delay for approximately usecs microseconds\r
-\r
*/\r
-\r
void\r
-\r
udelay (unsigned char usecs)\r
-\r
{\r
-\r
do {\r
-\r
udelay1 ();\r
-\r
} while (--usecs != 0);\r
-\r
}\r
\r
\r
-\r
-\r
-\r
/*\r
-\r
* Delay approximately 1 millisecond.\r
-\r
* We're running at 48 MHz, so we need 48,000 clock cycles.\r
-\r
*\r
-\r
* Note however, that each bus cycle takes 4 clock cycles (not obvious,\r
-\r
* but explains the factor of 4 problem below).\r
-\r
*/\r
-\r
static void\r
-\r
mdelay1 (void) _naked\r
-\r
{\r
-\r
_asm\r
-\r
mov dptr,#(-1200 & 0xffff)\r
-\r
002$: \r
-\r
inc dptr ; 3 bus cycles\r
-\r
mov a, dpl ; 2 bus cycles\r
-\r
orl a, dph ; 2 bus cycles\r
-\r
jnz 002$ ; 3 bus cycles\r
\r
-\r
-\r
ret\r
-\r
_endasm;\r
-\r
}\r
\r
-\r
-\r
void\r
-\r
mdelay (unsigned int msecs)\r
-\r
{\r
-\r
do {\r
-\r
mdelay1 ();\r
-\r
} while (--msecs != 0);\r
-\r
}\r
\r
-\r
-\r
\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Delay routines\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _DELAY_H_\r
-\r
#define _DELAY_H_\r
\r
-\r
-\r
/*\r
-\r
* delay for approximately usecs microseconds\r
-\r
* Note limit of 255 usecs.\r
-\r
*/\r
-\r
void udelay (unsigned char usecs);\r
\r
-\r
-\r
/*\r
-\r
* delay for approximately msecs milliseconds\r
-\r
*/\r
-\r
void mdelay (unsigned short msecs);\r
\r
\r
-\r
-\r
-\r
#endif /* _DELAY_H_ */\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* FX2 register definitions\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
/*\r
-\r
//-----------------------------------------------------------------------------\r
-\r
// File: FX2regs.h\r
-\r
// Contents: EZ-USB FX2 register declarations and bit mask definitions.\r
-\r
//\r
-\r
// $Archive: /USB/Target/Inc/fx2regs.h $\r
-\r
-// $Date: 2009/09/30 14:08:56 $\r
-\r
-// $Revision: 1.5 $\r
-\r
+// $Date: 2009/11/09 14:48:44 $\r
+// $Revision: 1.6 $\r
//\r
-\r
//\r
-\r
// Copyright (c) 2000 Cypress Semiconductor, All rights reserved\r
-\r
//-----------------------------------------------------------------------------\r
-\r
*/\r
\r
\r
-\r
-\r
-\r
#ifndef FX2REGS_H /* Header Sentry */\r
-\r
#define FX2REGS_H\r
\r
-\r
-\r
#define ALLOCATE_EXTERN // required for "right thing to happen" with fx2regs.h\r
\r
-\r
-\r
/*\r
-\r
//-----------------------------------------------------------------------------\r
-\r
// FX2 Related Register Assignments\r
-\r
//-----------------------------------------------------------------------------\r
\r
-\r
-\r
// The Ez-USB FX2 registers are defined here. We use FX2regs.h for register \r
-\r
// address allocation by using "#define ALLOCATE_EXTERN". \r
-\r
// When using "#define ALLOCATE_EXTERN", you get (for instance): \r
-\r
// xdata volatile BYTE OUT7BUF[64] _at_ 0x7B40;\r
-\r
// Such lines are created from FX2.h by using the preprocessor. \r
-\r
// Incidently, these lines will not generate any space in the resulting hex \r
-\r
// file; they just bind the symbols to the addresses for compilation. \r
-\r
// You just need to put "#define ALLOCATE_EXTERN" in your main program file; \r
-\r
// i.e. fw.c or a stand-alone C source file. \r
-\r
// Without "#define ALLOCATE_EXTERN", you just get the external reference: \r
-\r
// extern xdata volatile BYTE OUT7BUF[64] ;// 0x7B40;\r
-\r
// This uses the concatenation operator "##" to insert a comment "//" \r
-\r
// to cut off the end of the line, "_at_ 0x7B40;", which is not wanted.\r
-\r
*/\r
\r
\r
-\r
-\r
-\r
#ifdef ALLOCATE_EXTERN\r
-\r
#define EXTERN\r
-\r
#define _AT_(a) at a\r
-\r
#else\r
-\r
#define EXTERN extern\r
-\r
#define _AT_ ;/ ## /\r
-\r
#endif\r
\r
-\r
-\r
typedef unsigned char BYTE;\r
-\r
typedef unsigned short WORD;\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE400) volatile BYTE GPIF_WAVE_DATA[128];\r
-\r
EXTERN xdata _AT_(0xE480) volatile BYTE RES_WAVEDATA_END ;\r
\r
-\r
-\r
// General Configuration\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE600) volatile BYTE CPUCS ; // Control & Status\r
-\r
EXTERN xdata _AT_(0xE601) volatile BYTE IFCONFIG ; // Interface Configuration\r
-\r
EXTERN xdata _AT_(0xE602) volatile BYTE PINFLAGSAB ; // FIFO FLAGA and FLAGB Assignments\r
-\r
EXTERN xdata _AT_(0xE603) volatile BYTE PINFLAGSCD ; // FIFO FLAGC and FLAGD Assignments\r
-\r
EXTERN xdata _AT_(0xE604) volatile BYTE FIFORESET ; // Restore FIFOS to default state\r
-\r
EXTERN xdata _AT_(0xE605) volatile BYTE BREAKPT ; // Breakpoint\r
-\r
EXTERN xdata _AT_(0xE606) volatile BYTE BPADDRH ; // Breakpoint Address H\r
-\r
EXTERN xdata _AT_(0xE607) volatile BYTE BPADDRL ; // Breakpoint Address L\r
-\r
EXTERN xdata _AT_(0xE608) volatile BYTE UART230 ; // 230 Kbaud clock for T0,T1,T2\r
-\r
EXTERN xdata _AT_(0xE609) volatile BYTE FIFOPINPOLAR ; // FIFO polarities\r
-\r
EXTERN xdata _AT_(0xE60A) volatile BYTE REVID ; // Chip Revision\r
-\r
EXTERN xdata _AT_(0xE60B) volatile BYTE REVCTL ; // Chip Revision Control\r
\r
-\r
-\r
// Endpoint Configuration\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE610) volatile BYTE EP1OUTCFG ; // Endpoint 1-OUT Configuration\r
-\r
EXTERN xdata _AT_(0xE611) volatile BYTE EP1INCFG ; // Endpoint 1-IN Configuration\r
-\r
EXTERN xdata _AT_(0xE612) volatile BYTE EP2CFG ; // Endpoint 2 Configuration\r
-\r
EXTERN xdata _AT_(0xE613) volatile BYTE EP4CFG ; // Endpoint 4 Configuration\r
-\r
EXTERN xdata _AT_(0xE614) volatile BYTE EP6CFG ; // Endpoint 6 Configuration\r
-\r
EXTERN xdata _AT_(0xE615) volatile BYTE EP8CFG ; // Endpoint 8 Configuration\r
-\r
EXTERN xdata _AT_(0xE618) volatile BYTE EP2FIFOCFG ; // Endpoint 2 FIFO configuration\r
-\r
EXTERN xdata _AT_(0xE619) volatile BYTE EP4FIFOCFG ; // Endpoint 4 FIFO configuration\r
-\r
EXTERN xdata _AT_(0xE61A) volatile BYTE EP6FIFOCFG ; // Endpoint 6 FIFO configuration\r
-\r
EXTERN xdata _AT_(0xE61B) volatile BYTE EP8FIFOCFG ; // Endpoint 8 FIFO configuration\r
-\r
EXTERN xdata _AT_(0xE620) volatile BYTE EP2AUTOINLENH ; // Endpoint 2 Packet Length H (IN only)\r
-\r
EXTERN xdata _AT_(0xE621) volatile BYTE EP2AUTOINLENL ; // Endpoint 2 Packet Length L (IN only)\r
-\r
EXTERN xdata _AT_(0xE622) volatile BYTE EP4AUTOINLENH ; // Endpoint 4 Packet Length H (IN only)\r
-\r
EXTERN xdata _AT_(0xE623) volatile BYTE EP4AUTOINLENL ; // Endpoint 4 Packet Length L (IN only)\r
-\r
EXTERN xdata _AT_(0xE624) volatile BYTE EP6AUTOINLENH ; // Endpoint 6 Packet Length H (IN only)\r
-\r
EXTERN xdata _AT_(0xE625) volatile BYTE EP6AUTOINLENL ; // Endpoint 6 Packet Length L (IN only)\r
-\r
EXTERN xdata _AT_(0xE626) volatile BYTE EP8AUTOINLENH ; // Endpoint 8 Packet Length H (IN only)\r
-\r
EXTERN xdata _AT_(0xE627) volatile BYTE EP8AUTOINLENL ; // Endpoint 8 Packet Length L (IN only)\r
-\r
EXTERN xdata _AT_(0xE630) volatile BYTE EP2FIFOPFH ; // EP2 Programmable Flag trigger H\r
-\r
EXTERN xdata _AT_(0xE631) volatile BYTE EP2FIFOPFL ; // EP2 Programmable Flag trigger L\r
-\r
EXTERN xdata _AT_(0xE632) volatile BYTE EP4FIFOPFH ; // EP4 Programmable Flag trigger H\r
-\r
EXTERN xdata _AT_(0xE633) volatile BYTE EP4FIFOPFL ; // EP4 Programmable Flag trigger L\r
-\r
EXTERN xdata _AT_(0xE634) volatile BYTE EP6FIFOPFH ; // EP6 Programmable Flag trigger H\r
-\r
EXTERN xdata _AT_(0xE635) volatile BYTE EP6FIFOPFL ; // EP6 Programmable Flag trigger L\r
-\r
EXTERN xdata _AT_(0xE636) volatile BYTE EP8FIFOPFH ; // EP8 Programmable Flag trigger H\r
-\r
EXTERN xdata _AT_(0xE637) volatile BYTE EP8FIFOPFL ; // EP8 Programmable Flag trigger L\r
-\r
EXTERN xdata _AT_(0xE640) volatile BYTE EP2ISOINPKTS ; // EP2 (if ISO) IN Packets per frame (1-3)\r
-\r
EXTERN xdata _AT_(0xE641) volatile BYTE EP4ISOINPKTS ; // EP4 (if ISO) IN Packets per frame (1-3)\r
-\r
EXTERN xdata _AT_(0xE642) volatile BYTE EP6ISOINPKTS ; // EP6 (if ISO) IN Packets per frame (1-3)\r
-\r
EXTERN xdata _AT_(0xE643) volatile BYTE EP8ISOINPKTS ; // EP8 (if ISO) IN Packets per frame (1-3)\r
-\r
EXTERN xdata _AT_(0xE648) volatile BYTE INPKTEND ; // Force IN Packet End\r
-\r
EXTERN xdata _AT_(0xE649) volatile BYTE OUTPKTEND ; // Force OUT Packet End\r
\r
-\r
-\r
// Interrupts\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE650) volatile BYTE EP2FIFOIE ; // Endpoint 2 Flag Interrupt Enable\r
-\r
EXTERN xdata _AT_(0xE651) volatile BYTE EP2FIFOIRQ ; // Endpoint 2 Flag Interrupt Request\r
-\r
EXTERN xdata _AT_(0xE652) volatile BYTE EP4FIFOIE ; // Endpoint 4 Flag Interrupt Enable\r
-\r
EXTERN xdata _AT_(0xE653) volatile BYTE EP4FIFOIRQ ; // Endpoint 4 Flag Interrupt Request\r
-\r
EXTERN xdata _AT_(0xE654) volatile BYTE EP6FIFOIE ; // Endpoint 6 Flag Interrupt Enable\r
-\r
EXTERN xdata _AT_(0xE655) volatile BYTE EP6FIFOIRQ ; // Endpoint 6 Flag Interrupt Request\r
-\r
EXTERN xdata _AT_(0xE656) volatile BYTE EP8FIFOIE ; // Endpoint 8 Flag Interrupt Enable\r
-\r
EXTERN xdata _AT_(0xE657) volatile BYTE EP8FIFOIRQ ; // Endpoint 8 Flag Interrupt Request\r
-\r
EXTERN xdata _AT_(0xE658) volatile BYTE IBNIE ; // IN-BULK-NAK Interrupt Enable\r
-\r
EXTERN xdata _AT_(0xE659) volatile BYTE IBNIRQ ; // IN-BULK-NAK interrupt Request\r
-\r
EXTERN xdata _AT_(0xE65A) volatile BYTE NAKIE ; // Endpoint Ping NAK interrupt Enable\r
-\r
EXTERN xdata _AT_(0xE65B) volatile BYTE NAKIRQ ; // Endpoint Ping NAK interrupt Request\r
-\r
EXTERN xdata _AT_(0xE65C) volatile BYTE USBIE ; // USB Int Enables\r
-\r
EXTERN xdata _AT_(0xE65D) volatile BYTE USBIRQ ; // USB Interrupt Requests\r
-\r
EXTERN xdata _AT_(0xE65E) volatile BYTE EPIE ; // Endpoint Interrupt Enables\r
-\r
EXTERN xdata _AT_(0xE65F) volatile BYTE EPIRQ ; // Endpoint Interrupt Requests\r
-\r
EXTERN xdata _AT_(0xE660) volatile BYTE GPIFIE ; // GPIF Interrupt Enable\r
-\r
EXTERN xdata _AT_(0xE661) volatile BYTE GPIFIRQ ; // GPIF Interrupt Request\r
-\r
EXTERN xdata _AT_(0xE662) volatile BYTE USBERRIE ; // USB Error Interrupt Enables\r
-\r
EXTERN xdata _AT_(0xE663) volatile BYTE USBERRIRQ ; // USB Error Interrupt Requests\r
-\r
EXTERN xdata _AT_(0xE664) volatile BYTE ERRCNTLIM ; // USB Error counter and limit\r
-\r
EXTERN xdata _AT_(0xE665) volatile BYTE CLRERRCNT ; // Clear Error Counter EC[3..0]\r
-\r
EXTERN xdata _AT_(0xE666) volatile BYTE INT2IVEC ; // Interupt 2 (USB) Autovector\r
-\r
EXTERN xdata _AT_(0xE667) volatile BYTE INT4IVEC ; // Interupt 4 (FIFOS & GPIF) Autovector\r
-\r
EXTERN xdata _AT_(0xE668) volatile BYTE INTSETUP ; // Interrupt 2&4 Setup\r
\r
-\r
-\r
// Input/Output\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE670) volatile BYTE PORTACFG ; // I/O PORTA Alternate Configuration\r
-\r
EXTERN xdata _AT_(0xE671) volatile BYTE PORTCCFG ; // I/O PORTC Alternate Configuration\r
-\r
EXTERN xdata _AT_(0xE672) volatile BYTE PORTECFG ; // I/O PORTE Alternate Configuration\r
-\r
EXTERN xdata _AT_(0xE678) volatile BYTE I2CS ; // Control & Status\r
-\r
EXTERN xdata _AT_(0xE679) volatile BYTE I2DAT ; // Data\r
-\r
EXTERN xdata _AT_(0xE67A) volatile BYTE I2CTL ; // I2C Control\r
-\r
EXTERN xdata _AT_(0xE67B) volatile BYTE XAUTODAT1 ; // Autoptr1 MOVX access\r
-\r
EXTERN xdata _AT_(0xE67C) volatile BYTE XAUTODAT2 ; // Autoptr2 MOVX access\r
\r
-\r
-\r
#define EXTAUTODAT1 XAUTODAT1\r
-\r
#define EXTAUTODAT2 XAUTODAT2\r
\r
-\r
-\r
// USB Control\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE680) volatile BYTE USBCS ; // USB Control & Status\r
-\r
EXTERN xdata _AT_(0xE681) volatile BYTE SUSPEND ; // Put chip into suspend\r
-\r
EXTERN xdata _AT_(0xE682) volatile BYTE WAKEUPCS ; // Wakeup source and polarity\r
-\r
EXTERN xdata _AT_(0xE683) volatile BYTE TOGCTL ; // Toggle Control\r
-\r
EXTERN xdata _AT_(0xE684) volatile BYTE USBFRAMEH ; // USB Frame count H\r
-\r
EXTERN xdata _AT_(0xE685) volatile BYTE USBFRAMEL ; // USB Frame count L\r
-\r
EXTERN xdata _AT_(0xE686) volatile BYTE MICROFRAME ; // Microframe count, 0-7\r
-\r
EXTERN xdata _AT_(0xE687) volatile BYTE FNADDR ; // USB Function address\r
\r
-\r
-\r
// Endpoints\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE68A) volatile BYTE EP0BCH ; // Endpoint 0 Byte Count H\r
-\r
EXTERN xdata _AT_(0xE68B) volatile BYTE EP0BCL ; // Endpoint 0 Byte Count L\r
-\r
EXTERN xdata _AT_(0xE68D) volatile BYTE EP1OUTBC ; // Endpoint 1 OUT Byte Count\r
-\r
EXTERN xdata _AT_(0xE68F) volatile BYTE EP1INBC ; // Endpoint 1 IN Byte Count\r
-\r
EXTERN xdata _AT_(0xE690) volatile BYTE EP2BCH ; // Endpoint 2 Byte Count H\r
-\r
EXTERN xdata _AT_(0xE691) volatile BYTE EP2BCL ; // Endpoint 2 Byte Count L\r
-\r
EXTERN xdata _AT_(0xE694) volatile BYTE EP4BCH ; // Endpoint 4 Byte Count H\r
-\r
EXTERN xdata _AT_(0xE695) volatile BYTE EP4BCL ; // Endpoint 4 Byte Count L\r
-\r
EXTERN xdata _AT_(0xE698) volatile BYTE EP6BCH ; // Endpoint 6 Byte Count H\r
-\r
EXTERN xdata _AT_(0xE699) volatile BYTE EP6BCL ; // Endpoint 6 Byte Count L\r
-\r
EXTERN xdata _AT_(0xE69C) volatile BYTE EP8BCH ; // Endpoint 8 Byte Count H\r
-\r
EXTERN xdata _AT_(0xE69D) volatile BYTE EP8BCL ; // Endpoint 8 Byte Count L\r
-\r
EXTERN xdata _AT_(0xE6A0) volatile BYTE EP0CS ; // Endpoint Control and Status\r
-\r
EXTERN xdata _AT_(0xE6A1) volatile BYTE EP1OUTCS ; // Endpoint 1 OUT Control and Status\r
-\r
EXTERN xdata _AT_(0xE6A2) volatile BYTE EP1INCS ; // Endpoint 1 IN Control and Status\r
-\r
EXTERN xdata _AT_(0xE6A3) volatile BYTE EP2CS ; // Endpoint 2 Control and Status\r
-\r
EXTERN xdata _AT_(0xE6A4) volatile BYTE EP4CS ; // Endpoint 4 Control and Status\r
-\r
EXTERN xdata _AT_(0xE6A5) volatile BYTE EP6CS ; // Endpoint 6 Control and Status\r
-\r
EXTERN xdata _AT_(0xE6A6) volatile BYTE EP8CS ; // Endpoint 8 Control and Status\r
-\r
EXTERN xdata _AT_(0xE6A7) volatile BYTE EP2FIFOFLGS ; // Endpoint 2 Flags\r
-\r
EXTERN xdata _AT_(0xE6A8) volatile BYTE EP4FIFOFLGS ; // Endpoint 4 Flags\r
-\r
EXTERN xdata _AT_(0xE6A9) volatile BYTE EP6FIFOFLGS ; // Endpoint 6 Flags\r
-\r
EXTERN xdata _AT_(0xE6AA) volatile BYTE EP8FIFOFLGS ; // Endpoint 8 Flags\r
-\r
EXTERN xdata _AT_(0xE6AB) volatile BYTE EP2FIFOBCH ; // EP2 FIFO total byte count H\r
-\r
EXTERN xdata _AT_(0xE6AC) volatile BYTE EP2FIFOBCL ; // EP2 FIFO total byte count L\r
-\r
EXTERN xdata _AT_(0xE6AD) volatile BYTE EP4FIFOBCH ; // EP4 FIFO total byte count H\r
-\r
EXTERN xdata _AT_(0xE6AE) volatile BYTE EP4FIFOBCL ; // EP4 FIFO total byte count L\r
-\r
EXTERN xdata _AT_(0xE6AF) volatile BYTE EP6FIFOBCH ; // EP6 FIFO total byte count H\r
-\r
EXTERN xdata _AT_(0xE6B0) volatile BYTE EP6FIFOBCL ; // EP6 FIFO total byte count L\r
-\r
EXTERN xdata _AT_(0xE6B1) volatile BYTE EP8FIFOBCH ; // EP8 FIFO total byte count H\r
-\r
EXTERN xdata _AT_(0xE6B2) volatile BYTE EP8FIFOBCL ; // EP8 FIFO total byte count L\r
-\r
EXTERN xdata _AT_(0xE6B3) volatile BYTE SUDPTRH ; // Setup Data Pointer high address byte\r
-\r
EXTERN xdata _AT_(0xE6B4) volatile BYTE SUDPTRL ; // Setup Data Pointer low address byte\r
-\r
EXTERN xdata _AT_(0xE6B5) volatile BYTE SUDPTRCTL ; // Setup Data Pointer Auto Mode\r
-\r
EXTERN xdata _AT_(0xE6B8) volatile BYTE SETUPDAT[8] ; // 8 bytes of SETUP data\r
\r
-\r
-\r
// GPIF\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE6C0) volatile BYTE GPIFWFSELECT ; // Waveform Selector\r
-\r
EXTERN xdata _AT_(0xE6C1) volatile BYTE GPIFIDLECS ; // GPIF Done, GPIF IDLE drive mode\r
-\r
EXTERN xdata _AT_(0xE6C2) volatile BYTE GPIFIDLECTL ; // Inactive Bus, CTL states\r
-\r
EXTERN xdata _AT_(0xE6C3) volatile BYTE GPIFCTLCFG ; // CTL OUT pin drive\r
-\r
EXTERN xdata _AT_(0xE6C4) volatile BYTE GPIFADRH ; // GPIF Address H\r
-\r
EXTERN xdata _AT_(0xE6C5) volatile BYTE GPIFADRL ; // GPIF Address L\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE6CE) volatile BYTE GPIFTCB3 ; // GPIF Transaction Count Byte 3\r
-\r
EXTERN xdata _AT_(0xE6CF) volatile BYTE GPIFTCB2 ; // GPIF Transaction Count Byte 2\r
-\r
EXTERN xdata _AT_(0xE6D0) volatile BYTE GPIFTCB1 ; // GPIF Transaction Count Byte 1\r
-\r
EXTERN xdata _AT_(0xE6D1) volatile BYTE GPIFTCB0 ; // GPIF Transaction Count Byte 0\r
\r
-\r
-\r
#define EP2GPIFTCH GPIFTCB1 // these are here for backwards compatibility\r
-\r
#define EP2GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)\r
-\r
#define EP4GPIFTCH GPIFTCB1 // these are here for backwards compatibility\r
-\r
#define EP4GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)\r
-\r
#define EP6GPIFTCH GPIFTCB1 // these are here for backwards compatibility\r
-\r
#define EP6GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)\r
-\r
#define EP8GPIFTCH GPIFTCB1 // these are here for backwards compatibility\r
-\r
#define EP8GPIFTCL GPIFTCB0 // before REVE silicon (ie. REVB and REVD)\r
\r
-\r
-\r
// EXTERN xdata volatile BYTE EP2GPIFTCH _AT_ 0xE6D0; // EP2 GPIF Transaction Count High\r
-\r
// EXTERN xdata volatile BYTE EP2GPIFTCL _AT_ 0xE6D1; // EP2 GPIF Transaction Count Low\r
-\r
EXTERN xdata _AT_(0xE6D2) volatile BYTE EP2GPIFFLGSEL ; // EP2 GPIF Flag select\r
-\r
EXTERN xdata _AT_(0xE6D3) volatile BYTE EP2GPIFPFSTOP ; // Stop GPIF EP2 transaction on prog. flag\r
-\r
EXTERN xdata _AT_(0xE6D4) volatile BYTE EP2GPIFTRIG ; // EP2 FIFO Trigger\r
-\r
// EXTERN xdata volatile BYTE EP4GPIFTCH _AT_ 0xE6D8; // EP4 GPIF Transaction Count High\r
-\r
// EXTERN xdata volatile BYTE EP4GPIFTCL _AT_ 0xE6D9; // EP4 GPIF Transactionr Count Low\r
-\r
EXTERN xdata _AT_(0xE6DA) volatile BYTE EP4GPIFFLGSEL ; // EP4 GPIF Flag select\r
-\r
EXTERN xdata _AT_(0xE6DB) volatile BYTE EP4GPIFPFSTOP ; // Stop GPIF EP4 transaction on prog. flag\r
-\r
EXTERN xdata _AT_(0xE6DC) volatile BYTE EP4GPIFTRIG ; // EP4 FIFO Trigger\r
-\r
// EXTERN xdata volatile BYTE EP6GPIFTCH _AT_ 0xE6E0; // EP6 GPIF Transaction Count High\r
-\r
// EXTERN xdata volatile BYTE EP6GPIFTCL _AT_ 0xE6E1; // EP6 GPIF Transaction Count Low\r
-\r
EXTERN xdata _AT_(0xE6E2) volatile BYTE EP6GPIFFLGSEL ; // EP6 GPIF Flag select\r
-\r
EXTERN xdata _AT_(0xE6E3) volatile BYTE EP6GPIFPFSTOP ; // Stop GPIF EP6 transaction on prog. flag\r
-\r
EXTERN xdata _AT_(0xE6E4) volatile BYTE EP6GPIFTRIG ; // EP6 FIFO Trigger\r
-\r
// EXTERN xdata volatile BYTE EP8GPIFTCH _AT_ 0xE6E8; // EP8 GPIF Transaction Count High\r
-\r
// EXTERN xdata volatile BYTE EP8GPIFTCL _AT_ 0xE6E9; // EP8GPIF Transaction Count Low\r
-\r
EXTERN xdata _AT_(0xE6EA) volatile BYTE EP8GPIFFLGSEL ; // EP8 GPIF Flag select\r
-\r
EXTERN xdata _AT_(0xE6EB) volatile BYTE EP8GPIFPFSTOP ; // Stop GPIF EP8 transaction on prog. flag\r
-\r
EXTERN xdata _AT_(0xE6EC) volatile BYTE EP8GPIFTRIG ; // EP8 FIFO Trigger\r
-\r
EXTERN xdata _AT_(0xE6F0) volatile BYTE XGPIFSGLDATH ; // GPIF Data H (16-bit mode only)\r
-\r
EXTERN xdata _AT_(0xE6F1) volatile BYTE XGPIFSGLDATLX ; // Read/Write GPIF Data L & trigger transac\r
-\r
EXTERN xdata _AT_(0xE6F2) volatile BYTE XGPIFSGLDATLNOX ; // Read GPIF Data L, no transac trigger\r
-\r
EXTERN xdata _AT_(0xE6F3) volatile BYTE GPIFREADYCFG ; // Internal RDY,Sync/Async, RDY5CFG\r
-\r
EXTERN xdata _AT_(0xE6F4) volatile BYTE GPIFREADYSTAT ; // RDY pin states\r
-\r
EXTERN xdata _AT_(0xE6F5) volatile BYTE GPIFABORT ; // Abort GPIF cycles\r
\r
-\r
-\r
// UDMA\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE6C6) volatile BYTE FLOWSTATE ; //Defines GPIF flow state\r
-\r
EXTERN xdata _AT_(0xE6C7) volatile BYTE FLOWLOGIC ; //Defines flow/hold decision criteria\r
-\r
EXTERN xdata _AT_(0xE6C8) volatile BYTE FLOWEQ0CTL ; //CTL states during active flow state\r
-\r
EXTERN xdata _AT_(0xE6C9) volatile BYTE FLOWEQ1CTL ; //CTL states during hold flow state\r
-\r
EXTERN xdata _AT_(0xE6CA) volatile BYTE FLOWHOLDOFF ;\r
-\r
EXTERN xdata _AT_(0xE6CB) volatile BYTE FLOWSTB ; //CTL/RDY Signal to use as master data strobe \r
-\r
EXTERN xdata _AT_(0xE6CC) volatile BYTE FLOWSTBEDGE ; //Defines active master strobe edge\r
-\r
EXTERN xdata _AT_(0xE6CD) volatile BYTE FLOWSTBHPERIOD ; //Half Period of output master strobe\r
-\r
EXTERN xdata _AT_(0xE60C) volatile BYTE GPIFHOLDAMOUNT ; //Data delay shift \r
-\r
EXTERN xdata _AT_(0xE67D) volatile BYTE UDMACRCH ; //CRC Upper byte\r
-\r
EXTERN xdata _AT_(0xE67E) volatile BYTE UDMACRCL ; //CRC Lower byte\r
-\r
EXTERN xdata _AT_(0xE67F) volatile BYTE UDMACRCQUAL ; //UDMA In only, host terminated use only\r
\r
\r
-\r
-\r
-\r
// Debug/Test\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE6F8) volatile BYTE DBUG ; // Debug\r
-\r
EXTERN xdata _AT_(0xE6F9) volatile BYTE TESTCFG ; // Test configuration\r
-\r
EXTERN xdata _AT_(0xE6FA) volatile BYTE USBTEST ; // USB Test Modes\r
-\r
EXTERN xdata _AT_(0xE6FB) volatile BYTE CT1 ; // Chirp Test--Override\r
-\r
EXTERN xdata _AT_(0xE6FC) volatile BYTE CT2 ; // Chirp Test--FSM\r
-\r
EXTERN xdata _AT_(0xE6FD) volatile BYTE CT3 ; // Chirp Test--Control Signals\r
-\r
EXTERN xdata _AT_(0xE6FE) volatile BYTE CT4 ; // Chirp Test--Inputs\r
\r
-\r
-\r
// Endpoint Buffers\r
\r
-\r
-\r
EXTERN xdata _AT_(0xE740) volatile BYTE EP0BUF[64] ; // EP0 IN-OUT buffer\r
-\r
EXTERN xdata _AT_(0xE780) volatile BYTE EP1OUTBUF[64] ; // EP1-OUT buffer\r
-\r
EXTERN xdata _AT_(0xE7C0) volatile BYTE EP1INBUF[64] ; // EP1-IN buffer\r
-\r
EXTERN xdata _AT_(0xF000) volatile BYTE EP2FIFOBUF[1024] ; // 512/1024-byte EP2 buffer (IN or OUT)\r
-\r
EXTERN xdata _AT_(0xF400) volatile BYTE EP4FIFOBUF[1024] ; // 512 byte EP4 buffer (IN or OUT)\r
-\r
EXTERN xdata _AT_(0xF800) volatile BYTE EP6FIFOBUF[1024] ; // 512/1024-byte EP6 buffer (IN or OUT)\r
-\r
EXTERN xdata _AT_(0xFC00) volatile BYTE EP8FIFOBUF[1024] ; // 512 byte EP8 buffer (IN or OUT)\r
\r
-\r
-\r
#undef EXTERN\r
-\r
#undef _AT_\r
\r
-\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
Special Function Registers (SFRs)\r
-\r
The byte registers and bits defined in the following list are based\r
-\r
on the Synopsis definition of the 8051 Special Function Registers for EZ-USB. \r
-\r
If you modify the register definitions below, please regenerate the file \r
-\r
"ezregs.inc" which includes the same basic information for assembly inclusion.\r
-\r
-----------------------------------------------------------------------------*/\r
\r
-\r
-\r
sfr at 0x80 IOA;\r
-\r
sfr at 0x81 SP;\r
-\r
sfr at 0x82 DPL;\r
-\r
sfr at 0x83 DPH;\r
-\r
sfr at 0x84 DPL1;\r
-\r
sfr at 0x85 DPH1;\r
-\r
sfr at 0x86 DPS;\r
-\r
/* DPS */\r
-\r
sbit at 0x86+0 SEL;\r
-\r
sfr at 0x87 PCON; /* PCON */\r
-\r
//sbit IDLE = 0x87+0;\r
-\r
//sbit STOP = 0x87+1;\r
-\r
//sbit GF0 = 0x87+2;\r
-\r
//sbit GF1 = 0x87+3;\r
-\r
//sbit SMOD0 = 0x87+7;\r
-\r
sfr at 0x88 TCON;\r
-\r
/* TCON */\r
-\r
sbit at 0x88+0 IT0;\r
-\r
sbit at 0x88+1 IE0;\r
-\r
sbit at 0x88+2 IT1;\r
-\r
sbit at 0x88+3 IE1;\r
-\r
sbit at 0x88+4 TR0;\r
-\r
sbit at 0x88+5 TF0;\r
-\r
sbit at 0x88+6 TR1;\r
-\r
sbit at 0x88+7 TF1;\r
-\r
sfr at 0x89 TMOD;\r
-\r
/* TMOD */\r
-\r
//sbit M00 = 0x89+0;\r
-\r
//sbit M10 = 0x89+1;\r
-\r
//sbit CT0 = 0x89+2;\r
-\r
//sbit GATE0 = 0x89+3;\r
-\r
//sbit M01 = 0x89+4;\r
-\r
//sbit M11 = 0x89+5;\r
-\r
//sbit CT1 = 0x89+6;\r
-\r
//sbit GATE1 = 0x89+7;\r
-\r
sfr at 0x8A TL0;\r
-\r
sfr at 0x8B TL1;\r
-\r
sfr at 0x8C TH0;\r
-\r
sfr at 0x8D TH1;\r
-\r
sfr at 0x8E CKCON;\r
-\r
/* CKCON */\r
-\r
//sbit MD0 = 0x89+0;\r
-\r
//sbit MD1 = 0x89+1;\r
-\r
//sbit MD2 = 0x89+2;\r
-\r
//sbit T0M = 0x89+3;\r
-\r
//sbit T1M = 0x89+4;\r
-\r
//sbit T2M = 0x89+5;\r
-\r
// sfr at 0x8F SPC_FNC; // Was WRS in Reg320\r
-\r
/* CKCON */\r
-\r
//sbit WRS = 0x8F+0;\r
-\r
sfr at 0x90 IOB;\r
-\r
sfr at 0x91 EXIF; // EXIF Bit Values differ from Reg320\r
-\r
/* EXIF */\r
-\r
//sbit USBINT = 0x91+4;\r
-\r
//sbit I2CINT = 0x91+5;\r
-\r
//sbit IE4 = 0x91+6;\r
-\r
//sbit IE5 = 0x91+7;\r
-\r
sfr at 0x92 MPAGE;\r
-\r
sfr at 0x98 SCON0;\r
-\r
/* SCON0 */\r
-\r
sbit at 0x98+0 RI;\r
-\r
sbit at 0x98+1 TI;\r
-\r
sbit at 0x98+2 RB8;\r
-\r
sbit at 0x98+3 TB8;\r
-\r
sbit at 0x98+4 REN;\r
-\r
sbit at 0x98+5 SM2;\r
-\r
sbit at 0x98+6 SM1;\r
-\r
sbit at 0x98+7 SM0;\r
-\r
sfr at 0x99 SBUF0;\r
\r
-\r
-\r
sfr at 0x9A APTR1H;\r
-\r
sfr at 0x9B APTR1L;\r
-\r
sfr at 0x9C AUTODAT1; \r
-\r
sfr at 0x9D AUTOPTRH2;\r
-\r
sfr at 0x9E AUTOPTRL2; \r
-\r
sfr at 0x9F AUTODAT2;\r
-\r
sfr at 0xA0 IOC;\r
-\r
sfr at 0xA1 INT2CLR;\r
-\r
sfr at 0xA2 INT4CLR;\r
\r
-\r
-\r
#define AUTOPTRH1 APTR1H\r
-\r
#define AUTOPTRL1 APTR1L\r
\r
-\r
-\r
sfr at 0xA8 IE;\r
-\r
/* IE */\r
-\r
sbit at 0xA8+0 EX0;\r
-\r
sbit at 0xA8+1 ET0;\r
-\r
sbit at 0xA8+2 EX1;\r
-\r
sbit at 0xA8+3 ET1;\r
-\r
sbit at 0xA8+4 ES0;\r
-\r
sbit at 0xA8+5 ET2;\r
-\r
sbit at 0xA8+6 ES1;\r
-\r
sbit at 0xA8+7 EA;\r
\r
-\r
-\r
sfr at 0xAA EP2468STAT;\r
-\r
/* EP2468STAT */\r
-\r
//sbit EP2E = 0xAA+0;\r
-\r
//sbit EP2F = 0xAA+1;\r
-\r
//sbit EP4E = 0xAA+2;\r
-\r
//sbit EP4F = 0xAA+3;\r
-\r
//sbit EP6E = 0xAA+4;\r
-\r
//sbit EP6F = 0xAA+5;\r
-\r
//sbit EP8E = 0xAA+6;\r
-\r
//sbit EP8F = 0xAA+7;\r
\r
-\r
-\r
sfr at 0xAB EP24FIFOFLGS;\r
-\r
sfr at 0xAC EP68FIFOFLGS;\r
-\r
sfr at 0xAF AUTOPTRSETUP;\r
-\r
/* AUTOPTRSETUP */\r
-\r
sbit at 0xAF+0 EXTACC;\r
-\r
sbit at 0xAF+1 APTR1FZ;\r
-\r
sbit at 0xAF+2 APTR2FZ;\r
\r
-\r
-\r
sfr at 0xB0 IOD;\r
-\r
sfr at 0xB1 IOE;\r
-\r
sfr at 0xB2 OEA;\r
-\r
sfr at 0xB3 OEB;\r
-\r
sfr at 0xB4 OEC;\r
-\r
sfr at 0xB5 OED;\r
-\r
sfr at 0xB6 OEE;\r
\r
-\r
-\r
sfr at 0xB8 IP;\r
-\r
/* IP */\r
-\r
sbit at 0xB8+0 PX0;\r
-\r
sbit at 0xB8+1 PT0;\r
-\r
sbit at 0xB8+2 PX1;\r
-\r
sbit at 0xB8+3 PT1;\r
-\r
sbit at 0xB8+4 PS0;\r
-\r
sbit at 0xB8+5 PT2;\r
-\r
sbit at 0xB8+6 PS1;\r
\r
-\r
-\r
sfr at 0xBA EP01STAT;\r
-\r
sfr at 0xBB GPIFTRIG;\r
-\r
\r
-\r
sfr at 0xBD GPIFSGLDATH;\r
-\r
sfr at 0xBE GPIFSGLDATLX;\r
-\r
sfr at 0xBF GPIFSGLDATLNOX;\r
\r
-\r
-\r
sfr at 0xC0 SCON1;\r
-\r
/* SCON1 */\r
-\r
sbit at 0xC0+0 RI1;\r
-\r
sbit at 0xC0+1 TI1;\r
-\r
sbit at 0xC0+2 RB81;\r
-\r
sbit at 0xC0+3 TB81;\r
-\r
sbit at 0xC0+4 REN1;\r
-\r
sbit at 0xC0+5 SM21;\r
-\r
sbit at 0xC0+6 SM11;\r
-\r
sbit at 0xC0+7 SM01;\r
-\r
sfr at 0xC1 SBUF1;\r
-\r
sfr at 0xC8 T2CON;\r
-\r
/* T2CON */\r
-\r
sbit at 0xC8+0 CP_RL2;\r
-\r
sbit at 0xC8+1 C_T2;\r
-\r
sbit at 0xC8+2 TR2;\r
-\r
sbit at 0xC8+3 EXEN2;\r
-\r
sbit at 0xC8+4 TCLK;\r
-\r
sbit at 0xC8+5 RCLK;\r
-\r
sbit at 0xC8+6 EXF2;\r
-\r
sbit at 0xC8+7 TF2;\r
-\r
sfr at 0xCA RCAP2L;\r
-\r
sfr at 0xCB RCAP2H;\r
-\r
sfr at 0xCC TL2;\r
-\r
sfr at 0xCD TH2;\r
-\r
sfr at 0xD0 PSW;\r
-\r
/* PSW */\r
-\r
sbit at 0xD0+0 P;\r
-\r
sbit at 0xD0+1 FL;\r
-\r
sbit at 0xD0+2 OV;\r
-\r
sbit at 0xD0+3 RS0;\r
-\r
sbit at 0xD0+4 RS1;\r
-\r
sbit at 0xD0+5 F0;\r
-\r
sbit at 0xD0+6 AC;\r
-\r
sbit at 0xD0+7 CY;\r
-\r
sfr at 0xD8 EICON; // Was WDCON in DS80C320 EICON; Bit Values differ from Reg320\r
-\r
/* EICON */\r
-\r
sbit at 0xD8+3 INT6;\r
-\r
sbit at 0xD8+4 RESI;\r
-\r
sbit at 0xD8+5 ERESI;\r
-\r
sbit at 0xD8+7 SMOD1;\r
-\r
sfr at 0xE0 ACC;\r
-\r
sfr at 0xE8 EIE; // EIE Bit Values differ from Reg320\r
-\r
/* EIE */\r
-\r
sbit at 0xE8+0 EIUSB;\r
-\r
sbit at 0xE8+1 EI2C;\r
-\r
sbit at 0xE8+2 EIEX4;\r
-\r
sbit at 0xE8+3 EIEX5;\r
-\r
sbit at 0xE8+4 EIEX6;\r
-\r
sfr at 0xF0 B;\r
-\r
sfr at 0xF8 EIP; // EIP Bit Values differ from Reg320\r
-\r
/* EIP */\r
-\r
sbit at 0xF8+0 PUSB;\r
-\r
sbit at 0xF8+1 PI2C;\r
-\r
sbit at 0xF8+2 EIPX4;\r
-\r
sbit at 0xF8+3 EIPX5;\r
-\r
sbit at 0xF8+4 EIPX6;\r
\r
-\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
Bit Masks\r
-\r
-----------------------------------------------------------------------------*/\r
\r
-\r
-\r
#define bmBIT0 1\r
-\r
#define bmBIT1 2\r
-\r
#define bmBIT2 4\r
-\r
#define bmBIT3 8\r
-\r
#define bmBIT4 16\r
-\r
#define bmBIT5 32\r
-\r
#define bmBIT6 64\r
-\r
#define bmBIT7 128\r
\r
-\r
-\r
/* CPU Control & Status Register (CPUCS) */\r
-\r
#define bmPRTCSTB bmBIT5\r
-\r
#define bmCLKSPD (bmBIT4 | bmBIT3)\r
-\r
#define bmCLKSPD1 bmBIT4\r
-\r
#define bmCLKSPD0 bmBIT3\r
-\r
#define bmCLKINV bmBIT2\r
-\r
#define bmCLKOE bmBIT1\r
-\r
#define bm8051RES bmBIT0\r
-\r
/* Port Alternate Configuration Registers */\r
-\r
/* Port A (PORTACFG) */\r
-\r
#define bmFLAGD bmBIT7\r
-\r
#define bmINT1 bmBIT1\r
-\r
#define bmINT0 bmBIT0\r
-\r
/* Port C (PORTCCFG) */\r
-\r
#define bmGPIFA7 bmBIT7\r
-\r
#define bmGPIFA6 bmBIT6\r
-\r
#define bmGPIFA5 bmBIT5\r
-\r
#define bmGPIFA4 bmBIT4\r
-\r
#define bmGPIFA3 bmBIT3\r
-\r
#define bmGPIFA2 bmBIT2\r
-\r
#define bmGPIFA1 bmBIT1\r
-\r
#define bmGPIFA0 bmBIT0\r
-\r
/* Port E (PORTECFG) */\r
-\r
#define bmGPIFA8 bmBIT7\r
-\r
#define bmT2EX bmBIT6\r
-\r
#define bmINT6 bmBIT5\r
-\r
#define bmRXD1OUT bmBIT4\r
-\r
#define bmRXD0OUT bmBIT3\r
-\r
#define bmT2OUT bmBIT2\r
-\r
#define bmT1OUT bmBIT1\r
-\r
#define bmT0OUT bmBIT0\r
\r
-\r
-\r
/* I2C Control & Status Register (I2CS) */\r
-\r
#define bmSTART bmBIT7\r
-\r
#define bmSTOP bmBIT6\r
-\r
#define bmLASTRD bmBIT5\r
-\r
#define bmID (bmBIT4 | bmBIT3)\r
-\r
#define bmBERR bmBIT2\r
-\r
#define bmACK bmBIT1\r
-\r
#define bmDONE bmBIT0\r
-\r
/* I2C Control Register (I2CTL) */\r
-\r
#define bmSTOPIE bmBIT1\r
-\r
#define bm400KHZ bmBIT0\r
-\r
/* Interrupt 2 (USB) Autovector Register (INT2IVEC) */\r
-\r
#define bmIV4 bmBIT6\r
-\r
#define bmIV3 bmBIT5\r
-\r
#define bmIV2 bmBIT4\r
-\r
#define bmIV1 bmBIT3\r
-\r
#define bmIV0 bmBIT2\r
-\r
/* USB Interrupt Request & Enable Registers (USBIE/USBIRQ) */\r
-\r
#define bmEP0ACK bmBIT6\r
-\r
#define bmHSGRANT bmBIT5\r
-\r
#define bmURES bmBIT4\r
-\r
#define bmSUSP bmBIT3\r
-\r
#define bmSUTOK bmBIT2\r
-\r
#define bmSOF bmBIT1\r
-\r
#define bmSUDAV bmBIT0\r
-\r
/* Breakpoint register (BREAKPT) */\r
-\r
#define bmBREAK bmBIT3\r
-\r
#define bmBPPULSE bmBIT2\r
-\r
#define bmBPEN bmBIT1\r
-\r
/* Interrupt 2 & 4 Setup (INTSETUP) */\r
-\r
#define bmAV2EN bmBIT3\r
-\r
#define bmINT4IN bmBIT1\r
-\r
#define bmAV4EN bmBIT0\r
-\r
/* USB Control & Status Register (USBCS) */\r
-\r
#define bmHSM bmBIT7\r
-\r
#define bmDISCON bmBIT3\r
-\r
#define bmNOSYNSOF bmBIT2\r
-\r
#define bmRENUM bmBIT1\r
-\r
#define bmSIGRESUME bmBIT0\r
-\r
/* Wakeup Control and Status Register (WAKEUPCS) */\r
-\r
#define bmWU2 bmBIT7\r
-\r
#define bmWU bmBIT6\r
-\r
#define bmWU2POL bmBIT5\r
-\r
#define bmWUPOL bmBIT4\r
-\r
#define bmDPEN bmBIT2\r
-\r
#define bmWU2EN bmBIT1\r
-\r
#define bmWUEN bmBIT0\r
-\r
/* End Point 0 Control & Status Register (EP0CS) */\r
-\r
#define bmHSNAK bmBIT7\r
-\r
/* End Point 0-1 Control & Status Registers (EP0CS/EP1OUTCS/EP1INCS) */\r
-\r
#define bmEPBUSY bmBIT1\r
-\r
#define bmEPSTALL bmBIT0\r
-\r
/* End Point 2-8 Control & Status Registers (EP2CS/EP4CS/EP6CS/EP8CS) */\r
-\r
#define bmNPAK (bmBIT6 | bmBIT5 | bmBIT4)\r
-\r
#define bmEPFULL bmBIT3\r
-\r
#define bmEPEMPTY bmBIT2\r
-\r
/* Endpoint Status (EP2468STAT) SFR bits */\r
-\r
#define bmEP8FULL bmBIT7\r
-\r
#define bmEP8EMPTY bmBIT6\r
-\r
#define bmEP6FULL bmBIT5\r
-\r
#define bmEP6EMPTY bmBIT4\r
-\r
#define bmEP4FULL bmBIT3\r
-\r
#define bmEP4EMPTY bmBIT2\r
-\r
#define bmEP2FULL bmBIT1\r
-\r
#define bmEP2EMPTY bmBIT0\r
-\r
/* SETUP Data Pointer Auto Mode (SUDPTRCTL) */\r
-\r
#define bmSDPAUTO bmBIT0\r
-\r
/* Endpoint Data Toggle Control (TOGCTL) */\r
-\r
#define bmQUERYTOGGLE bmBIT7\r
-\r
#define bmSETTOGGLE bmBIT6\r
-\r
#define bmRESETTOGGLE bmBIT5\r
-\r
#define bmTOGCTLEPMASK bmBIT3 | bmBIT2 | bmBIT1 | bmBIT0\r
-\r
/* IBN (In Bulk Nak) enable and request bits (IBNIE/IBNIRQ) */\r
-\r
#define bmEP8IBN bmBIT5\r
-\r
#define bmEP6IBN bmBIT4\r
-\r
#define bmEP4IBN bmBIT3\r
-\r
#define bmEP2IBN bmBIT2\r
-\r
#define bmEP1IBN bmBIT1\r
-\r
#define bmEP0IBN bmBIT0\r
\r
-\r
-\r
/* PING-NAK enable and request bits (NAKIE/NAKIRQ) */\r
-\r
#define bmEP8PING bmBIT7\r
-\r
#define bmEP6PING bmBIT6\r
-\r
#define bmEP4PING bmBIT5\r
-\r
#define bmEP2PING bmBIT4\r
-\r
#define bmEP1PING bmBIT3\r
-\r
#define bmEP0PING bmBIT2\r
-\r
#define bmIBN bmBIT0\r
\r
-\r
-\r
/* Interface Configuration bits (IFCONFIG) */\r
-\r
#define bmIFCLKSRC bmBIT7 // set == INTERNAL\r
-\r
#define bm3048MHZ bmBIT6 // set == 48 MHz\r
-\r
#define bmIFCLKOE bmBIT5\r
-\r
#define bmIFCLKPOL bmBIT4\r
-\r
#define bmASYNC bmBIT3\r
-\r
#define bmGSTATE bmBIT2\r
-\r
#define bmIFCFG1 bmBIT1\r
-\r
#define bmIFCFG0 bmBIT0\r
-\r
#define bmIFCFGMASK (bmIFCFG0 | bmIFCFG1)\r
-\r
#define bmIFGPIF bmIFCFG1\r
\r
-\r
-\r
/* EP 2468 FIFO Configuration bits (EP2FIFOCFG,EP4FIFOCFG,EP6FIFOCFG,EP8FIFOCFG) */\r
-\r
#define bmINFM bmBIT6\r
-\r
#define bmOEP bmBIT5\r
-\r
#define bmAUTOOUT bmBIT4\r
-\r
#define bmAUTOIN bmBIT3\r
-\r
#define bmZEROLENIN bmBIT2\r
-\r
// must be zero bmBIT1\r
-\r
#define bmWORDWIDE bmBIT0\r
\r
-\r
-\r
/*\r
-\r
* Chip Revision Control Bits (REVCTL) - used to ebable/disable revision specific features\r
-\r
*/ \r
-\r
#define bmNOAUTOARM bmBIT1 // these don't match the docs\r
-\r
#define bmSKIPCOMMIT bmBIT0 // these don't match the docs\r
\r
-\r
-\r
#define bmDYN_OUT bmBIT1 // these do...\r
-\r
#define bmENH_PKT bmBIT0\r
\r
\r
-\r
-\r
-\r
/* Fifo Reset bits (FIFORESET) */\r
-\r
#define bmNAKALL bmBIT7\r
\r
-\r
-\r
/* Endpoint Configuration (EPxCFG) */\r
-\r
#define bmVALID bmBIT7\r
-\r
#define bmIN bmBIT6\r
-\r
#define bmTYPE1 bmBIT5\r
-\r
#define bmTYPE0 bmBIT4\r
-\r
#define bmISOCHRONOUS bmTYPE0\r
-\r
#define bmBULK bmTYPE1\r
-\r
#define bmINTERRUPT (bmTYPE1 | bmTYPE0)\r
-\r
#define bm1KBUF bmBIT3\r
-\r
#define bmBUF1 bmBIT1\r
-\r
#define bmBUF0 bmBIT0\r
-\r
#define bmQUADBUF 0\r
-\r
#define bmINVALIDBUF bmBUF0\r
-\r
#define bmDOUBLEBUF bmBUF1\r
-\r
#define bmTRIPLEBUF (bmBUF1 | bmBUF0)\r
\r
-\r
-\r
/* OUTPKTEND */\r
-\r
#define bmSKIP bmBIT7 // low 4 bits specify which end point\r
\r
-\r
-\r
/* GPIFTRIG defs */\r
-\r
#define bmGPIF_IDLE bmBIT7 // status bit\r
\r
-\r
-\r
#define bmGPIF_EP2_START 0\r
-\r
#define bmGPIF_EP4_START 1\r
-\r
#define bmGPIF_EP6_START 2\r
-\r
#define bmGPIF_EP8_START 3\r
-\r
#define bmGPIF_READ bmBIT2\r
-\r
#define bmGPIF_WRITE 0\r
\r
-\r
-\r
/* EXIF bits */\r
-\r
#define bmEXIF_USBINT bmBIT4\r
-\r
#define bmEXIF_I2CINT bmBIT5\r
-\r
#define bmEXIF_IE4 bmBIT6\r
-\r
#define bmEXIF_IE5 bmBIT7\r
\r
\r
-\r
-\r
-\r
#endif /* FX2REGS_H */\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* FX2 specific subroutines\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "fx2utils.h"\r
-\r
#include "fx2regs.h"\r
-\r
#include "delay.h"\r
\r
-\r
-\r
void\r
-\r
fx2_stall_ep0 (void)\r
-\r
{\r
-\r
EP0CS |= bmEPSTALL;\r
-\r
}\r
\r
-\r
-\r
void\r
-\r
fx2_reset_data_toggle (unsigned char ep)\r
-\r
{\r
-\r
TOGCTL = ((ep & 0x80) >> 3 | (ep & 0x0f));\r
-\r
TOGCTL |= bmRESETTOGGLE;\r
-\r
}\r
\r
-\r
-\r
void\r
-\r
fx2_renumerate (void)\r
-\r
{\r
-\r
USBCS |= bmDISCON | bmRENUM;\r
\r
-\r
-\r
// mdelay (1500); // FIXME why 1.5 seconds?\r
-\r
mdelay (250); // FIXME why 1.5 seconds?\r
-\r
\r
-\r
USBIRQ = 0xff; // clear any pending USB irqs...\r
-\r
EPIRQ = 0xff; // they're from before the renumeration\r
\r
-\r
-\r
EXIF &= ~bmEXIF_USBINT;\r
\r
-\r
-\r
USBCS &= ~bmDISCON; // reconnect USB\r
-\r
}\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* FX2 specific subroutines\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _FX2UTILS_H_\r
-\r
#define _FX2UTILS_H_\r
\r
-\r
-\r
void fx2_stall_ep0 (void);\r
-\r
void fx2_reset_data_toggle (unsigned char ep);\r
-\r
void fx2_renumerate (void);\r
\r
\r
\r
-\r
-\r
-\r
-\r
#endif /* _FX2UTILS_H_ */\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* I2C read/write functions for FX2\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "i2c.h"\r
-\r
#include "fx2regs.h"\r
-\r
#include <string.h>\r
\r
\r
-\r
-\r
-\r
// issue a stop bus cycle and wait for completion\r
\r
\r
-\r
-\r
-\r
// returns non-zero if successful, else 0\r
-\r
unsigned char\r
-\r
i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len)\r
-\r
{\r
-\r
volatile unsigned char junk;\r
-\r
\r
-\r
if (len == 0) // reading zero bytes always works\r
-\r
return 1;\r
-\r
\r
-\r
while (I2CS & bmSTOP) // wait for stop to clear\r
-\r
;\r
\r
-\r
-\r
I2CS = bmSTART;\r
-\r
I2DAT = (addr << 1) | 1; // write address and direction (1's the read bit)\r
\r
-\r
-\r
while ((I2CS & bmDONE) == 0)\r
-\r
;\r
\r
-\r
-\r
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...\r
-\r
goto fail;\r
\r
-\r
-\r
if (len == 1)\r
-\r
I2CS |= bmLASTRD; \r
\r
-\r
-\r
junk = I2DAT; // trigger the first read cycle\r
\r
-\r
-\r
while (--len != 0){\r
-\r
while ((I2CS & bmDONE) == 0)\r
-\r
;\r
\r
-\r
-\r
if (I2CS & bmBERR)\r
-\r
goto fail;\r
\r
-\r
-\r
if (len == 1)\r
-\r
I2CS |= bmLASTRD;\r
-\r
\r
-\r
*buf++ = I2DAT; // get data, trigger another read\r
-\r
}\r
\r
-\r
-\r
// wait for final byte\r
-\r
\r
-\r
while ((I2CS & bmDONE) == 0)\r
-\r
;\r
-\r
\r
-\r
if (I2CS & bmBERR)\r
-\r
goto fail;\r
\r
-\r
-\r
I2CS |= bmSTOP;\r
-\r
*buf = I2DAT;\r
\r
-\r
-\r
return 1;\r
\r
-\r
-\r
fail:\r
-\r
I2CS |= bmSTOP;\r
-\r
return 0;\r
-\r
}\r
\r
\r
\r
-\r
-\r
-\r
-\r
// returns non-zero if successful, else 0\r
-\r
unsigned char\r
-\r
i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len)\r
-\r
{\r
-\r
while (I2CS & bmSTOP) // wait for stop to clear\r
-\r
;\r
\r
-\r
-\r
I2CS = bmSTART;\r
-\r
I2DAT = (addr << 1) | 0; // write address and direction (0's the write bit)\r
\r
-\r
-\r
while ((I2CS & bmDONE) == 0)\r
-\r
;\r
\r
-\r
-\r
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...\r
-\r
goto fail;\r
\r
-\r
-\r
while (len > 0){\r
-\r
I2DAT = *buf++;\r
-\r
len--;\r
\r
-\r
-\r
while ((I2CS & bmDONE) == 0)\r
-\r
;\r
\r
-\r
-\r
if ((I2CS & bmBERR) || (I2CS & bmACK) == 0) // no device answered...\r
-\r
goto fail;\r
-\r
}\r
\r
-\r
-\r
I2CS |= bmSTOP;\r
-\r
return 1;\r
\r
-\r
-\r
fail:\r
-\r
I2CS |= bmSTOP;\r
-\r
return 0;\r
-\r
}\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* I2C read/write functions for FX2\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _I2C_H_\r
-\r
#define _I2C_H_\r
\r
-\r
-\r
// returns non-zero if successful, else 0\r
-\r
unsigned char i2c_read (unsigned char addr, xdata unsigned char *buf, unsigned char len);\r
\r
-\r
-\r
// returns non-zero if successful, else 0\r
-\r
unsigned char i2c_write (unsigned char addr, xdata const unsigned char *buf, unsigned char len);\r
\r
-\r
-\r
#endif /* _I2C_H_ */\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Interrupt handling for FX2\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "isr.h"\r
-\r
#include "fx2regs.h"\r
-\r
#include "syncdelay.h"\r
\r
-\r
-\r
extern xdata unsigned char _standard_interrupt_vector[];\r
-\r
extern xdata unsigned char _usb_autovector[];\r
-\r
extern xdata unsigned char _fifo_gpif_autovector[];\r
\r
-\r
-\r
#define LJMP_OPCODE 0x02\r
\r
-\r
-\r
/*\r
-\r
* Hook standard interrupt vector.\r
-\r
*\r
-\r
* vector_number is from the SV_<foo> list.\r
-\r
* addr is the address of the interrupt service routine.\r
-\r
*/\r
-\r
void \r
-\r
hook_sv (unsigned char vector_number, unsigned short addr)\r
-\r
{\r
-\r
bit t;\r
-\r
\r
-\r
// sanity checks\r
\r
-\r
-\r
if (vector_number < SV_MIN || vector_number > SV_MAX)\r
-\r
return;\r
\r
-\r
-\r
if ((vector_number & 0x0f) != 0x03 && (vector_number & 0x0f) != 0x0b)\r
-\r
return;\r
\r
-\r
-\r
t = EA;\r
-\r
EA = 0;\r
-\r
_standard_interrupt_vector[vector_number] = LJMP_OPCODE;\r
-\r
_standard_interrupt_vector[vector_number + 1] = addr >> 8;\r
-\r
_standard_interrupt_vector[vector_number + 2] = addr & 0xff;\r
-\r
EA = t;\r
-\r
}\r
\r
-\r
-\r
/*\r
-\r
* Hook usb interrupt vector.\r
-\r
*\r
-\r
* vector_number is from the UV_<foo> list.\r
-\r
* addr is the address of the interrupt service routine.\r
-\r
*/\r
-\r
void \r
-\r
hook_uv (unsigned char vector_number, unsigned short addr)\r
-\r
{\r
-\r
bit t;\r
-\r
\r
-\r
// sanity checks\r
\r
-\r
-\r
#if UV_MIN>0\r
-\r
if (vector_number < UV_MIN) return;\r
-\r
#endif\r
-\r
if (vector_number > UV_MAX)\r
-\r
return;\r
\r
-\r
-\r
if ((vector_number & 0x3) != 0)\r
-\r
return;\r
\r
-\r
-\r
t = EA;\r
-\r
EA = 0;\r
-\r
_usb_autovector[vector_number] = LJMP_OPCODE;\r
-\r
_usb_autovector[vector_number + 1] = addr >> 8;\r
-\r
_usb_autovector[vector_number + 2] = addr & 0xff;\r
-\r
EA = t;\r
-\r
}\r
\r
-\r
-\r
/*\r
-\r
* Hook fifo/gpif interrupt vector.\r
-\r
*\r
-\r
* vector_number is from the FGV_<foo> list.\r
-\r
* addr is the address of the interrupt service routine.\r
-\r
*/\r
-\r
void \r
-\r
hook_fgv (unsigned char vector_number, unsigned short addr)\r
-\r
{\r
-\r
bit t;\r
-\r
\r
-\r
// sanity checks\r
\r
-\r
-\r
if (vector_number < FGV_MIN || vector_number > FGV_MAX)\r
-\r
return;\r
\r
-\r
-\r
if ((vector_number & 0x3) != 0)\r
-\r
return;\r
\r
-\r
-\r
t = EA;\r
-\r
EA = 0;\r
-\r
_fifo_gpif_autovector[vector_number] = LJMP_OPCODE;\r
-\r
_fifo_gpif_autovector[vector_number + 1] = addr >> 8;\r
-\r
_fifo_gpif_autovector[vector_number + 2] = addr & 0xff;\r
-\r
EA = t;\r
-\r
}\r
\r
-\r
-\r
/*\r
-\r
* One time call to enable autovectoring for both USB and FIFO/GPIF.\r
-\r
*\r
-\r
* This disables all USB and FIFO/GPIF interrupts and clears\r
-\r
* any pending interrupts too. It leaves the master USB and FIFO/GPIF\r
-\r
* interrupts enabled.\r
-\r
*/\r
-\r
void\r
-\r
setup_autovectors (void)\r
-\r
{\r
-\r
// disable master usb and fifo/gpif interrupt enables\r
-\r
EIUSB = 0;\r
-\r
EIEX4 = 0;\r
\r
-\r
-\r
hook_sv (SV_INT_2, (unsigned short) _usb_autovector);\r
-\r
hook_sv (SV_INT_4, (unsigned short) _fifo_gpif_autovector);\r
\r
-\r
-\r
// disable all fifo interrupt enables\r
-\r
SYNCDELAY;\r
-\r
EP2FIFOIE = 0; SYNCDELAY;\r
-\r
EP4FIFOIE = 0; SYNCDELAY;\r
-\r
EP6FIFOIE = 0; SYNCDELAY;\r
-\r
EP8FIFOIE = 0; SYNCDELAY;\r
\r
-\r
-\r
// clear all pending fifo irqs \r
-\r
EP2FIFOIRQ = 0xff; SYNCDELAY;\r
-\r
EP4FIFOIRQ = 0xff; SYNCDELAY;\r
-\r
EP6FIFOIRQ = 0xff; SYNCDELAY;\r
-\r
EP8FIFOIRQ = 0xff; SYNCDELAY;\r
\r
-\r
-\r
IBNIE = 0;\r
-\r
IBNIRQ = 0xff;\r
-\r
NAKIE = 0;\r
-\r
NAKIRQ = 0xff;\r
-\r
USBIE = 0;\r
-\r
USBIRQ = 0xff;\r
-\r
EPIE = 0;\r
-\r
EPIRQ = 0xff;\r
-\r
SYNCDELAY; GPIFIE = 0; \r
-\r
SYNCDELAY; GPIFIRQ = 0xff;\r
-\r
USBERRIE = 0;\r
-\r
USBERRIRQ = 0xff;\r
-\r
CLRERRCNT = 0;\r
-\r
\r
-\r
INTSETUP = bmAV2EN | bmAV4EN | bmINT4IN;\r
\r
-\r
-\r
// clear master irq's for usb and fifo/gpif\r
-\r
EXIF &= ~bmEXIF_USBINT;\r
-\r
EXIF &= ~bmEXIF_IE4;\r
-\r
\r
-\r
// enable master usb and fifo/gpif interrrupts\r
-\r
EIUSB = 1;\r
-\r
EIEX4 = 1;\r
-\r
}\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Synchronization delay for FX2 access to specific registers\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _SYNCDELAY_H_\r
-\r
#define _SYNCDELAY_H_\r
\r
-\r
-\r
/*\r
-\r
* Magic delay required between access to certain xdata registers (TRM page 15-106).\r
-\r
* For our configuration, 48 MHz FX2 / 48 MHz IFCLK, we need three cycles. Each\r
-\r
* NOP is a single cycle....\r
-\r
*\r
-\r
* From TRM page 15-105:\r
-\r
*\r
-\r
* Under certain conditions, some read and write access to the FX2 registers must\r
-\r
* be separated by a "synchronization delay". The delay is necessary only under the\r
-\r
* following conditions:\r
-\r
*\r
-\r
* - between a write to any register in the 0xE600 - 0xE6FF range and a write to one\r
-\r
* of the registers listed below.\r
-\r
*\r
-\r
* - between a write to one of the registers listed below and a read from any register\r
-\r
* in the 0xE600 - 0xE6FF range.\r
-\r
*\r
-\r
* Registers which require a synchronization delay:\r
-\r
*\r
-\r
* FIFORESET FIFOPINPOLAR\r
-\r
* INPKTEND EPxBCH:L\r
-\r
* EPxFIFOPFH:L EPxAUTOINLENH:L\r
-\r
* EPxFIFOCFG EPxGPIFFLGSEL\r
-\r
* PINFLAGSAB PINFLAGSCD\r
-\r
* EPxFIFOIE EPxFIFOIRQ\r
-\r
* GPIFIE GPIFIRQ\r
-\r
* UDMACRCH:L GPIFADRH:L\r
-\r
* GPIFTRIG EPxGPIFTRIG\r
-\r
* OUTPKTEND REVCTL\r
-\r
* GPIFTCB3 GPIFTCB2\r
-\r
* GPIFTCB1 GPIFTCB0\r
-\r
*/\r
\r
-\r
-\r
/*\r
-\r
* FIXME ensure that the peep hole optimizer isn't screwing us\r
-\r
*/\r
-\r
#define SYNCDELAY _asm nop; nop; nop; _endasm\r
-\r
#define NOP _asm nop; _endasm\r
\r
\r
-\r
-\r
-\r
#endif /* _SYNCDELAY_H_ */\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Timer handling for FX2\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "timer.h"\r
-\r
#include "fx2regs.h"\r
-\r
#include "isr.h"\r
\r
-\r
-\r
/*\r
-\r
* Arrange to have isr_tick_handler called at 100 Hz.\r
-\r
*\r
-\r
* The cpu clock is running at 48e6. The input to the timer\r
-\r
* is 48e6 / 12 = 4e6.\r
-\r
*\r
-\r
* We arrange to have the timer overflow every 40000 clocks == 100 Hz\r
-\r
*/\r
\r
-\r
-\r
#define RELOAD_VALUE ((unsigned short) -40000)\r
\r
-\r
-\r
void \r
-\r
hook_timer_tick (unsigned short isr_tick_handler)\r
-\r
{\r
-\r
ET2 = 0; // disable timer 2 interrupts\r
-\r
hook_sv (SV_TIMER_2, isr_tick_handler);\r
-\r
\r
-\r
RCAP2H = RELOAD_VALUE >> 8; // setup the auto reload value\r
-\r
RCAP2L = RELOAD_VALUE & 0xFF;\r
\r
-\r
-\r
T2CON = 0x04; // interrupt on overflow; reload; run\r
-\r
ET2 = 1; // enable timer 2 interrupts\r
-\r
}\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Timer handling for FX2\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _TIMER_H_\r
-\r
#define _TIMER_H_\r
\r
-\r
-\r
/*\r
-\r
* Arrange to have isr_tick_handler called at 100 Hz\r
-\r
*/\r
-\r
void hook_timer_tick (unsigned short isr_tick_handler);\r
\r
-\r
-\r
#define clear_timer_irq() \\r
TF2 = 0 /* clear overflow flag */\r
\r
\r
-\r
-\r
-\r
#endif /* _TIMER_H_ */\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Common USB code for FX2\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "usb_common.h"\r
-\r
#include "fx2regs.h"\r
-\r
#include "syncdelay.h"\r
-\r
#include "fx2utils.h"\r
-\r
#include "isr.h"\r
-\r
#include "usb_descriptors.h"\r
-\r
#include "usb_requests.h"\r
\r
-\r
-\r
extern xdata char str0[];\r
-\r
extern xdata char str1[];\r
-\r
extern xdata char str2[];\r
-\r
extern xdata char str3[];\r
-\r
extern xdata char str4[];\r
-\r
extern xdata char str5[];\r
\r
-\r
-\r
volatile bit _usb_got_SUDAV;\r
\r
-\r
-\r
unsigned char _usb_config = 0;\r
-\r
unsigned char _usb_alt_setting = 0; // FIXME really 1/interface\r
\r
-\r
-\r
xdata unsigned char *current_device_descr;\r
-\r
xdata unsigned char *current_devqual_descr;\r
-\r
xdata unsigned char *current_config_descr;\r
-\r
xdata unsigned char *other_config_descr;\r
\r
-\r
-\r
static void\r
-\r
setup_descriptors (void)\r
-\r
{\r
-\r
if (USBCS & bmHSM){ // high speed mode\r
-\r
current_device_descr = high_speed_device_descr;\r
-\r
current_devqual_descr = high_speed_devqual_descr;\r
-\r
current_config_descr = high_speed_config_descr;\r
-\r
other_config_descr = full_speed_config_descr;\r
-\r
EP8AUTOINLENH = 0x02; SYNCDELAY; // Size in bytes of the IN data automatically commited (512 bytes here)\r
-\r
EP8AUTOINLENL = 0x00; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet\r
-\r
}\r
-\r
else {\r
-\r
current_device_descr = full_speed_device_descr;\r
-\r
current_devqual_descr = full_speed_devqual_descr;\r
-\r
current_config_descr = full_speed_config_descr;\r
-\r
other_config_descr = high_speed_config_descr;\r
-\r
EP8AUTOINLENH = 0x00; SYNCDELAY; // Size in bytes of the IN data automatically commited (64 bytes here)\r
-\r
EP8AUTOINLENL = 0x40; SYNCDELAY; // Can use signal PKTEND if you want to commit a shorter packet\r
-\r
}\r
\r
-\r
-\r
// whack the type fields\r
-\r
// FIXME, may not be required.\r
-\r
// current_config_descr[1] = DT_CONFIG;\r
-\r
// other_config_descr[1] = DT_OTHER_SPEED;\r
-\r
}\r
\r
-\r
-\r
static void\r
-\r
isr_SUDAV (void) interrupt\r
-\r
{\r
-\r
clear_usb_irq ();\r
-\r
_usb_got_SUDAV = 1;\r
-\r
}\r
\r
-\r
-\r
static void\r
-\r
isr_USBRESET (void) interrupt\r
-\r
{\r
-\r
clear_usb_irq ();\r
-\r
setup_descriptors ();\r
-\r
}\r
\r
-\r
-\r
static void\r
-\r
isr_HIGHSPEED (void) interrupt\r
-\r
{\r
-\r
clear_usb_irq ();\r
-\r
setup_descriptors ();\r
-\r
}\r
\r
-\r
-\r
void\r
-\r
usb_install_handlers (void)\r
-\r
{\r
-\r
setup_descriptors (); // ensure that they're set before use\r
\r
-\r
-\r
hook_uv (UV_SUDAV, (unsigned short) isr_SUDAV);\r
-\r
hook_uv (UV_USBRESET, (unsigned short) isr_USBRESET);\r
-\r
hook_uv (UV_HIGHSPEED, (unsigned short) isr_HIGHSPEED);\r
\r
-\r
-\r
USBIE = bmSUDAV | bmURES | bmHSGRANT;\r
-\r
}\r
\r
-\r
-\r
// On the FX2 the only plausible endpoints are 0, 1, 2, 4, 6, 8\r
-\r
// This doesn't check to see that they're enabled\r
\r
-\r
-\r
unsigned char\r
-\r
plausible_endpoint (unsigned char ep)\r
-\r
{\r
-\r
ep &= ~0x80; // ignore direction bit\r
\r
-\r
-\r
if (ep > 8)\r
-\r
return 0;\r
\r
-\r
-\r
if (ep == 1)\r
-\r
return 1;\r
\r
-\r
-\r
return (ep & 0x1) == 0; // must be even\r
-\r
}\r
\r
-\r
-\r
// return pointer to control and status register for endpoint.\r
-\r
// only called with plausible_endpoints\r
\r
-\r
-\r
xdata volatile unsigned char *\r
-\r
epcs (unsigned char ep)\r
-\r
{\r
-\r
if (ep == 0x01) // ep1 has different in and out CS regs\r
-\r
return EP1OUTCS;\r
\r
-\r
-\r
if (ep == 0x81)\r
-\r
return EP1INCS;\r
\r
-\r
-\r
ep &= ~0x80; // ignore direction bit\r
\r
-\r
-\r
if (ep == 0x00) // ep0\r
-\r
return EP0CS;\r
\r
-\r
-\r
return EP2CS + (ep >> 1); // 2, 4, 6, 8 are consecutive\r
-\r
}\r
\r
-\r
-\r
void\r
-\r
usb_handle_setup_packet (void)\r
-\r
{\r
-\r
_usb_got_SUDAV = 0;\r
\r
-\r
-\r
// handle the standard requests...\r
\r
-\r
-\r
switch (bRequestType & bmRT_TYPE_MASK){\r
\r
-\r
-\r
case bmRT_TYPE_CLASS:\r
-\r
case bmRT_TYPE_RESERVED:\r
-\r
fx2_stall_ep0 (); // we don't handle these. indicate error\r
-\r
break;\r
-\r
\r
-\r
case bmRT_TYPE_VENDOR:\r
-\r
// call the application code.\r
-\r
// If it handles the command it returns non-zero\r
\r
-\r
-\r
if (!app_vendor_cmd ()) \r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
\r
-\r
-\r
case bmRT_TYPE_STD:\r
-\r
// these are the standard requests...\r
\r
-\r
-\r
if ((bRequestType & bmRT_DIR_MASK) == bmRT_DIR_IN){\r
\r
-\r
-\r
////////////////////////////////////\r
-\r
// handle the IN requests\r
-\r
////////////////////////////////////\r
\r
-\r
-\r
switch (bRequest){\r
\r
-\r
-\r
case RQ_GET_CONFIG:\r
-\r
EP0BUF[0] = _usb_config; // FIXME app should handle\r
-\r
EP0BCH = 0;\r
-\r
EP0BCL = 1;\r
-\r
break;\r
-\r
\r
-\r
// --------------------------------\r
\r
-\r
-\r
case RQ_GET_INTERFACE:\r
-\r
EP0BUF[0] = _usb_alt_setting; // FIXME app should handle\r
-\r
EP0BCH = 0;\r
-\r
EP0BCL = 1;\r
-\r
break;\r
\r
-\r
-\r
// --------------------------------\r
\r
-\r
-\r
case RQ_GET_DESCR:\r
-\r
switch (wValueH){\r
\r
-\r
-\r
case DT_DEVICE:\r
-\r
SUDPTRH = MSB (current_device_descr);\r
-\r
SUDPTRL = LSB (current_device_descr);\r
-\r
break;\r
-\r
\r
-\r
case DT_DEVQUAL:\r
-\r
SUDPTRH = MSB (current_devqual_descr);\r
-\r
SUDPTRL = LSB (current_devqual_descr);\r
-\r
break;\r
\r
-\r
-\r
case DT_CONFIG:\r
-\r
if (0 && wValueL != 1) // FIXME only a single configuration\r
-\r
fx2_stall_ep0 ();\r
-\r
else {\r
-\r
SUDPTRH = MSB (current_config_descr);\r
-\r
SUDPTRL = LSB (current_config_descr);\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
case DT_OTHER_SPEED:\r
-\r
if (0 && wValueL != 1) // FIXME only a single configuration\r
-\r
fx2_stall_ep0 ();\r
-\r
else {\r
-\r
SUDPTRH = MSB (other_config_descr);\r
-\r
SUDPTRL = LSB (other_config_descr);\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
case DT_STRING:\r
-\r
if (wValueL >= nstring_descriptors)\r
-\r
fx2_stall_ep0 ();\r
-\r
else {\r
-\r
xdata char *p = string_descriptors[wValueL];\r
-\r
SUDPTRH = MSB (p);\r
-\r
SUDPTRL = LSB (p);\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
default:\r
-\r
fx2_stall_ep0 (); // invalid request\r
-\r
break;\r
-\r
}\r
-\r
break;\r
-\r
\r
-\r
// --------------------------------\r
\r
-\r
-\r
case RQ_GET_STATUS:\r
-\r
switch (bRequestType & bmRT_RECIP_MASK){\r
-\r
case bmRT_RECIP_DEVICE:\r
-\r
EP0BUF[0] = 0;\r
-\r
EP0BUF[1] = 0;\r
-\r
EP0BCH = 0;\r
-\r
EP0BCL = 2;\r
-\r
break;\r
\r
-\r
-\r
case bmRT_RECIP_INTERFACE:\r
-\r
EP0BUF[0] = 0;\r
-\r
EP0BUF[1] = 0;\r
-\r
EP0BCH = 0;\r
-\r
EP0BCL = 2;\r
-\r
break;\r
\r
-\r
-\r
case bmRT_RECIP_ENDPOINT:\r
-\r
if (plausible_endpoint (wIndexL)){\r
-\r
EP0BUF[0] = *epcs (wIndexL) & bmEPSTALL;\r
-\r
EP0BUF[1] = 0;\r
-\r
EP0BCH = 0;\r
-\r
EP0BCL = 2;\r
-\r
}\r
-\r
else\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
\r
-\r
-\r
default:\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
// --------------------------------\r
\r
-\r
-\r
case RQ_SYNCH_FRAME: // not implemented\r
-\r
default:\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
-\r
}\r
-\r
}\r
\r
-\r
-\r
else {\r
\r
-\r
-\r
////////////////////////////////////\r
-\r
// handle the OUT requests\r
-\r
////////////////////////////////////\r
\r
-\r
-\r
switch (bRequest){\r
\r
-\r
-\r
case RQ_SET_CONFIG:\r
-\r
IOE &= ~(1 << 6);\r
-\r
_usb_config = wValueL; // FIXME app should handle\r
-\r
break;\r
\r
-\r
-\r
case RQ_SET_INTERFACE:\r
-\r
_usb_alt_setting = wValueL; // FIXME app should handle\r
-\r
break;\r
\r
-\r
-\r
// --------------------------------\r
\r
-\r
-\r
case RQ_CLEAR_FEATURE:\r
-\r
switch (bRequestType & bmRT_RECIP_MASK){\r
\r
-\r
-\r
case bmRT_RECIP_DEVICE:\r
-\r
switch (wValueL){\r
-\r
case FS_DEV_REMOTE_WAKEUP:\r
-\r
default:\r
-\r
fx2_stall_ep0 ();\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
case bmRT_RECIP_ENDPOINT:\r
-\r
if (wValueL == FS_ENDPOINT_HALT && plausible_endpoint (wIndexL)){\r
-\r
*epcs (wIndexL) &= ~bmEPSTALL;\r
-\r
fx2_reset_data_toggle (wIndexL);\r
-\r
}\r
-\r
else\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
\r
-\r
-\r
default:\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
// --------------------------------\r
\r
-\r
-\r
case RQ_SET_FEATURE:\r
-\r
switch (bRequestType & bmRT_RECIP_MASK){\r
\r
-\r
-\r
case bmRT_RECIP_DEVICE:\r
-\r
switch (wValueL){\r
-\r
case FS_TEST_MODE:\r
-\r
// hardware handles this after we complete SETUP phase handshake\r
-\r
break;\r
\r
-\r
-\r
case FS_DEV_REMOTE_WAKEUP:\r
-\r
default:\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
-\r
}\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
case bmRT_RECIP_ENDPOINT:\r
-\r
switch (wValueL){\r
-\r
case FS_ENDPOINT_HALT:\r
-\r
if (plausible_endpoint (wIndexL))\r
-\r
*epcs (wIndexL) |= bmEPSTALL;\r
-\r
else\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
\r
-\r
-\r
default:\r
-\r
fx2_stall_ep0 ();\r
-\r
break;\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
// --------------------------------\r
\r
-\r
-\r
case RQ_SET_ADDRESS: // handled by fx2 hardware\r
-\r
case RQ_SET_DESCR: // not implemented\r
-\r
default:\r
-\r
fx2_stall_ep0 ();\r
-\r
}\r
\r
-\r
-\r
}\r
-\r
break;\r
\r
-\r
-\r
} // bmRT_TYPE_MASK\r
\r
-\r
-\r
// ack handshake phase of device request\r
-\r
EP0CS |= bmHSNAK;\r
-\r
}\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Common USB code for FX2\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _USB_COMMON_H_\r
-\r
#define _USB_COMMON_H_\r
\r
-\r
-\r
#define bRequestType SETUPDAT[0]\r
-\r
#define bRequest SETUPDAT[1]\r
-\r
#define wValueL SETUPDAT[2]\r
-\r
#define wValueH SETUPDAT[3]\r
-\r
#define wIndexL SETUPDAT[4]\r
-\r
#define wIndexH SETUPDAT[5]\r
-\r
#define wLengthL SETUPDAT[6]\r
-\r
#define wLengthH SETUPDAT[7]\r
\r
-\r
-\r
#define MSB(x) (((unsigned short) x) >> 8)\r
-\r
#define LSB(x) (((unsigned short) x) & 0xff)\r
\r
-\r
-\r
extern volatile bit _usb_got_SUDAV;\r
\r
-\r
-\r
// Provided by user application to report device status.\r
-\r
// returns non-zero if it handled the command.\r
-\r
unsigned char app_get_status (void);\r
-\r
// Provided by user application to handle VENDOR commands.\r
-\r
// returns non-zero if it handled the command.\r
-\r
unsigned char app_vendor_cmd (void);\r
\r
-\r
-\r
void usb_install_handlers (void);\r
-\r
void usb_handle_setup_packet (void);\r
\r
-\r
-\r
#define usb_setup_packet_avail() _usb_got_SUDAV\r
\r
-\r
-\r
#endif /* _USB_COMMON_H_ */\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* USB descriptor references\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
extern xdata const char high_speed_device_descr[];\r
-\r
extern xdata const char high_speed_devqual_descr[];\r
-\r
extern xdata const char high_speed_config_descr[];\r
\r
-\r
-\r
extern xdata const char full_speed_device_descr[];\r
-\r
extern xdata const char full_speed_devqual_descr[];\r
-\r
extern xdata const char full_speed_config_descr[];\r
\r
-\r
-\r
extern xdata unsigned char nstring_descriptors;\r
-\r
extern xdata char * xdata string_descriptors[];\r
\r
-\r
-\r
/*\r
-\r
* We patch these locations with info read from the usrp config eeprom\r
-\r
*/\r
-\r
extern xdata char usb_desc_hw_rev_binary_patch_location_0[];\r
-\r
extern xdata char usb_desc_hw_rev_binary_patch_location_1[];\r
-\r
extern xdata char usb_desc_hw_rev_ascii_patch_location_0[];\r
-\r
extern xdata char usb_desc_serial_number_ascii[];\r
-\r
/* -*- c++ -*- */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* USB request definitions\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
* Copyright 2003 Free Software Foundation, Inc.\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
// Standard USB requests.\r
-\r
// These are contained in end point 0 setup packets\r
\r
\r
-\r
-\r
-\r
#ifndef _USB_REQUESTS_H_\r
-\r
#define _USB_REQUESTS_H_\r
\r
-\r
-\r
// format of bmRequestType byte\r
\r
-\r
-\r
#define bmRT_DIR_MASK (0x1 << 7)\r
-\r
#define bmRT_DIR_IN (1 << 7)\r
-\r
#define bmRT_DIR_OUT (0 << 7)\r
\r
-\r
-\r
#define bmRT_TYPE_MASK (0x3 << 5)\r
-\r
#define bmRT_TYPE_STD (0 << 5)\r
-\r
#define bmRT_TYPE_CLASS (1 << 5)\r
-\r
#define bmRT_TYPE_VENDOR (2 << 5)\r
-\r
#define bmRT_TYPE_RESERVED (3 << 5)\r
\r
-\r
-\r
#define bmRT_RECIP_MASK (0x1f << 0)\r
-\r
#define bmRT_RECIP_DEVICE (0 << 0)\r
-\r
#define bmRT_RECIP_INTERFACE (1 << 0)\r
-\r
#define bmRT_RECIP_ENDPOINT (2 << 0)\r
-\r
#define bmRT_RECIP_OTHER (3 << 0)\r
\r
\r
-\r
-\r
-\r
// standard request codes (bRequest)\r
\r
-\r
-\r
#define RQ_GET_STATUS 0\r
-\r
#define RQ_CLEAR_FEATURE 1\r
-\r
#define RQ_RESERVED_2 2\r
-\r
#define RQ_SET_FEATURE 3\r
-\r
#define RQ_RESERVED_4 4\r
-\r
#define RQ_SET_ADDRESS 5\r
-\r
#define RQ_GET_DESCR 6\r
-\r
#define RQ_SET_DESCR 7\r
-\r
#define RQ_GET_CONFIG 8\r
-\r
#define RQ_SET_CONFIG 9\r
-\r
#define RQ_GET_INTERFACE 10\r
-\r
#define RQ_SET_INTERFACE 11\r
-\r
#define RQ_SYNCH_FRAME 12\r
\r
-\r
-\r
// standard descriptor types\r
\r
-\r
-\r
#define DT_DEVICE 1\r
-\r
#define DT_CONFIG 2\r
-\r
#define DT_STRING 3\r
-\r
#define DT_INTERFACE 4\r
-\r
#define DT_ENDPOINT 5\r
-\r
#define DT_DEVQUAL 6\r
-\r
#define DT_OTHER_SPEED 7\r
-\r
#define DT_INTERFACE_POWER 8\r
\r
-\r
-\r
// standard feature selectors\r
\r
-\r
-\r
#define FS_ENDPOINT_HALT 0 // recip: endpoint\r
-\r
#define FS_DEV_REMOTE_WAKEUP 1 // recip: device\r
-\r
#define FS_TEST_MODE 2 // recip: device\r
\r
-\r
-\r
// Get Status device attributes\r
\r
-\r
-\r
#define bmGSDA_SELF_POWERED 0x01\r
-\r
#define bmGSDA_REM_WAKEUP 0x02\r
\r
\r
-\r
-\r
-\r
#endif /* _USB_REQUESTS_H_ */\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Hardware-dependent code for usb_jtag\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Copyright (C) 2007 Kolja Waschk, ixo.de\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#ifndef _HARDWARE_H\r
-\r
#define _HARDWARE_H 1\r
\r
-\r
-\r
extern void ProgIO_Init(void);\r
-\r
extern void ProgIO_Poll(void);\r
-\r
extern void ProgIO_Enable(void);\r
-\r
extern void ProgIO_Disable(void);\r
-\r
extern void ProgIO_Deinit(void);\r
\r
-\r
-\r
extern void ProgIO_Set_State(unsigned char d);\r
-\r
extern unsigned char ProgIO_Set_Get_State(unsigned char d);\r
-\r
extern void ProgIO_ShiftOut(unsigned char x);\r
-\r
extern unsigned char ProgIO_ShiftInOut(unsigned char x);\r
\r
-\r
-\r
#endif /* _HARDWARE_H */\r
\r
-\r
-\r
#include "delay.h"\r
\r
//-----------------------------------------------------------------------------\r
+// comment out (undefine!) if you don't want PS, AS or OE signals\r
\r
#define HAVE_PS_MODE 1\r
#define HAVE_AS_MODE 1\r
#define HAVE_OE_LED 1\r
\r
+// comment in (define!) if you want outputs disabled when possible\r
+//#define HAVE_OENABLE 1\r
+\r
//-----------------------------------------------------------------------------\r
\r
/* JTAG TCK, AS/PS DCLK */\r
\r
-sbit at 0xA2 TCK; /* Port C.0 */\r
+sbit at 0xA2 TCK; /* Port C.2 */\r
#define bmTCKOE bmBIT2\r
#define SetTCK(x) do{TCK=(x);}while(0)\r
\r
/* JTAG TDI, AS ASDI, PS DATA0 */\r
\r
-sbit at 0xA0 TDI; /* Port C.2 */\r
+sbit at 0xA0 TDI; /* Port C.0 */\r
#define bmTDIOE bmBIT0\r
#define SetTDI(x) do{TDI=(x);}while(0)\r
\r
#define GetTDO(x) TDO\r
\r
/* JTAG ENABLE */\r
-sbit JTAG_EN = 0xA0+7;\r
+sbit JTAG_EN = 0xA7; /* Port C.7 */\r
#define bmJTAG_EN bmBIT7\r
\r
//-----------------------------------------------------------------------------\r
#else\r
\r
#define bmASDOOE 0\r
- #define GetASDO(x) 0\r
+ #define GetASDO(x) 1\r
\r
#endif\r
\r
/* The following code depends on your actual circuit design.\r
Make required changes _before_ you try the code! */\r
\r
+ // set the CPU clock to 48MHz, enable clock output to FPGA\r
+ CPUCS = bmCLKOE | bmCLKSPD1;\r
+\r
+ // put the system in FIFO mode by default\r
+ // internal clock source at 48Mhz, drive output pin, synchronous mode\r
+ // NOTE: Altera USB-Blaster does not work in another mode\r
+ IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;\r
+ IFCONFIG |= bmASYNC | bmIFCFG1 | bmIFCFG0;\r
+\r
// set port C output enable (so we can handle the JTAG enable signal)\r
OEC = (1 << 7);\r
\r
// more than 100ma)\r
IOE = (1 << 6);\r
\r
- // set the CPU clock to 48MHz\r
- CPUCS = bmCLKSPD1;\r
-\r
// activate JTAG outputs on Port C\r
OEC = bmTDIOE | bmTCKOE | bmTMSOE | bmJTAG_EN;\r
-\r
- // put the system in FIFO mode by default\r
- // internal clock source at 48Mhz, drive output pin, synchronous mode\r
- // NOTE: Altera USB-Blaster does not work in another mode\r
- IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;\r
- IFCONFIG |= bmASYNC | bmIFCFG1 | bmIFCFG0;\r
}\r
\r
void ProgIO_Set_State(unsigned char d)\r
* d.2 => nCE (only #ifdef HAVE_AS_MODE)\r
* d.3 => nCS (only #ifdef HAVE_AS_MODE)\r
* d.4 => TDI\r
- * d.6 => LED / Output Enable\r
+ * d.5 => LED / Output Enable\r
*/\r
\r
SetTCK((d & bmBIT0) ? 1 : 0);\r
\r
unsigned char ProgIO_Set_Get_State(unsigned char d)\r
{\r
- ProgIO_Set_State(d);\r
-\r
- /* Read state of input pins:\r
+ /* Set state of output pins (s.a.)\r
+ * then read state of input pins:\r
*\r
* TDO => d.0\r
* DATAOUT => d.1 (only #ifdef HAVE_AS_MODE)\r
*/\r
\r
+ ProgIO_Set_State(d);\r
return (GetASDO()<<1)|GetTDO();\r
}\r
\r
/*-----------------------------------------------------------------------------\r
-\r
*\r
-\r
* Hardware-dependent code for usb_jtag\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Copyright (C) 2007 Kolja Waschk, ixo.de\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "hardware.h"\r
-\r
#include "fx2regs.h"\r
-\r
#include "syncdelay.h"\r
\r
-\r
-\r
//---------------------------------------------------------------------------\r
\r
-\r
-\r
#define SetTCK(x) do{if(x) IOE|=0x08; else IOE&=~0x08; }while(0)\r
-\r
#define SetTMS(x) do{if(x) IOE|=0x10; else IOE&=~0x10; }while(0)\r
-\r
#define SetTDI(x) do{if(x) IOE|=0x40; else IOE&=~0x40; }while(0)\r
-\r
#define GetTDO() ((IOE>>5)&1)\r
\r
-\r
-\r
/* XPCU has neither AS nor PS mode pins */\r
\r
-\r
-\r
#define HAVE_OE_LED 1\r
-\r
/* +0=green led, +1=red led */\r
-\r
sbit at 0x80+1 OELED;\r
-\r
#define SetOELED(x) do{OELED=(x);}while(0)\r
\r
-\r
-\r
//-----------------------------------------------------------------------------\r
\r
-\r
-\r
void ProgIO_Poll(void) {}\r
-\r
void ProgIO_Enable(void) {}\r
-\r
void ProgIO_Disable(void) {}\r
-\r
void ProgIO_Deinit(void) {}\r
\r
-\r
-\r
void ProgIO_Init(void)\r
-\r
{\r
-\r
/* The following code depends on your actual circuit design.\r
-\r
Make required changes _before_ you try the code! */\r
\r
-\r
-\r
// set the CPU clock to 48MHz, enable clock output to FPGA\r
-\r
CPUCS = bmCLKOE | bmCLKSPD1;\r
\r
-\r
-\r
// Use internal 48 MHz, enable output, use "Port" mode for all pins\r
-\r
IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE;\r
\r
-\r
-\r
GPIFABORT = 0xFF;\r
\r
-\r
-\r
PORTACFG = 0x00; OEA = 0x03; IOA=0x01;\r
-\r
PORTCCFG = 0x00; OEC = 0x00; IOC=0x00;\r
-\r
PORTECFG = 0x00; OEE = 0x58; IOE=0x00;\r
-\r
}\r
\r
-\r
-\r
void ProgIO_Set_State(unsigned char d)\r
-\r
{\r
-\r
- /* Set state of output pins:\r
-\r
+ /* Set state of output pins\r
+ * (d is the byte from the host):\r
*\r
-\r
* d.0 => TCK\r
-\r
* d.1 => TMS\r
-\r
* d.2 => nCE (only #ifdef HAVE_AS_MODE)\r
-\r
* d.3 => nCS (only #ifdef HAVE_AS_MODE)\r
-\r
* d.4 => TDI\r
-\r
* d.6 => LED / Output Enable\r
-\r
*/\r
\r
-\r
-\r
SetTCK((d & bmBIT0) ? 1 : 0);\r
-\r
SetTMS((d & bmBIT1) ? 1 : 0);\r
-\r
SetTDI((d & bmBIT4) ? 1 : 0);\r
-\r
#ifdef HAVE_OE_LED\r
-\r
SetOELED((d & bmBIT5) ? 1 : 0);\r
-\r
#endif\r
-\r
}\r
\r
-\r
-\r
unsigned char ProgIO_Set_Get_State(unsigned char d)\r
-\r
{\r
-\r
- /* Read state of input pins:\r
-\r
+ /* Set state of output pins (s.a.)\r
+ * then read state of input pins:\r
*\r
-\r
* TDO => d.0\r
-\r
* DATAOUT => d.1 (only #ifdef HAVE_AS_MODE)\r
-\r
*/\r
\r
-\r
-\r
ProgIO_Set_State(d);\r
-\r
- return 2|GetTDO();\r
-\r
+ return 2|GetTDO(); /* DATAOUT assumed high, no AS mode */\r
}\r
\r
-\r
-\r
void ProgIO_ShiftOut(unsigned char c)\r
-\r
{\r
-\r
/* Shift out byte C:\r
-\r
*\r
-\r
* 8x {\r
-\r
* Output least significant bit on TDI\r
-\r
* Raise TCK\r
-\r
* Shift c right\r
-\r
* Lower TCK\r
-\r
* }\r
-\r
*/\r
\r
-\r
-\r
unsigned char lc=c;\r
\r
-\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
\r
-\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
-\r
if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc>>=1; IOE&=~0x08;\r
-\r
}\r
\r
-\r
-\r
unsigned char ProgIO_ShiftInOut(unsigned char c)\r
-\r
{\r
-\r
/* Shift out byte C, shift in from TDO:\r
-\r
*\r
-\r
* 8x {\r
-\r
* Read carry from TDO\r
-\r
* Output least significant bit on TDI\r
-\r
* Raise TCK\r
-\r
- * Shift c right, append carry (TDO) at left\r
-\r
+ * Shift c right, append carry (TDO) at left (into MSB)\r
* Lower TCK\r
-\r
* }\r
-\r
* Return c.\r
-\r
*/\r
\r
-\r
-\r
unsigned char carry;\r
-\r
unsigned char lc=c;\r
\r
-\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
\r
-\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
-\r
carry = (IOE&0x20)<<2; if(lc&1) IOE|=0x40; else IOE&=~0x40; IOE|=0x08; lc=carry|(lc>>1); IOE&=~0x08;\r
\r
-\r
-\r
return lc;\r
-\r
}\r
\r
\r
-\r
-\r
-\r
/*-----------------------------------------------------------------------------\r
-\r
* Hardware-dependent code for usb_jtag\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* Copyright (C) 2007 Kolja Waschk, ixo.de\r
-\r
*-----------------------------------------------------------------------------\r
-\r
* This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
* it and/or modify it under the terms of the GNU General Public License as\r
-\r
* published by the Free Software Foundation; either version 2 of the License,\r
-\r
* or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
* that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
* warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
* GNU General Public License for more details. You should have received a\r
-\r
* copy of the GNU General Public License along with this program in the file\r
-\r
* COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
* St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
*-----------------------------------------------------------------------------\r
-\r
*/\r
\r
-\r
-\r
#include "delay.h"\r
-\r
#include "syncdelay.h"\r
-\r
#include "hardware.h"\r
\r
-\r
-\r
#include "isr.h"\r
-\r
#include "timer.h"\r
-\r
#include "delay.h"\r
-\r
#include "fx2regs.h"\r
-\r
#include "fx2utils.h"\r
-\r
#include "usb_common.h"\r
-\r
#include "usb_descriptors.h"\r
-\r
#include "usb_requests.h"\r
-\r
#include "syncdelay.h"\r
-\r
#include "eeprom.h"\r
\r
\r
\r
\r
void ProgIO_Poll(void) {}\r
-\r
void ProgIO_Enable(void) {}\r
-\r
void ProgiO_Disable(void) {}\r
-\r
void ProgiO_Deinit(void) {}\r
\r
-\r
-\r
static unsigned char curios;\r
\r
-\r
-\r
const unsigned char wavedata[64] =\r
-\r
{\r
-\r
/* Single Write:\r
-\r
s0: BITS=D0 NEXT/SGLCRC DATA WAIT 4\r
-\r
s1: BITS= DATA WAIT 4\r
-\r
s2: BITS=D1|D0 DATA WAIT 4\r
-\r
s3: BITS=D1 DATA WAIT 3\r
-\r
s4: BITS=D1 DATA DP IF(RDY0) THEN 5 ELSE 2\r
-\r
s5: BITS=D1|D0 DATA WAIT 4\r
-\r
s6: BITS=D1 DATA WAIT 3\r
-\r
s7: BITS=D1 DATA FIN */\r
\r
-\r
-\r
4, 4, 4, 3, 0x2A, 4, 3, 7,\r
-\r
6, 2, 2, 2, 3, 2, 2, 2,\r
-\r
1, 0, 3, 2, 2, 3, 2, 2,\r
-\r
0, 0, 0, 0, 0, 0, 0, 0x3F,\r
\r
-\r
-\r
/* Single Read:\r
-\r
s0: BITS=D0 WAIT 4\r
-\r
s1: BITS= WAIT 4\r
-\r
s2: BITS=D1|D0 WAIT 4\r
-\r
s3: BITS=D1 WAIT 4\r
-\r
s4: BITS=D1|D0 WAIT 3\r
-\r
s5: BITS=D1|D0 DP IF(RDY0) THEN 6 ELSE 3\r
-\r
s6: BITS=D1 DATA WAIT 4\r
-\r
s7: BITS=D1 FIN */\r
\r
-\r
-\r
4, 4, 4, 4, 3, 0x33, 4, 7,\r
-\r
0, 0, 0, 0, 0, 1, 2, 0,\r
-\r
1, 0, 3, 2, 3, 3, 2, 2,\r
-\r
0, 0, 0, 0, 0, 0, 0, 0x3F\r
-\r
};\r
\r
-\r
-\r
void ProgIO_Init(void)\r
-\r
{\r
-\r
unsigned char i;\r
\r
-\r
-\r
/* The following code depends on your actual circuit design.\r
-\r
Make required changes _before_ you try the code! */\r
\r
-\r
-\r
// set the CPU clock to 48MHz, enable clock output to FPGA\r
-\r
CPUCS = bmCLKOE | bmCLKSPD1;\r
\r
-\r
-\r
// Use internal 48 MHz, enable output, GPIF Master mode\r
-\r
IFCONFIG = bmIFCLKSRC | bm3048MHZ | bmIFCLKOE | bmIFGPIF;\r
\r
-\r
-\r
PORTACFG = 0x00; OEA = 0xFB; IOA = 0x20;\r
-\r
PORTCCFG = 0x00; OEC = 0xFF; IOC = 0x10;\r
-\r
PORTECFG = 0x00; OEE = 0xFC; IOE = 0xC0;\r
-\r
\r
-\r
GPIFABORT = 0xFF;\r
\r
-\r
-\r
GPIFREADYCFG = 0xA0;\r
-\r
GPIFCTLCFG = 0x00;\r
-\r
GPIFIDLECS = 0x00;\r
-\r
GPIFIDLECTL = 0x00;\r
-\r
GPIFWFSELECT = 0x01;\r
\r
-\r
-\r
// Copy waveform data\r
-\r
AUTOPTRSETUP = 0x07;\r
-\r
APTR1H = MSB( &wavedata );\r
-\r
APTR1L = LSB( &wavedata );\r
-\r
AUTOPTRH2 = 0xE4;\r
-\r
AUTOPTRL2 = 0x00;\r
-\r
for ( i = 0; i < 64; i++ ) EXTAUTODAT2 = EXTAUTODAT1;\r
\r
-\r
-\r
SYNCDELAY;\r
-\r
GPIFADRH = 0x00;\r
-\r
SYNCDELAY;\r
-\r
GPIFADRL = 0x00;\r
\r
-\r
-\r
FLOWSTATE = 0x00;\r
-\r
FLOWLOGIC = 0x00;\r
-\r
FLOWEQ0CTL = 0x00;\r
-\r
FLOWEQ1CTL = 0x00;\r
-\r
FLOWHOLDOFF = 0x00;\r
-\r
FLOWSTB = 0x00;\r
-\r
FLOWSTBEDGE = 0x00;\r
-\r
FLOWSTBHPERIOD = 0x00;\r
\r
-\r
-\r
curios = 0;\r
-\r
}\r
\r
-\r
-\r
unsigned char GetTDO(unsigned char r)\r
-\r
{\r
-\r
unsigned char x;\r
\r
-\r
-\r
IOC = 0x41;\r
-\r
while(!(GPIFTRIG & 0x80)); x = XGPIFSGLDATLX;\r
-\r
while(!(GPIFTRIG & 0x80)); x = XGPIFSGLDATLNOX;\r
\r
-\r
-\r
if(IOA & 0x20) IOA |= 0x40; else IOA &= ~0x40;\r
\r
-\r
-\r
return (x&1) ? r : 0;\r
-\r
}\r
\r
-\r
-\r
#define SetPins(x) while(!(GPIFTRIG & 0x80)); XGPIFSGLDATLX = (x)\r
\r
-\r
-\r
void ProgIO_Set_State(unsigned char d)\r
-\r
{\r
-\r
/* Set state of output pins:\r
-\r
*\r
-\r
* d.0 => TCK (PE.6)\r
-\r
* d.1 => TMS (PE.5)\r
-\r
* d.4 => TDI (PE.4)\r
-\r
* d.6 => LED / Output Enable\r
-\r
*/\r
\r
- \r
-\r
curios = (d & bmBIT0) ? 0x40 : 0; // TCK\r
-\r
curios |= (d & bmBIT1) ? 0x20 : 0; // TMS\r
-\r
curios |= (d & bmBIT4) ? 0x10 : 0; // TDI\r
\r
-\r
-\r
- IOC = 0x81;\r
-\r
+ IOC = 0x81; /* Select direction */\r
SetPins(curios);\r
\r
-\r
-\r
if(d & bmBIT6) IOA=(IOA&~3)|1; else IOA=(IOA&~3)|2;\r
-\r
}\r
\r
-\r
-\r
unsigned char ProgIO_Set_Get_State(unsigned char d)\r
-\r
{\r
\r
ProgIO_Set_State(d);\r
\r
-\r
-\r
/* Read state of input pins:\r
-\r
*\r
-\r
* TDO => d.0\r
-\r
* DATAOUT => d.1 (only #ifdef HAVE_AS_MODE)\r
-\r
*/\r
\r
-\r
-\r
return 2|GetTDO(0x01);\r
-\r
}\r
\r
\r
\r
void ProgIO_ShiftOut(unsigned char c)\r
-\r
{\r
-\r
unsigned char r,i;\r
-\r
unsigned char locios = curios & ~0x50;\r
\r
-\r
-\r
- IOC = 0x81;\r
-\r
-\r
+ IOC = 0x81; /* Select direction */\r
\r
for(i=0,r=1;i<8;i++)\r
-\r
{\r
-\r
unsigned char t = locios;\r
-\r
if(c & r) t |= 0x10;\r
-\r
SetPins(t);\r
-\r
SetPins(t|0x40);\r
-\r
r <<= 1;\r
-\r
SetPins(t);\r
-\r
};\r
\r
-\r
-\r
curios = locios;\r
-\r
}\r
\r
\r
-\r
-\r
-\r
unsigned char ProgIO_ShiftInOut(unsigned char c)\r
-\r
{\r
-\r
unsigned char r,i,n;\r
-\r
unsigned char locios = curios & ~0x50;\r
\r
-\r
-\r
for(i=0,r=1,n=0;i<8;i++)\r
-\r
{\r
-\r
unsigned char t = locios;\r
\r
-\r
-\r
n |= GetTDO(r);\r
\r
-\r
-\r
IOC = 0x81;\r
\r
if(c & r) t |= 0x10;\r
\r
SetPins(t);\r
-\r
SetPins(t|0x40);\r
-\r
r <<= 1;\r
-\r
SetPins(t);\r
-\r
};\r
\r
-\r
-\r
curios = locios;\r
-\r
return n;\r
-\r
}\r
\r
\r
-\r
-\r
-\r
;;; -*- asm -*-\r
-\r
;;;\r
-\r
;;;-----------------------------------------------------------------------------\r
-\r
;;; Startup code\r
-\r
;;;-----------------------------------------------------------------------------\r
-\r
;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
;;; Copyright 2003 Free Software Foundation, Inc.\r
-\r
;;;-----------------------------------------------------------------------------\r
-\r
;;; This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
;;; it and/or modify it under the terms of the GNU General Public License as\r
-\r
;;; published by the Free Software Foundation; either version 2 of the License,\r
-\r
;;; or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
;;; GNU General Public License for more details. You should have received a\r
-\r
;;; copy of the GNU General Public License along with this program in the file\r
-\r
;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
;;; St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
;;;-----------------------------------------------------------------------------\r
\r
-\r
-\r
;;; The default external memory initialization provided by sdcc is not\r
-\r
;;; appropriate to the FX2. This is derived from the sdcc code, but uses \r
-\r
;;; the FX2 specific _MPAGE sfr.\r
\r
\r
-\r
-\r
-\r
;; .area XISEG (XDATA) ; the initialized external data area\r
-\r
;; .area XINIT (CODE) ; the code space consts to init XISEG\r
-\r
.area XSEG (XDATA) ; zero initialized xdata\r
-\r
.area USBDESCSEG (XDATA) ; usb descriptors\r
\r
\r
-\r
- \r
-\r
.area CSEG (CODE)\r
\r
-\r
-\r
;; sfr that sets upper address byte of MOVX using @r0 or @r1\r
-\r
_MPAGE = 0x0092\r
\r
-\r
-\r
__sdcc_external_startup::\r
-\r
;; This system is now compiled with the --no-xinit-opt \r
-\r
;; which means that any initialized XDATA is handled\r
-\r
;; inline by code in the GSINIT segs emitted for each file.\r
-\r
;; \r
-\r
;; We zero XSEG and all of the internal ram to ensure \r
-\r
;; a known good state for uninitialized variables.\r
\r
-\r
-\r
; _mcs51_genRAMCLEAR() start\r
-\r
mov r0,#l_XSEG\r
-\r
mov a,r0\r
-\r
orl a,#(l_XSEG >> 8)\r
-\r
jz 00002$\r
-\r
mov r1,#((l_XSEG + 255) >> 8)\r
-\r
mov dptr,#s_XSEG\r
-\r
clr a\r
-\r
\r
-\r
00001$: movx @dptr,a\r
-\r
inc dptr\r
-\r
djnz r0,00001$\r
-\r
djnz r1,00001$\r
-\r
\r
-\r
;; We're about to clear internal memory. This will overwrite\r
-\r
;; the stack which contains our return address.\r
-\r
;; Pop our return address into DPH, DPL\r
-\r
00002$: pop dph\r
-\r
pop dpl\r
-\r
\r
-\r
;; R0 and A contain 0. This loop will execute 256 times.\r
-\r
;; \r
-\r
;; FWIW the first iteration writes direct address 0x00,\r
-\r
;; which is the location of r0. We get lucky, we're \r
-\r
;; writing the correct value (0)\r
-\r
\r
-\r
00003$: mov @r0,a\r
-\r
djnz r0,00003$\r
\r
-\r
-\r
push dpl ; restore our return address\r
-\r
push dph\r
\r
-\r
-\r
mov dpl,#0 ; indicate that data init is still required\r
-\r
ret\r
-\r
*/\r
\r
// The firmware version should be regularly updated.\r
-#define FWVERSION "4.1.0"\r
+#define FWVERSION "4.2.0"\r
\r
#include "isr.h"\r
#include "timer.h"\r
\r
if(!(EP2468STAT & bmEP2EMPTY) && (Pending < OUTBUFFER_LEN-0x3F))\r
{\r
- BYTE i, n = EP2BCL;\r
+ WORD i, n = EP2BCL|EP2BCH<<8;\r
\r
APTR1H = MSB( EP2FIFOBUF );\r
APTR1L = LSB( EP2FIFOBUF );\r
{\r
if(ClockBytes > 0)\r
{\r
- BYTE m;\r
+ WORD m;\r
\r
m = n-i;\r
if(ClockBytes < m) m = ClockBytes;\r
-:06000000020FA402006BD8\r
+:06000000020FF802006B84\r
:03000B0002006B85\r
:0300130002006B7D\r
:03001B0002006B75\r
:1001500002006B0002006B0002006B0002006B00EB\r
:1001600002006B0002006B0002006B0002006B00DB\r
:1001700002006B0002006B0002006B0002006B00CB\r
-:030FAC00020FAF82\r
-:030FC200020180A9\r
-:1001800012057B80FEC200E4F508F509F50AD201EC\r
-:10019000750B00750C0012077812077575CB637527\r
+:03100000021003D8\r
+:0310160002018054\r
+:100180001205CF80FEC200E4F508F509F50AD20198\r
+:10019000750B00750C001207CC1207C975CB63757F\r
:1001A000CAC0758E0075C804D2AFD2B0D2B190E685\r
:1001B0000B7403F00090E6047480F00090E6047481\r
:1001C00002F00090E6047404F00090E6047406F077\r
:10025000E6917480F00090E6957480F00043A080F1\r
:1002600090E6FBE0FA54FDF090E601E0FA54F7F076\r
:1002700022AA82850C827583E0EAF0050C0509E468\r
-:10028000B50902050A222000012212077490E6A295\r
+:10028000B50902050A22200001221207C890E6A241\r
:10029000E0FA30E10302031FE509450A60697AC00C\r
:1002A0007BE78B9D7AC07BE77B008A9E90E67C741F\r
:1002B00031F07460F0C3743E9509E4950A50107AE9\r
:10030000022BF0D2CF801830CF1590E7C07431F0B7\r
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:00000001FF\r
;;; -*- asm -*-\r
-\r
;;;\r
-\r
;;;-----------------------------------------------------------------------------\r
-\r
;;; Interrupt vectors\r
-\r
;;;-----------------------------------------------------------------------------\r
-\r
;;; Code taken from USRP2 firmware (GNU Radio Project), version 3.0.2,\r
-\r
;;; Copyright 2003 Free Software Foundation, Inc.\r
-\r
;;;-----------------------------------------------------------------------------\r
-\r
;;; This code is part of usbjtag. usbjtag is free software; you can redistribute\r
-\r
;;; it and/or modify it under the terms of the GNU General Public License as\r
-\r
;;; published by the Free Software Foundation; either version 2 of the License,\r
-\r
;;; or (at your option) any later version. usbjtag is distributed in the hope\r
-\r
;;; that it will be useful, but WITHOUT ANY WARRANTY; without even the implied\r
-\r
;;; warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the\r
-\r
;;; GNU General Public License for more details. You should have received a\r
-\r
;;; copy of the GNU General Public License along with this program in the file\r
-\r
;;; COPYING; if not, write to the Free Software Foundation, Inc., 51 Franklin\r
-\r
;;; St, Fifth Floor, Boston, MA 02110-1301 USA\r
-\r
;;;-----------------------------------------------------------------------------\r
\r
-\r
-\r
;;; N.B. This object module must come first in the list of modules\r
\r
-\r
-\r
.module vectors\r
\r
-\r
-\r
;;; ----------------------------------------------------------------\r
-\r
;;; standard FX2 interrupt vectors\r
-\r
;;; ----------------------------------------------------------------\r
\r
-\r
-\r
.area CSEG (CODE)\r
-\r
.area GSINIT (CODE)\r
-\r
.area CSEG (CODE)\r
-\r
__standard_interrupt_vector::\r
-\r
__reset_vector::\r
-\r
ljmp s_GSINIT\r
-\r
\r
-\r
;; 13 8-byte entries. We point them all at __isr_nop\r
-\r
ljmp __isr_nop ; 3 bytes\r
-\r
.ds 5 ; + 5 = 8 bytes for vector slot\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
-\r
ljmp __isr_nop\r
-\r
.ds 5\r
\r
-\r
-\r
__isr_nop::\r
-\r
reti\r
\r
-\r
-\r
;;; ----------------------------------------------------------------\r
-\r
;;; the FIFO/GPIF autovector. 14 4-byte entries.\r
-\r
;;; must start on a 128 byte boundary.\r
-\r
;;; ----------------------------------------------------------------\r
-\r
\r
-\r
. = __reset_vector + 0x0080\r
-\r
\r
-\r
__fifo_gpif_autovector::\r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
-\r
ljmp __isr_nop\r
-\r
nop \r
\r
-\r
-\r
\r
-\r
;;; ----------------------------------------------------------------\r
-\r
;;; the USB autovector. 32 4-byte entries.\r
-\r
;;; must start on a 256 byte boundary.\r
-\r
;;; ----------------------------------------------------------------\r
\r
-\r
-\r
. = __reset_vector + 0x0100\r
-\r
\r
-\r
__usb_autovector::\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
ljmp __isr_nop\r
-\r
nop\r
-\r
projects / fx2fw-sdcc / commitdiff