target/fw/layer1: Add support for the various TCH multi frame tasks

Signed-off-by: Sylvain Munaut <tnt@246tNt.com>

diff --git a/src/target/firmware/include/layer1/mframe_sched.h b/src/target/firmware/include/layer1/mframe_sched.h
index 5e71dac..fa94422 100644 (file)
--- a/src/target/firmware/include/layer1/mframe_sched.h
+++ b/src/target/firmware/include/layer1/mframe_sched.h
@@ -23,6 +23,11 @@ enum mframe_task {
        MF_TASK_SDCCH8_6,
        MF_TASK_SDCCH8_7,
 
+       MF_TASK_TCH_F_EVEN,
+       MF_TASK_TCH_F_ODD,
+       MF_TASK_TCH_H_0,
+       MF_TASK_TCH_H_1,
+
        /* Test task: send Normal Burst in all timeslots */
        MF_TASK_UL_ALL_NB,
 };

diff --git a/src/target/firmware/layer1/l23_api.c b/src/target/firmware/layer1/l23_api.c
index 0aa5b1a..f6a2a9c 100644 (file)
--- a/src/target/firmware/layer1/l23_api.c
+++ b/src/target/firmware/layer1/l23_api.c
@@ -56,14 +56,15 @@ void l1_queue_for_l2(struct msgb *msg)
 static enum mframe_task chan_nr2mf_task(uint8_t chan_nr)
 {
        uint8_t cbits = chan_nr >> 3;
+       uint8_t tn = chan_nr & 0x7;
        uint8_t lch_idx;
 
        if (cbits == 0x01) {
                lch_idx = 0;
-               /* FIXME: TCH/F */
+               return (tn & 1) ? MF_TASK_TCH_F_ODD : MF_TASK_TCH_F_EVEN;
        } else if ((cbits & 0x1e) == 0x02) {
                lch_idx = cbits & 0x1;
-               /* FIXME: TCH/H */
+               return MF_TASK_TCH_H_0 + lch_idx;
        } else if ((cbits & 0x1c) == 0x04) {
                lch_idx = cbits & 0x3;
                return MF_TASK_SDCCH4_0 + lch_idx;

diff --git a/src/target/firmware/layer1/mframe_sched.c b/src/target/firmware/layer1/mframe_sched.c
index 8e92b93..30cd03f 100644 (file)
--- a/src/target/firmware/layer1/mframe_sched.c
+++ b/src/target/firmware/layer1/mframe_sched.c
@@ -197,6 +197,67 @@ static const struct mframe_sched_item mf_sdcch8_7[] = {
        { .sched_set = NULL }
 };
 
+/* TCH */
+#define TCH    tch_sched_set
+#define TCH_A  tch_a_sched_set
+
+static const struct mframe_sched_item mf_tch_f_even[] = {
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  0 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  1 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  2 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  3 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  4 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  5 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  6 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  7 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  8 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  9 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr = 10 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr = 11 },
+       { .sched_set = TCH_A, .modulo = 26, .frame_nr = 12 },
+       { .sched_set = NULL }
+};
+
+static const struct mframe_sched_item mf_tch_f_odd[] = {
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  0 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  1 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  2 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  3 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  4 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  5 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  6 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  7 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  8 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  9 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr = 10 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr = 11 },
+       { .sched_set = TCH_A, .modulo = 26, .frame_nr = 25 },
+       { .sched_set = NULL }
+};
+
+static const struct mframe_sched_item mf_tch_h_0[] = {
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  0 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  2 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  4 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  6 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  8 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr = 10 },
+       { .sched_set = TCH_A, .modulo = 26, .frame_nr = 12 },
+       { .sched_set = NULL }
+};
+
+static const struct mframe_sched_item mf_tch_h_1[] = {
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  1 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  3 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  5 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  7 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr =  9 },
+       { .sched_set = TCH,   .modulo = 13, .frame_nr = 11 },
+       { .sched_set = TCH_A, .modulo = 26, .frame_nr = 25 },
+       { .sched_set = NULL }
+};
+
+/* Test TX */
 static const struct mframe_sched_item mf_tx_all_nb[] = {
        { .sched_set = NB_QUAD_FH_UL, .modulo = 4, .frame_nr = 0 },
        { .sched_set = NULL }
@@ -222,6 +283,11 @@ static const struct mframe_sched_item *sched_set_for_task[32] = {
        [MF_TASK_SDCCH8_6] = mf_sdcch8_6,
        [MF_TASK_SDCCH8_7] = mf_sdcch8_7,
 
+       [MF_TASK_TCH_F_EVEN] = mf_tch_f_even,
+       [MF_TASK_TCH_F_ODD]  = mf_tch_f_odd,
+       [MF_TASK_TCH_H_0]    = mf_tch_h_0,
+       [MF_TASK_TCH_H_1]    = mf_tch_h_1,
+
        [MF_TASK_UL_ALL_NB] = mf_tx_all_nb,
 };
 
@@ -275,6 +341,16 @@ uint8_t mframe_task2chan_nr(enum mframe_task mft, uint8_t ts)
        case MF_TASK_SDCCH8_7:
                cbits = 0x08 + 7;
                break;
+       case MF_TASK_TCH_F_EVEN:
+       case MF_TASK_TCH_F_ODD:
+               cbits = 0x01;
+               break;
+       case MF_TASK_TCH_H_0:
+               cbits = 0x02 + 0;
+               break;
+       case MF_TASK_TCH_H_1:
+               cbits = 0x02 + 1;
+               break;
        case MF_TASK_UL_ALL_NB:
                /* ERROR: cannot express as channel number */
                cbits = 0;