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Fix SBIS etc trace output.
[simavr]
/
simavr
/
sim
/
sim_core.c
2011-02-21
Sami Liedes
Fix SBIS etc trace output.
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2011-02-20
Michel Pollet
Merge git://gitorious.org/~luki/simavr/lukis-simavr...
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2010-10-12
Michel Pollet
core: Added a bit of documentation
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2010-08-31
Michel Pollet
misc: Fixed clang static analizer warnings
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2010-08-25
Michel Pollet
core: CALL/RET instructions fix
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2010-07-05
Michel Pollet
core: Fix SBRS/C for 32 bits instructions
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2010-07-05
Michel Pollet
core: Fix MULS register
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2010-04-14
Michel Pollet
core: Fixes SBCI
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2010-04-04
Michel Pollet
core: Add support for RAMPZ and refactor instructions
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2010-01-06
Michel Pollet
core: Simplify changes to SREG
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2010-01-06
Michel Pollet
core: Add watchdog timer support
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2009-12-26
Michel Pollet
core: Shuffled code around
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2009-12-24
Michel Pollet
SPM: Added Self Programming Instruction & Support
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2009-12-23
Michel Pollet
core: No longer crash if "codeline" is missing
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2009-12-23
Michel Pollet
comments: What don't you typo the comments, too ?
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2009-12-15
Michel Pollet
Added support for IRQ triggers on any IO register
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2009-12-14
Michel Pollet
Disable the debugging traces
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2009-12-04
Michel Pollet
Many more changes, timed callbacks etc
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2009-12-02
Michel Pollet
GDB working, some more source massaging
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2009-11-30
Michel Pollet
Cores, decoder, uart, ioports - lots of changes
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2009-11-24
Michel Pollet
Initial Commit
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